Verification Technology Spring 2008
Verification Technology Spring 2008
Related Courses:
Programming Theory (Parosh Abdulla):
Verification Technology
Spring 2008
lecture 1
Bengt Jonsson
Lecture 1
Administrative
Goal:
Modeling, Specifying, and Analyzing concurrent, parallel,
and distributed algorithms, systems, and programs.
Contents:
Modeling parallel systems (as transition systems)
Specifying requirements and correctness properties
Algorithms for automatically checking that a model
satisfies a property
Instructors:
Bengt Jonsson, room 1435 bengt(at)it.uu.se
Mayank Saksena, room 1137 mayanks(at)it.uu.se
Course page
http://www.it.uu.se/edu/course/homepage/verteknik/vt08/
Examination:
5 homework exercises (solved in pairs)
Final exam on the topics covered in lectures.
SPIN
You must use SPIN for the exercises.
Installed at /stud/docs/kurs/ReactiveSystems/bin/spin
XSPIN at /stud/docs/kurs/ReactiveSystems/bin/xspin
Further material at http://spinroot.com/spin/
Lecture 1
Course Material
Lecture 1
Application to examples
Lecture 1
Examination
Homeworks, to be solved in pairs. mandatory
Final exam
Each counts for half of your final grade.
HOW TO DO WELL:
Lecture 1
Verification
Lecture 1
Verification
COURSE OVERVIEW:
What problems can be solved?
|=
conforms
Web server
implementation
Protocol standard
Functional spec.
..
Correctness
properties
Absence of
Run-time errors
deadlocks
Memory leaks
Protocol service
..
Lecture 1
Lecture 1
10
Programming languages
Development environments/Libraries
Software architectures
Detailed design
Better Processes
coding
testing
deployment
Lecture 1
11
Lecture 1
12
Requirements
Where most design
errors are made
Where most
design errors are
found
testing
deployment
13
Lecture 1
Lecture 1
Lecture 1
Detailed design
coding
testing
deployment
Lecture 1
Lecture 1
16
Requirements
High level design
14
Implement your
model, and spend
effort to check
conformance to the
model
17
Checking correctness of
Communication protocols
Distributed Algorithms
Controllers
Hardware circuits
Embedded and real-time systems and software
e.g.,
Absence of race conditions, deadlocks, livelocks, priority inversions,
proper synchronization, .
Model checking is the appropriate technique
when there are many many different
scenarios of interaction between components
in a system
Lecture 1
18
The objective is to have tools that can help a developer find errors and gain
confidence in her/his design. That is achievable
start
y1;y2:=x1,x2
y1==y2
print(y1)
stop
N
y1>y2
Y
y1:=y1-y2
y2:=y2-y1
19
Lecture 1
20
Lecture 1
WY3
start
start
y1,y2:=x1,x2
y1;y2:=x1,x2
y1==y2
Y
y1==y2
print(y1)
stop
N
N
Y
y1:=y1-y2
y1>y2
y1>y2
Y
print(y1)
stop
y1:=y1-y2
N
y2:=y2-y1
y2:=y2-y1
21
Lecture 1
WY4
22
Lecture 1
WY5
start
start
x1>0, x2>0
y1,y2:=x1,x2
x1>0, x2>0
y1,y2:=x1,x2
Y
print(y1)
stop
y1==y2
N
Y
y1:=y1-y2
y1>y2
Y
print(y1)
stop
N
N
y2:=y2-y1
Lecture 1
y1:=y1-y2
y1=gcd(x1,x2)
23
y1>y2
N
y2:=y2-y1
y1=gcd(x1,x2)
24
Slide 22
WY3
Slide 23
WY4
Slide 24
WY5
n := n0;
i := n;
while (i <> 0 ) do
j := 0;
while (j <> i) do
j := j + 1
od;
i := i - 1
od
25
Lecture 1
26
Lecture 1
Yes!
Model
Checker
implies that j does not overflow
Property:
No!
Error trace
27
Lecture 1
Lecture 1
28
Promela
int x, y, z;
Model: M
Yes!
Model
Checker
Property:
z = Pid;
if (x != Pid)
goto busywait;
No!
Error trace
y = Pid;
if (z != Pid)
goto busywait;
}
Promela/
Temporal Logic
SPIN
Lecture 1
void unlock()
{
x = 0;
y = 0;
z = 0;
}
29
Lecture 1
30
while(1) {
printf("MAIN: cointuing subroutine thread\n"); fflush(stdout);
thr_continue(thread_id);
printf("MAIN: suspending self\n"); fflush(stdout);
thr_suspend(main_id);
}
return(0);
}
void *tread_sub(void *arg)
{
thread_t thread_id;
thread_t main_id = (thread_t) arg;
thread_id = thr_self();
while(1) {
printf("THREAD: cointuing main thread\n"); fflush(stdout);
thr_continue(main_id);
printf("THREAD: suspending self\n"); fflush(stdout);
thr_suspend(thread_id);
}
return((void *)0);
}
Lecture 1
31
Lecture 1
32
Hippies problem
18: main(0):[Suspend_main = 1]
spin: trail ends after 18 steps
#processes 2:
18:
proc 0 (main) line
5 (state 7) (invalid end state)
Printf("MAIN: continuing subroutine thread\n");
18:
proc 1 (thread) line 20 (state 7) (invalid end state)
Printf("THREAD: continuing main thread\n");
global vars:
bit
Suspend_main:
1
bit
Suspend_thread:
1
bit
arg: 0
10
20
25
...
Lecture 1
33
Lecture 1
Lecture 1
34
35
Lecture 1
36
Reachable?
(bug?)
Example of Model
Remaining Problems
Constructing a Model
not so easy, this course will make you experts
Conformance testing
Static program analysis
Automated code generation
37
Lecture 1
38
Lecture 1
idle
Scheduling priority
Saving data to memory has higher priority than processing data
Low priority process cannot execute when high priority process is ready
to execute or executes
run
wait
39
Lecture 1
40
Lecture 1
idle
run
l := 1
High@idle -> l := 1
run
run
wait
wait
l = 1 -> l := 0
run
wait
wait
High@idle /\ l = 1
Lecture 1
41
idle
Lecture 1
->
l := 0
42