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Vlsi Ratioed (Pseudo) Logic

Ratioed logic, also known as pseudo-nMOS logic, uses weaker pull-up devices and stronger pull-down devices to reduce the number of transistors needed for a logic function compared to complementary CMOS, but results in increased power dissipation and reduced noise margins. It replaces the pull-up network with a single always-on PMOS load transistor and uses a pull-down network to realize the logic function, with the output determined by the balance of strengths between the load and pull-down devices. The voltage at the output depends on the ratio of the strengths of the pull-up to pull-down devices, requiring optimization of device widths to minimize static power dissipation while maintaining a low output voltage for logic 0.

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1K views3 pages

Vlsi Ratioed (Pseudo) Logic

Ratioed logic, also known as pseudo-nMOS logic, uses weaker pull-up devices and stronger pull-down devices to reduce the number of transistors needed for a logic function compared to complementary CMOS, but results in increased power dissipation and reduced noise margins. It replaces the pull-up network with a single always-on PMOS load transistor and uses a pull-down network to realize the logic function, with the output determined by the balance of strengths between the load and pull-down devices. The voltage at the output depends on the ratio of the strengths of the pull-up to pull-down devices, requiring optimization of device widths to minimize static power dissipation while maintaining a low output voltage for logic 0.

Uploaded by

MasudRana
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Ratioed Logic (Pseudo nMOS)

Ratioed logic is an attempt to reduce the number of transistors required to implement


a logic function at the cost of reduced robustness and extra power dissipation.
Uses weak pull-up devices and stronger pull-down devices.
The pull-up network (PUN) is replaced with a single unconditional load device- a
single PMOS transistor whose gate is grounded and so is always ON, that pulls the
o/p high
PDN realizes the logic function and the load PMOS pulls o/p up.

- In complementary CMOS, PMOS devices are sized larger to compensate for slower
mobility and to realize symmetric delay. Large PMOS devices add large input
capacitances and require large logical effort.
- Pseudo NMOS reduces i/p capacitance and hence improve logical effort but require
correct ratio of pull-up and pull-down strength.
- No. of transistors = N+1

When a particular set of i/p require a high o/p, PDN is inactive,


the load PMOS charges the o/p high.
When a particular set of i/p require a low o/p, PDN is active,
high o/p attempts to discharges to Vss, but there is a fight
between PUN (load) and PDN.
There will be some static power dissipation when i/p require
low o/p (when PDN is active) and VOL is not 0. There is a direct
current path between VDD and GND in pull-down.
This results in reduced noise margin and non-zero static power
dissipation

Consider a Pseudo NMOS inverter


When A=1, PDN active, load PMOS is always ON.
Assuming current IDN and IDP are equal,
If VOL is assumed to be small, PMOS is saturated when NMOS is
in linear
N

2
2
2V DD VTN VOL V IL P V DD VTP
2
2

2
2
VOL V DD VTN V DD VTN N V DD VTP
P

N
P

Value of VOL depends on the ratio of

Increasing ratio decreases VOL


Because of this characteristics, pseudo NMOS is a type of ratioed logic, where
relative device sizes set VOL or VOH
This is in contrast to complementary CMOS where VOL and VOH do not depend on
transistor sizes
To make VOL as small as possible, PMOS should be sized smaller than NMOS devices
Rload>RPDN and load<PDN, to keep Noise Margin low
Generally PMOS width is kept of PDN width as a compromise between noise
margin and speed

Example:
Consider a CMOS process with VDD=5V, VTN=0.7V, VTP=0.87V, kn=150uA/V2,
kp=68uA/V2, where kn/kp is called the process conductance parameter (COX). A pseudo
NMOS inverter is sized with (W/L)n=4 and (W/L)p=6
N
408
(V DD VTP ) 2 4.3 ( 4.3) 2
( 4.2) 2 1.75V
P
600
This above is too large to be interpreted as logic 0.
If we increase (W/L)n=8 and decrease (W/L)p=2,
VOL VDD VTN (V DD VTN ) 2

VOL 4.3

(4.3) 2

136
( 4.2) 2 0.24V
1200

which is acceptable as it is below the voltage Vin=VTN that turns NMOS devices ON (this
is needed so that low o/p does not turn on next stage)
If the pull-up is too weak, the rising delay will be too slow.

Pseudo NMOS logic are useful for large fan-in circuits but Ps0 limits their use.
When area is most important, the reduced transistor count as compared to
complementary CMOS is quite attractive.
Pseudo NMOS is well-suited for NOR structures (used in RAMs, PLAs)
The logical effort is independent of inputs in wide NORs and is useful for fast wide
NOR gates on NOR-based structures like ROMs and PLAs when power permits.

Pseudo-NAND vs Pseudo-NOR

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