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Lecture #7
No
lab next week
Midterm on Fr Febr 19 6:30-8pm in 2060 Valley
LSB
Review
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Session: TBA (most likely on Th)
Lecture #7
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Last
lecture
Optimizing complex logic
Todays
lecture
Applying what we learned on memory
decoders
Reading
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(Ch 6.2, 12.1,12.3)
Lecture #7
tpgate = tinv (p + LEf)
Measure everything in units of tinv (divide by tinv):
p intrinsic delay (kg) - gate parameter f(W)
LE logical effort (k) gate parameter f(W)
f electrical effort (effective fanout)
Normalize everything to an inverter:
LEinv =1, pinv =
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Compute
the path effort: PE = (LE)BF
Find the best number of stages N ~ log4PE
Compute the effective fanout/stage EF = PE1/N
Sketch the path with this number of stages
Work either from either end, find sizes:
Cin = Cout*LE/EF
Reference: Sutherland, Sproull, Harris, Logical Effort, Morgan-Kaufmann 1999.
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LE=10/3
1
LE = 10/3
P= 8 + 1
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LE=2
5/3
LE = 10/3
P=4 + 2
LE=4/3
5/3
4/3
1
LE = 80/27
P= 2 + 2 + 2 + 1
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Branching effort:
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Branching Example 1
15
90
5
15
90
LE
FO
PE
SE1
SE2
PE
=
=
=
=
=
=
1
90/5 = 18
18 (wrong!)
(15+15)/5 = 6
90/15 = 6
36, not 18!
Introduce new kind of effort to account for branching:
Con-path + Coff-path
Branching Effort:
b=
Con-path
Path Branching Effort:
B=
Now we can compute the path effort:
Path Effort: PE = LEFOB
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Branching Example 2
Select gate sizes y and z to minimize delay from A to B
Logical Effort:
LE = (4/3)3
Electrical Effort:
FO = Cout/Cin = 9
Branching Effort:
B = 23 = 6
Path Effort:
PE = LEFOB= 128
Best Stage Effort:
SE = PE1/3 5
Delay:
D = 35 + 32 = 21
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Work backward for sizes:
9C(4/3)
= 2.4C
5
3z(4/3)
y=
= 1.9C
5
z=
Lecture #7
Compute
the path effort: PE = (LE)BF
Find the best number of stages N ~ log4PE
Compute the effective fanout/stage EF = PE1/N
Sketch the path with this number of stages
Work either from either end, find sizes:
Cin = Cout*LE/EF
Reference: Sutherland, Sproull, Harris, Logical Effort, Morgan-Kaufmann 1999.
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Schematic
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Physical
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Capacitance-only
All-inclusive model
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Interconnect
and its parasitics can affect all of
the metrics we care about
Cost, reliability, performance, power consumption
Parasitics
associated with interconnect:
Capacitance
Resistance
Inductance
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SLocal = STechnology
SGlobal = SDie
From Magen et al., Interconnect Power Dissipation in a Microprocessor
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Better Interconnect Materials
e.g. copper, silicides
More
Interconnect Layers
reduce average wire-length
Selective
Technology Scaling
(More later)
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Silicides: WSi 2, TiSi 2, PtSi 2 and TaSi
Conductivity: 8-10 times better than Poly
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Analysis method:
Break the wire up into segments of length dx
Each segment has resistance (r dx) and
capacitance (c dx)
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Model the wire with N equal-length segments:
For large values of N:
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