INSTITUTE OF COMPUTER TECHNOLOGY

UNIVERSITY OF COLOMBO, SRI LANKA

DEGREE OF BACHELOR OF INFORMATION TECHNOLOGY (EXTERNAL)

Academic Year 2000/01 - 1st Year Examination – Semester 2

IT2101 – Computer Architecture and Operating Systems

Model Question Paper – Academic Year 2001/02
01st September, 2001 (Revised Examination Paper)
(TWO HOURS)

Important Instructions :
• The duration of the paper is 2 (two) hours.

• The medium of instruction and questions is English.

• The paper has 45 questions and 12 pages.

• All questions are of the MCQ (Multiple Choice Questions) type.

• All questions should be answered.

• Each question will have 5 (five) choices with one or more correct answers.

• All questions will carry equal marks.

• There will be a penalty for incorrect responses to discourage guessing.

• The mark given for a question will vary from –1 (All the incorrect choices are
marked & no correct choices are marked) to +1 (All the correct choices are
marked & no incorrect choices are marked).

• Answers should be marked on the special answer sheet provided.

• Note that questions appear on both sides of the paper.

If a page is not printed, please inform the supervisor immediately.

• Mark the correct choices on the question paper first and then transfer them
to the given answer sheet which will be machine marked. Please
completely read and follow the instructions given on the other side
of the answer sheet before you shade your correct choices.

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1) What is the most compact form of the following Boolean expression?
__ _ _ _ _
F = A⋅ B⋅ C + A⋅ B⋅ C + A⋅ B⋅ C + A⋅ B⋅ C
_ _
(a) (A⋅ B + A⋅ B) ⊕ C (b) A ⊕ B ⊕ C (c) (A ⊕ B) ⊕
_ __ C
(d) (A ⊕ B) C + C (AB + (e) A ⊕ (B ⊕ C)
AB) _
2) The Boolean expression F = P + Q⋅ R is equivalent to _
_ _____ _____
_ _
(a) (P + Q) ⋅ (P + R) (b) (P + Q) ⋅ (P + R) (c) P + (Q + R)
(d) P⋅ (Q + R) (e) P + Q + R

3) A 2:4 decoder has 2 inputs A and B (B is the least significant bit) and 4 outputs F 0, F1, F2 and F3 (F0
is the least significant bit). Consider the following Boolean expressions.
_ _ _ _
(i) F0 = A⋅ B ; F1 = A⋅ B ; F2 = A⋅ B ; F3 = A⋅ B
_ _ _ _
(ii) F0 = A⋅ B ; F1 = A⋅ B ; F2 = A⋅ B; F3 = A⋅ B
_ _ _ _
(iii) F0 = A + B ; F1 = A + B ; F2 = A + B ; F3 = A + B

What could be a valid Boolean expression that could implement the decoder logic?

(a) Only (i) is correct (b) Only (ii) is correct

(c) Only (i) and (ii) are correct (d) Only (iii) is correct
(e) Insufficient data available to derive expression

4) What can be said about the binary equivalent of the hexadecimal number 0x3A5E?

(a) Undefined since the symbol x is undefined (b) 0011 1010 0101 1110
(c) 0011 1011 0101 1111 (d) 0011 1001 0101 1101
(e) 0011 1010 0101 1101

5) Consider the following three statements about R-S Flipflops and J-K Flipflops.

(i) J-K Flipflops do not have the uncertainty associated with R-S Flipflops for the
R = S = 1 state, in its J = K = 1 state
(ii) If J ≠ K, the next output state of the J-K Flipflop will be same as the current state
(iii) When R = 1 and S = 0, the next output state of the R-S Flipflop will be made 0
irrespective of the current output state

What statement (s) is/are correct about R-S Flipflops and J-K Flipflops?

(a) Only (i) (b) Only (iii) (c) Only (i) and
(iii)
(d) Only (ii) (e) All

6) In Flynn’s classification of computers, the vector and array classes of machines belong to:

(a) Single instruction/single data category

(b) Single instruction/multiple data category
(c) Multiple instruction/single data category
(d) Multiple instruction/multiple data category

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 (e) An undefined category as yet.

7) Consider the following three statements.

(i) A multilevel view of a computer system simplifies the design of a complex system
by identifying specific functionalities for each level.
(ii) The Instruction Set Architecture (ISA) level defines the characteristics of the CPU.
(iii) One of the functions of the operating system machine level is to enforce a
separation between the users tasks and the privileged tasks.

Which of the following statement (s) is/are true about the multilevel machine view point?
(a) Only (i) is true (b) Only (i) and (iii) are true (c) Only (iii) is true
(d) All are true (e) None is true

8) In a general purpose computer system the CPU, the main memory and the cache may be
interconnected via one or more shared system bus(es). However, input/output devices (eg. Hard
disk, network interfaces) may only be connected to the system bus through an I/O controller. The
following are four statements regarding the requirement for an I/O controller.

(i) The capacities of I/O devices are magnitude order larger than that of main memory
and hence direct interfacing is impossible.
(ii) The response times of I/O devices are magnitude order slower than that of CPU and
hence direct interfacing is impossible.
(iii) It is always better to off load the I/O processing to a secondary processor on the I/O
controller board than to depend on the primary CPU for I/O processing.
(iv) The variety of I/O devices in the market requires that a separate I/O controller exist
for each device.

What statement(s) best explain the requirement for an I/O controller?

(a) Only (i) is true (b) Only (iii) is true

(c) Only (ii) and (iii) are true (d) Only (iii) and (iv) are true
(e) Only (ii), (iii) and (iv) are true

9) The following are four statements regarding what a CPU with only a set of 32 bit registers can
perform.

(i) Hold and operate on 32 bit integers

(ii) Hold and operate on 16 bit integers
(iii) Hold and operate on 64 bit floating point arithmetic
(iv) Hold and operate on 16 bit UNICODE characters

Which of the following is/are true about such a CPU?

(a) All are true (b) Only (i), (ii) and (iii) are true
(c) Only (i), (ii) and (iv) are true (d) Only (i), (iii) and (iv) are true
(e) (i) and (iii) are only true

10) The following are four statements about Reduced Instruction Set Computer (RISC) architectures.

(i) The typical RISC machine instruction set is small, and is usually a subject of a
CISC instruction set.
(ii) No arithmetic or logical instruction can refer to the memory directly.
(iii) A comparatively large number of user registers are available.
(iv) Instructions can be easily decoded through hard-wired control units.

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 Which of the above statements is/are true?

(a) (i) and (iii) only (b) (i), (iii) and (iv) (c) (i), (ii) and (iii)
only only
(d) (i), (ii) and (iv) only (e) all are true.

11) What statement(s) is/are true about RISC processors’ claimed advantages over CISC processors?

(a) Keeping regularly accessed variables in registers as opposed to keeping them in

memory facilitates faster execution.
(b) RISC CPUs outperform CISC CPU’s in procedural programming environments.
(c) Instruction pipelining has helped RISC CPU’s to attain a target of 1 cycle per
instruction.
(d) It is easier to maintain the “family concept” in RISC CPUs.
(e) RISC CPUs generally out perform CISC processors in all application
environments: procedural, object oriented, networking etc.,

12) A certain processor executes the following set of machine instructions sequentially.

MOV R0, # 0
MOV R1, 100(R0)
ADD R1, 200(R0)
MOV 100(R0), R1

Assuming that memory location 100 contains the value 35 (Hex), and the memory location 200
contains the value A4 (Hex), what could be said about the final result?

(a) Memory location 100 contains value A4

(b) Memory location 100 contains value DA
(c) Memory location 100 contains value D9
(d) Memory location 200 contains value 35
(e) Given data is insufficient to decide

13) A stack-based processor executes the following set of machine instructions sequentially.

PUSH 100
PUSH 200
ADD
POP 300

Assuming that
(i) memory location 100 contains the value 53 (Hex) and memory location 200
contains the value 4C (Hex),
(ii) the stack is byte organised and the stack pointer is at 00FF, and that
(iii) all PUSH and POP instructions have a memory operand.

Which of the following could the final result be?

(a) Memory location 300 contains the value 9F

(b) Memory location 00FD contains the value 9F
(c) Memory location 00FF contains a value 100
(d) Memory location 00FE contains a value 200
(e) Memory location 00FD contains a value 300.

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14) In a register/memory type CPU, the instruction lengths are typically variable. This presents a
problem when the program counter (PC) of the CPU is incremented during the Fetch-Execute cycle.
What statement(s) is/are true with regard to PC incrementing?

(a) PC is incremented by the largest possible fixed value, irrespective of the

variability of the instruction.
(b) Increment value is known when the current instruction is decoded within the IR.
(c) Increment value is known when the current instruction has completed execution.
(d) The binary loader overcomes the problem by positioning instructions at word
boundaries so that PC can be incremented by a constant amount.
(e) PC incrementing method is implementation dependent.

15) When a particular high-level language code fragment is compiled, it produces the following set of
machine instructions.

MOV R1, #j
BEQZ R1, label
MOV R2, #0
JMP exit
label : MOV R2, R3
exit : …

Assuming that values p and q are stored in registers R2 and R3 respectively, to which high-level
language code fragment does the above machine code closely correspond?

(a) if (j ≥ 0) p = q (b) if (j ==0) q = p (c) if (j ==0) p = q

else p = 0; else q = 0; else p = 0;
(d) if (j == 0) p = 0 (e) if (j ≥ 0) p = 0
else p = q; else p = q;

16) A non-pipelined RISC CPU consists of five functional stages: IF, ID, EX, MEM and WB. The
following is a machine instruction.

ADD R3, R2, R1

According to the standard notation, what micro instruction(s) may fall within the MEM stage for
the above machine instruction gives that ALUout, A, B and C are temporary buffers?

(a) ALUout  A + B (where A = R1, B= R2 previously)

(b) ALUout  Mem[A + B] (where A = R1, B = R2 previously)
(c) C  ALUout (where R3  C later)
(d) IR  Mem [MAR]
(e) There will not be any micro instructions within this stage for the given machine
instruction

17) Most micro instructions corresponding to a given machine instruction, such as PC increment and
temporary buffer loading (Eg., A, B, MAR and MDR) among others, can each be carried out
typically within a 1 clock cycle. Certain other micro-instructions may however take more than 1
clock cycle to execute. Which of the following is/are an example(s) of a micro instruction(s) (or a
pair/triple) that may take more than 1 clock cycle to execute?

(a) IR  Mem[MAR] (where MAR = PC previously)

(b) Mem[MAR]  MDR;

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 (c) MDR  Mem[MAR] (where MAR = ALUout previously)
(d) PC  PC + 4 concurrently with A  R1 and B  R2
(e) C  MDR

18) Which of the following statements is/are true about CISC architectures?

(a) CISC machine instructions may include complex addressing modes, which
require many clock cycles to carry out
(b) CISC control units are typically micro-programmed, allowing the instruction set
to be more flexible
(c) In the CISC instruction set, all arithmetic/logic instructions must be register
based
(d) CISC architectures may perform better in network centric applications than RISC
(e) Various compiler optimizations are more relevant for RISC than for CISC
architectures.

19) A certain statistical observation made on a CPU executing a piece of code shows that the code has
50% arithmetic/logic machine instructions each taking 1 clock cycle, 30% load /store (memory
reference) instructions each taking 2.0 clock cycles and 20% branch instructions each taking 1.5
clock cycles. What can be said about the average CPI (cycles per instruction) value of the
processor?

(a) Insufficient data to (b) 1.4 (c) 4.5

calculate
(d) 0.71 (e) 1.5

20) The word length of a CPU is defined as:

(a) the maximum addressable memory size

(b) the width of a CPU register (integer or float point)
(c) the width of the data bus
(d) the width of the address bus
(e) the number of general purpose CPU registers

21) The following are three statements about the “locality of reference” principle used in memory
systems.

(i) Says it is more likely that an already accessed memory location is accessed further,
and, it is more likely that surrounding (adjacent) memory locations will also be
accessed
(ii) An observation equally widely used to implement virtual memory and cache
memory systems
(iii) Says that the bytes of a word be interleaved on several physical memory modules
for better performance

Which of them is/are true?

(a) only (i) is true (b) only (ii) is true (c) only (iii) is
true
(d) only (i) and (ii) are true (e) only (i) and (iii) are
true

22) Which of the following statements is/are true about dynamic RAM?

(a) Dynamic RAMs are faster than static RAMs

(b) Power consumption of dynamic RAMs is more than that of static RAMs
(c) Gate density of dynamic RAMs is higher than that of static RAMs

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 (d) Dynamic RAMs require a memory refresh cycle after each memory read cycle
(e) Main memory of a general purpose computer system is usually built using
dynamic RAMs

23) Which of the following statements is/are true about the cache memory system and the virtual
memory system found in a computer system?

(a) Both systems employ the ‘locality of reference’ principle for their respective
implementations
(b) A ‘cache miss’ is handled primarily by the hardware, while a ‘page fault’ is
handled primarily by the operating system
(c) A cache miss may not cause the running process (which caused the miss) to be
context switched, but a page fault will definitely do so.
(d) A page (or block) replacement algorithm is a necessary requirement in virtual
memory management, but not essential in cache management
(e) Cache miss penalties are several orders of magnitude larger than main memory
miss penalties.

24) In a two level memory hierarchy, the access time of the cache memory is 12 nano-seconds and the
access time of the main memory is 1.5 micro-seconds. The hit ratio is 0.98. What is the average
access time of the two level memory system?

(a) 13.5 nsec (b) 42 nsec (c) 756 nsec

(d) 41.76 nsec (e) 30.24 nsec

25) A computer system with a cache may face an unusual problem compared with that without a cache,
when it comes to I/O operations. Consider the following three statements.

(i) CPU may be reading and writing to the cache, while I/O controller may be reading
and writing to main memory, making the data held in cache and main memory
inconsistent.
(ii) Activities of cache block replacement and page replacement may clash with each
other
(iii) As long as both CPU and the I/O controllers are only ‘reading’ the contents of
cache and main memory respectively, there will not be any problem

Which of he following statements is/are true?

(a) Only (i) is true (b) Only (i) and (ii) are (c) Only (i) and (iii) are
true true
(d) All are true (e) None is true

26) What is signified by the term Direct Memory Access (DMA)?

(a) A less efficient I/O mechanism than ‘interrupts’ for single byte transfer
operations
(b) A more efficient I/O mechanism than ‘interrupts’ for data block (multi-byte)
movements
(c) A class of multiprocessor computers
(d) A mechanism used by the I/O system to by-pass the memory management
functions of an operating system
(e) A more efficient I/O mechanism than ‘programmed I/O’ for single byte transfer

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 operations.

27) Which of the following statements is/are true with regard to fully associative and direct mapped
cache organisations?

(a) Use of hardware comparators make fully associative caches much faster, but
more expensive than direct mapped caches
(b) Direct mapped caches do not need a cache block replacement policy, whereas
fully associative caches do
(c) In a fully associative cache, the full address is stored alongside the data block
(d) A direct mapped cache is organized according to an ‘index’, and the ‘tag’ part of
the memory address is stored alongside the data block
(e) Direct mapped caches may produce more misses if programs refer to memory
words that occupy a single tag value.

28) Amdahl’s law is expressed by the equation S = n/{f + n(1-f)} where, S is the speedup of the
multiprocessor system, n is the number of processors and f is the fraction of the task that has
inherent concurrency. Which of the following statements is/are true with regard to Amdahl’s law?

(a) As n increases, S increases linearly

(b) As n increases, S increases and reaches a limit defined by f
(c) As f approaches 1, S becomes directly proportional to n
(d) As f decreases, S becomes independent of n
(e) Provides an approximation to the performance obtainable from a MIMD
multiprocessor.

29) Which of he following statements is/are true with regard to instruction pipelining?

(a) The basic goal of instruction pipelining is to achieve a CPI of 1

(b) Instruction set architectures having simple registry/register addressing modes can
be easily pipelined than those having complex addressing modes
(c) By the use of hardware special features and compiler design techniques, pipeline
hazards can be removed
(d) CISC CPUs can be more easily pipelined than RISC CPUs
(e) The basic goal of instruction pipelining is to achieve a CPI of more than 1.

30) What is/are the major objective(s) of an operating system?

(a) To act as a resource manager for multiple tasks running on the CPU, the memory
and disk resources
(b) To provide a programming interface to the user
(c) To act as an uniform abstract machine on top of a variety of different hardware
platforms
(d) To act as a File server to client machines requiring such service
(e) To enable loading and execution of binary code with minimum intervention by
the user.

31) In a multitasking kernel, a running process makes a system call to read some file blocks. Which of

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 the following statements is/are true about the process in particular and the system in general?

(a) Calling process enters the kernel mode from the user mode to execute the system call
(b) Calling process moves to the ‘blocked’ state due to the I/O nature of the system call;
another process in the ‘ready to run queue’ is scheduled to be run
(c) Transfer of file blocks is undertaken by an I/O thread
(d) Calling process continues to execute in the user mode
(e) Once the required file blocks are transferred to main memory, the I/O thread
interrupts the kernel, which moves the calling process from ‘blocked’ state to ‘ready
to run’ state.

32) Which of the following statements comparing the context of a thread with that of a process is/are
true?

(a) Two processes will not share any context; two threads of a same process will only
share the data and the code (text) areas of the context
(b) Two processes will not share any context; two threads of a same process will share
the data, code (text) and the stack areas of the context
(c) Two processes will share the data and the code (text) areas of the user context; two
threads of a same process will only share the register context
(d) The overhead involved in context switching for processor is much higher than that
for threads
(e) The overhead involved in context switching for threads is much higher than that for
processes

33) Under which of the following conditions could a running process be transferred from the ‘running’
state to the ‘blocked’ state?

(a) a page fault (b) a cache miss

(c) a file system call causing an I/O (d) A SLEEP inter process system
operation call
(e) a WAKE UP inter process system call

34) A certain task is multithreaded in such a way that it is supported by two kernel threads where each
kernel thread is supporting more than one user thread. Which of the following statements is/are
true about this scenario?

(a) the task can utilize the combined power of more than one CPU, if CPUs are
available
(b) if a user thread makes a blocking system call, the corresponding kernel thread
blocks but the task is still able to continue through the remaining kernel thread
(c) the task could have been programmed using a thread library such as POSIX threads
or Java threads
(d) if a user thread makes a blocking system call, the corresponding kernel thread
blocks and the task will also be blocked
(e) kernel threads capability needs to be built into the operating system, and cannot be
provided by a system call library

35) Semaphores can be used to enforce mutual exclusion and synchronization between processes
interacting over shared data and variables. Which of the following statements is/are true about
semaphores in this regard?

(a) The operations UP(S) (or SIGNAL(S)) and DOWN(S) (or WAIT(S)) need to be atomic
(b) If a process calling DOWN(S) causes ‘S’ to go negative, the process calls itself SLEEP()
and goes to ‘blocked’ state
(c) A process exiting the critical section will call UP(S) which will WAKEUP( ) a blocked
process awaiting entry to the critical section

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 (d) For short duration critical sections, the context-switching overhead caused by
semaphores is significantly higher than ‘busy-wait’ solutions.
(e) ‘Busy-wait’ solutions to the critical section are typically implemented using machine
instructions that execute in the kernel mode.

36) One needs a good practical example of a “producer-consumer” type problem from among the
following.

(i) a multithreaded audio server, where a thread writes digitized sound into a circular
buffer and another thread reads it over to a web page
(ii) a printer spooler where files are spooled on to the printer queue, to be taken and
printed by the printer driver
(iii) a shared data base updated by simultaneous queries

Which of the following is/are true of such a good practical example?

(a) Only (i) is true (b) Only (ii) is true (c) Only (i) and (iii) are true
(d) Only (i) and (ii) (e) all are true.

37) Demand paging and swapping are two widely used memory management techniques. Which of the
following statements is/are true in this regard?

(a) Moving the whole user context of a process between the main memory and the virtual
memory is known as swapping
(b) Moving pages corresponding to the user context of a process between the main memory
and the virtual memory as and when required is known as demand paging
(c) Demand paging incurs a higher overhead than swapping
(d) If both demand paging and swapping are implemented by the memory management
system, the default mechanism resorted to is demand paging
(e) When the system’s main memory space becomes comparatively smaller than the space
required to run its applications, swapping activity becomes more visible.

38) Which of the following can be said about a segmentation fault caused when a process is active?

(a) It will recover from the fault transparently to the user, by moving the required page from
the secondary memory
(b) the fault’s cause may most likely be an error in programming
(c) it will abruptly terminate the process and a core image of the process will be saved for
further observations
(d) it will cause the process to go into the ‘blocked’ state
(e) it will most likely be caused by a hardware fault.

39) Consider the following sample directory listing of a UNIX file system.

drwxr-xr-x 2 kamal wheel 512 Jun 27 12:35 robot

-rw-r- - r - - 1 kamal wheel 551596 Sept 30 1999 set_bk2.zip
drwxrwxr-x 2 kamal wheel 512 Mar 20 14:27 sida
-rwx - - - - - - 1 kamal wheel 4287659 Jun 27 12:36 a.out

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 drwxrwxr-x 13 kamal wheel 3584 Apr 24 23:01 ssh

Which of the above statements is/are true?

(a) All users of the system can read and modify the set_bk2.zip file
(b) All users of the system can read but not modify the set_bk2.zip file
(c) a.out is a program file, that can be executed by all users of the system
(d) a.out is a program file, that can be executed by only its owner
(e) All users under the ‘wheel’ group can access and create a file under the ssh directory

40) In a certain UNIX file system, the INODE data structure can contain pointers to 12 direct disk
blocks, and to a 1st indirect disk block. Given that the disk block size is 4096 bytes and that a block
pointer is 4 bytes long, what can be said about the maximum size of the file that can be stored on
this particular UNIX file system?

(a) 1072 K bytes (b) 4144 K bytes (c) 4096 K bytes

(d) 1036 K bytes (e) Insufficient information available

41) You are given that the following set of UNIX commands is issued.

% ps > file_1
% ls –l > file_2
% grep secret file_2 > file_3

Which of the following can be observed after the issue?

(a) file_2 contains the current directory list and a list of current processes
(b) Each line of file_3 if that file exists, contains the word ‘secret’
(c) file_1 contains a list of current processes
(d) file_2 contains a current directory listing
(e) file_3 contains a current directory listing with the word ‘secret’ attached.

42) If /usr/home/kamal/my_file as well as kamal/my_file denote the same file, which of

the following is/are the correct statement(s)?

(a) Current directory is /usr/home

(b) The command ‘ls ..’ will display the contents of the /usr directory
(c) The command ‘ls ..’ will display the contents of the /usr/home directory
(d) Current directory is /usr
(e) The command ‘cat kamal/my_file’ will display the contents of my_file.

43) Consider the following pseudo code fragment.

print(‘hello’);
if(fork( )== 0)
print(‘world’);

Which of the following statements best explains the outcome when the code is executed?

(a) Prints the word ‘hello’ only

(b) Prints the words ‘hello’ and ‘world’ in any order
(c) Prints the words ‘hello’ followed by ‘world’ in that order
(d) Prints the words ‘hello’ followed by two words of ‘world’ in that order
(e) Prints the words ‘hello’ and two words of ‘world’ in any order

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44) Which of the following statements is/are true about Windows NT operating system’s ability to
support DOS, Windows and UNIX applications?

(a) Windows NT does not support DOS and UNIX applications

(b) 16 bit Windows (eg. MS-Windows 3.11) and MSDOS applications are run on Virtual
DOS Machines (VDMs) provided by Windows NT
(c) Windows NT supports POSIX compliant UNIX system calls
(d) Windows NT supports 32 bit Windows applications over its native interface
(e) Windows NT does not support 32 bit Windows applications

45) Consider the following pseudo code fragment.

if (fork( ) == 0)
execl(‘/bin/date’, ‘date’, 0);
wait();

Which of the following statements best explains the outcome when the code is executed?

(a) Parent process prints the current date on screen

(b) Child process prints the current date on screen
(c) Parent waits, till the child prints the current date and the child exits
(d) Child waits, till the parent prints the current date and the parent exits
(e) execl() call replaces the child’s code area (text) by that of the /bin/date system
program

********

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