Design and Implementation of Reconfigurable

Coders for Communication Systems

Abstract Digital Communication is extensively used for a large

number of applications which includes deep space
communication, satellite communication, mobile and wireless
communication, ultra wideband applications and many more.
Coders in the form of encoders and decoders play an important
part of any digital communication system. Encoders are used on
the transmitter side of a communication system and decoders are
used on the receiver side of corresponding system. On the
transmitter side, the digitized data is processed or encoded,
followed by modulation and transmission over the medium. On
the receiver side, the data is down converted and decoded for
further processing. Different types of encoders and decoders are
reported in literature for communication systems with each type
having its own advantages and disadvantages. In this paper, a
novel attempt is made to design a reconfigurable coder system
which can be reconfigured on-the-fly to work either as an
encoder, or decoder, or both encoder and decoder depending on
the user requirements. In order to build the proposed
reconfigurable system, Convolutional encoder, Viterbi decoder,
Golay encoder and Golay decoder are employed in different
combinations for the proposed design. The proposed system is
implemented on a Virtex-5 FPGA and the performance of the
system with and without reconfigurable architecture are reported.
It is observed that 56.36% of hardware resources and 72.21% of
power are saved on using reconfigurable architecture over nonreconfigurable architecture. The proposed system can be easily
extended to include various other encoding and decoding schemes.
Keywords Convolutional; Decoders; Encoders; FPGA; Golay;
Reconfigurable; Viterbi.

I. INTRODUCTION
The main aim of digital communication is to provide errorfree data transmission and the main advantage of using digital
signal is that the errors introduced by noise during transmission
can be detected and possibly corrected. Encoders and decoders
are considered as important blocks of any digital
communication system. Encoders are used on the transmitter
side of the system for the purpose of standardization, speed,
secrecy, security and compression. Decoders are used on the
receiver side of the system to retrieve the actual message
signal. Every encoder has its corresponding decoder and
usually an encoder-decoder pair is used for designing a
communication system.
Convolutional coding is one of the most commonly used
encoder and Viterbi decoder is used for decoding.
Convolutional coding and Viterbi decoder have been
successfully used for various applications including satellite
communication in [1], for mobile communication in [2], deepspace optical communication in [3], for digital broadcasting

systems in [4], Code Division Multiple Access (CDMA) in [5],

for Ultrawideband (UWB) signalling in [6] and many more.
This has motivated the hardware implementation of
convolutional coding-Viterbi decoder pair as reported in [7-9].
Similarly block codes such as Golay encoder and decoder
are considered as efficient coders for forward error correction
with an ability to detect four errors and correct upto three
errors. Golay encoders and decoders are simple to implement
and are hence used for various applications such as multiple
error correcting codes in [10], for Synthetic Aperture Radar
(SAR) imaging systems in [11], and for wireless
communication of Software Defined Radio (SDR) in [12]. The
hardware implementation of Golay encoder-decoder pair are
reported in [13-15].
It is observed that FPGAs have come a long way from mere
glue-logic applications to design of on-board satellite systems
in [16] and design of reconfigurable systems in [17] due to
their higher level of flexibility. In this paper, design and
implementation of reconfigurable coders using Xilinx make
SRAM based Virtex-5 FPGA is proposed, wherein the
functionality of system as an encoder or decoder, or both are
reconfigured on-the-fly based on the requirements of user. The
system is also capable of reconfiguring itself to two different
encoding and decoding schemes as illustrated in Fig. 1,
wherein it may be observed that the proposed reconfigurable
system can be easily reconfigured for usage with any
application that demands these encoding and decoding
schemes.
The organization of the paper is as follows: Section II gives
an overview of the coders used for proposed work. Section III
explains the implementation of different reconfigurable
architectures for the proposed design. Experimental results and
observations of the proposed design are reported in Section IV
followed by conclusion and references.

Fig. 1. Functionality of proposed Reconfigurable Coding System

II.

OVERVIEW OF CODERS FOR PROPOSED WORK

In this section, a brief overview of different coders used for

proposed work is reported, which includes Convolutional
encoder, Viterbi decoder, Golay encoder and Golay decoder.
A.

Convolutional Encoder

The ability to perform economical soft decision decoding

on convolutional codes, as well as the flexibility to change
block length and code rate has made convolutional coding very
popular for digital communications. Convolutional encoder is
mainly characterized using three parameters i.e., k - the number
of input bits, n - the number of output bits and K - the
constraint length. The code rate for transmission is defined as r
= k/n. A generalized [n,k,K] convolutional encoder
ncoder has K-1
shift registers. The convolutional encoder used for proposed
work is shown in Fig. 2, where k=1, K=3 and n=2. Two
generator polynomials are used which are given as g0 = 101
and g1 = 111. Two outputs V0 and V1 are generated using the
generator polynomials as given in (1) and (2).
V0 = u1 u3
(1)
V1 = u1 u2 u3
(2)
where u1 represents the input to the encoder, u2 and u3
represents the output from first flip flop and second flip flop
respectively.

B.

Viterbi Decoder

The Viterbi decoder is an optimum maximum likelihood

algorithm proposed by A.J.Viterbi to decode the convolutional
codes for constraint length K 15. The Viterbi decoder
comprises of three basic units Branch metric unit, Path metric
unit and Trace back unit. Branch metric is the hamming
distance from current state to next state due to change in input.
Path metric unit summarizes branch metrics to get metrics for
2K-1 paths, one of which can eventuall
eventually be chosen as optimal.
Fig. 4 illustrates the branch metric and path metric calculation
for the proposed work. The results from these decisions are
written to the memory of a trace back unit and the trace back
unit restores an almost maximum-likelihood
likelihood pa
path from the
decisions made by the Path metric unit. Viterbi decoding is
best envisaged using a trellis diagram as shown in Fig. 5 which
contains the information of the state diagram and uses time as a
horizontal axis to show the possible paths through the states.
More details about Viterbi decoder can be had from [1
[18].

Fig. 4. Branch Metric and Path Metric Calculation for Viterbi Decoder

Fig. 2. Convolutional Encoder used for proposed work

Convolutional encoder can be applied to either continuous

stream of data or block of data. The message bits are shifted
into shift registers k bits at a time. Since K=3,
=3, there are two
shift registers and the encoder has 2K-1 = 4 states.
states The state
diagram for the convolutional encoder used in the proposed
propos
work is shown in Fig. 3. More details about convolutional
encoder can be had from [18].

Fig. 5. Trellis diagram for Viterbi Decoder

C.

Fig. 3. State diagram of Convolutional Encoder designed

Golay Encoder

Golay encoder is one among the most widely used block

code where a continuous stream of data is divided into block
blocks
of 12 bits and each block is processed
rocessed, one at a time. The two
closely related Golay codes are extended binary Golay code
and perfect binary Golay code. The extended binary Golay
code, represented as G24 encodes 12 bits of data in a 24
24-bit
word in such a way that any 3-bit
bit errors can be corrected or

any 7-bit errors can be detected, whereas the perfect binary

Golay code, represented as G23 has codewords of length 23 and
is obtained from the extended binary Golay code by deleting
one coordinate position. The standard code notation for G24 and
G23 have parameters [24,12,8] and [23,12,7] corresponding to
the length of the codewords, the dimension of the code, and the
minimum Hamming distance between two codewords
respectively. The extended binary Golay code G24 is used for
the proposed work, which has a generator matrix, G given as
G = [ P I]
(3)
where I is the 12x12 identity matrix and P is the Parity matrix.
The encoded output, V of Golay encoder is given as
V=U*G
(4)
where U is the 1x12 input block and the size of encoded output
is 1x24. More details about Golay Encoder can be had from
[18,19].

D.

Golay Decoder

Golay decoder is a decoding algorithm for Golay codes

which can detect upto 7 errors and correct upto 3 errors. Golay
decoder uses the same parity matrix as in Golay encoder to
obtain a parity check matrix, H given as
H =[ I P]
(5)
The decoding algorithm consists of determining the error
pattern u = v + w, where w denotes the vector received and v
is the nearest to w code vector. Let wt(x) denote the weight of
the vector x i.e., the number of ones in x, pi denote the i-th
row of the parity matrix P, ei denote the word of length 12 with
1 in the i-th position and 0 elsewhere. Once u is determined,
the corrected received vector will be v = u + w, and the last 12
elements of v will be the input block fed to Golay encoder. The
steps for Golay decoding algorithm [19] is given as a
pseudocode in Fig. 6. More details about the decoding
algorithm can be had from [18].

II is shown in Fig. 8 which is identical to Architecture I with

the only difference that this system can reconfigure itself to
function as either Golay encoder or Golay decoder. Fig. 9
shows Architecture III where the reconfigurable system is
capable of reconfiguring itself to perform as one among the
four schemes. Architecure IV shown in Fig. 10 is capable of
providing two functionalities at a time and can reconfigure
itself to select different combinations of encoder and decoder.
Architecture V shown in Fig. 11 is identical to Fig. 10 wherein
the encoder output is given to decoder input and at any instance
the system can reconfigure itself to function as an encoderdecoder pair.
It may be observed from Fig. 7 to Fig. 9 that, only one
reconfigurable block is selected for the system and hence only
one functionality can be achieved at any instance. This
approach reduces the hardware resources required which inturn
reduces the power consumption and is employed for
applications where only one scheme is required at any instance.
On the other hand, it may be observed from Fig. 10 and Fig. 11
that two reconfigurable blocks are employed which enables
two schemes to function simultaneously and thus the hardware
resources required and power consumption will be greater than
that required for system designed using single reconfigurable
block. The number of reconfigurable modules in each
reconfigurable block can be increased depending on the user
requirements.

Fig. 7. Architecture I of Proposed Reconfigurable Coder System

Fig. 6. Pseudocode for Golay Decoder

Step 1: Compute the syndrome s = wHT
Step 2: If wt(s) 3then u=[s, 000000000000].
Step 3: If wt(s+pi) 2 for some pi of P, then u = [s+ pi , ei].
Step 4: Compute the second syndrome sP.
Step 5: If wt(sP) 3then u=[000000000000, sP ].
Step 6: If wt(sP+pi) 2 for some pi of P, then u = [ei, sP+ pi ].
Step 7: If u is not yet determined then request retransmission.

III. RECONFIGURABLE ARCHITECTURES DESIGNED FOR

PROPOSED WORK

Fig. 8. Architecture II of Proposed Reconfigurable Coder System

In this section, five different architectures employed for

proposed reconfigurable coder systems are discussed.
Reconfigurable systems are defined as systems which are
capable of reconfiguring itself on-the-fly to perform different
functionalities. Reconfiguration trigger is defined as the signal
used to initiate reconfiguration of the system and the different
approaches for generating these reconfiguration triggers
include RS232 based reconfiguration, discrete input based
reconfiguration, event based reconfiguration, timer based auto
reconfiguration[17]. Fig. 7 shows Architecture I of
reconfigurable coder which can reconfigure itself to function as
either Convolutional encoder or Viterbi decoder. Architecture
Fig. 9. Architecture III of Proposed Reconfigurable Coder System

TABLE IV. HARDWARE RESOURCES SAVED ON USING ARCHITECTURE III

Resources

Non Reconfig. Arch

Arch III

% Saved

Slices
LUTs
Used LUT-FF pairs

325
732
291

145
439
127

55.38%
40.02%
56.36%

TABLE V. HARDWARE RESOURCES SAVED ON USING ARCHITECTURE IV & V

Non Reconfig.
Arch
Slices
325
LUTs
732
Used LUT-FF pairs
291
Resources

Fig. 10. Architecture IV of Proposed Reconfigurable Coder System

Fig. 11. Architecture V of Proposed Reconfigurable Coder System

IV. EXPERIMENTAL RESULTS

The proposed reconfigurable system is designed and
implemented using Xilinx make Virtex-5 XC5VFX70T [20]
FPGA based ML507 evaluation board [21]. The hardware
resources required for the implementation of four different
schemes mentioned in Section II are reported in Table I.
Details about the hardware resources saved on using
reconfigurable architecture over non reconfigurable
architecture for different types of architectures reported in
Section III are given in Table II to Table V. It is observed from
Table II, III and IV that as the number of reconfigurable
modules in a reconfigurable block increases, the amount of
hardware resources saved also increases. It is observed from
Table V that a maximum of 24.05% of hardware resources are
saved on using two reconfigurable blocks, which comes with a
benefit that the system can reconfigure itself to perform two
functionalities at any instance.
TABLE I. HARDWARE RESOURCES REQUIRED BY DIFFERENT SCHEMES
Resources
Conv Enc
Slices
36
LUTs
40
Used LUT-FF pairs
35

Viter Dec
35
42
35

Gol Enc
109
211
97

Gol Dec
145
439
124

TABLE II. HARDWARE RESOURCES SAVED ON USING ARCHITECTURE I

Resources

Non Reconfig. Arch

Arch I

% Saved

Slices
LUTs
Used LUT-FF pairs

71
82
70

36
42
35

49.30%
48.78%
50.00%

TABLE III. HARDWARE RESOURCES SAVED ON USING ARCHITECTURE II

Resources

Non Reconfig. Arch

Arch II

% Saved

Slices
LUTs
Used LUT-FF pairs

254
650
221

145
439
124

42.91%
32.46%
43.89%

Arch IV and Arch V

Block1 Block2 Total
109
145
254
211
439
650
97
124
221

%
Saved
21.85%
11.20%
24.05%

It should also be noted that the reconfigurable based design

comes at an expense of implementing soft-processor called
Microblaze onto FPGA which again consumes hardware
resources as given in Table VI. This becomes negligibly small
when the hardware resources required by the modules to be
reconfigured is large or when the number of modules to be
reconfigured increases. Details about the power consumption
for proposed system using different architectures is obtained
from XPower Analyzer and are reported in Table VII. It is
observed that on using reconfigurable architecture, a maximum
of 72.21% of power is saved.
TABLE VI. HARDWARE RESOURCES UTILIZED BY THE SOFT PROCESSOR
Resources
#Slice Registers
#Slice LUTs
#Block Memory
#DSP48Es
#Clock Manager
#Bonded IOBs
#BUFG/BUFGCTRLs

Available

MicroBlaze

44800
44800
148
128
18
640
32

2850
2690
17
3
0
0
2

TABLE VII. POWER ANALYSIS REPORT FOR PROPOSED WORK

Module/Architecture

Power

Power Saved

Convolutional Encoder
Viterbi Decoder
Golay Encoder
Golay Decoder
Architecture I
Architecture II
Architecture III
Architecture IV
Architecture V

1.423 W
1.423 W
1.423 W
1.423 W
1.607 W
1.591 W
1.603 W
1.597 W
1.582 W

----43.53%
44.10%
43.68%
71.94%
72.21%

Details about the size of bitstream file and reconfiguration

time for proposed work is reported in Table VIII. The
reconfiguration time is defined as the time taken by FPGA to
reconfigure and is given as [22]


 =  


(6)

where  denotes the size of bitstream or configuration file

for reconfiguration modules and  denotes the maximum
bandwidth of the configuration mode which is given as
3.2Gbps at 100MHZ clock rate for the ICAP configuration
mode, which is used in the proposed work.

TABLE VIII. DETAILS OF CONFIGURATION FILE FOR PROPOSED WORK

Module/Architecture

Size

Treconfig

Convolutional Encoder
Viterbi Decoder
Golay Encoder
Golay Decoder
Architecture I
Architecture II
Architecture III
Architecture IV

3300 kB
3300 kB
3300 kB
3300 kB
777kB
1046kB
1247kB
575kB
644kB
621kB
432kB

----242 s
326 s
389 s
179 s
201 s
194 s
135 s

Architecture V

The FPGA floorplan for the proposed reconfigurable

system using single reconfigurable block is shown in Fig. 15(a)
and using two reconfigurable blocks in Fig.15(b). The pink
rectangle in Fig. 12 denotes the reconfigurable p-block
allocated for reconfigurable modules as described in Section
III.
V.

CONCLUSION

In this paper, design and implementation of reconfigurable

coder system on a SRAM based Xilinx Virtex-5 FPGA is
proposed using Convolutional encoder, Viterbi decoder, Golay
encoder and Golay decoder schemes as reconfigurable
modules. Different architectures of implementing the
reconfigurable system is discussed and results are reported.
Performance of the system designed is compared with and
without reconfigurable architecture. The proposed system can
be easily adapted for various communication systems and has
facility to enhance the system by adding additional encoding
and decoding schemes as reconfigurable modules.
ACKNOWLEDGEMENT
This work is funded by the All India Council for Technical
Education (AICTE) under the Research Promotion Scheme
(RPS) vide project grant No. 20/AICTE/RIFD/RPS(POLICYIII)75/2012-13. The authors thank the technical team of
CoreEL Technologies, Bangalore for their support.

(a) Single P-Block

Fig. 12. FPGA Floorplan for the proposed reconfigurable system

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