1

Verilint Coding Rules

Introduction
This chapter provides detailed reference information for the Leda Verilint
policy, which is centered on the former Avant! Nova-Verilint tool. These rules
are for Verilog only.
Note that Avant! Corporation marketed Nova-Verilint before its acquisition by
Synopsys Inc. The Leda Verilint policy covers most of the synthesis and
simulation-related checks that were performed by Nova-Verilint. Leda
performs these checks during:
o Language syntactic and semantic analysis
o Specific post-analysis checking phase
In the Leda environment, rules checked during the post-analysis phase are
organized into policies and rulesets that you can activate and manage from
the command-line using the -p or -r options, or from the GUI using the Rule
Configuration Wizard. For more information on activating and configuring
rules to meet your own design team's needs, see the Leda User Guide. The
rules in the Verilint policy that are checked during the post-analysis phase
are organized into one ruleset named CHECKER_ERROR. The labels for these
rules are the same as the ones used in Nova-Verilint for similar checks. It is
the descriptions for these CHECKER_ERROR rules that make up the bulk of
this chapter.

CHECKER_ERROR Ruleset
The following rules are from the CHECKER_ERROR ruleset:

E25
Message: Bits are backwards
Descriptio
n

Leda fires for this rule when it detects that the high index of
the width range is in the RHS.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Error

Example
The following example of invalid Verilog code exhibits this problem:
//Example:a[1:2]
moduletop(a,b);
input[2:1]a;
output[2:1]b;
reg[2:1]b;
always@(a[1:2]ora[2])
if(a[2])
b<=1'b0;
elseif(b)
b<=1'b0;
else
b<=a;
endmodule

E54
Message: Instance name required for module

Descriptio
n

Leda fires for this rule when there is no instance name for a
module. To solve this problem, name the instance.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Error

Example
The following example of invalid Verilog code exhibits this problem:
//Example:test(clk,reset,d,q);
moduletop(clk,reset,d,q);
inputclk,reset,d;
outputq;
test(clk,reset,d,q);//E54, no instance name.
endmodule
moduletest(clk,reset,d,q);
inputclk,reset,d;
outputq;
regq;
always@(posedgeclkorposedgereset)
if(reset==1'b1)
q<=1'b0;
else
q<=d;
endmodule

E66
Message: Not a constant expression
Descriptio
n

Leda fires for this rule when it detects variables in parameter

or defparam definitions. To solve this problem, use a constant
expression.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Error

Example
The following example of invalid Verilog code exhibits this problem:
//Example:i
moduletest;
integeri;
parameterk=i;
endmodule

E267
Message: Range index out of bound
Description

None.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Error

Example
The following example of invalid Verilog code exhibits this problem:
//Example:input[2:1]a;
...
always@(posedgea[1:0])
...

moduletop(clk,reseta,resetb,a,b);
inputclk,reseta,resetb;
input[2:1]a;
output[2:1]b;
reg[2:1]b;
always@(posedgea[1:0])
if(reseta)
b<=1'b0;
elseif(resetb)
b<=1'b0;
else
b<=a;
endmodule

E268
Message: Index out of bound
Descriptio
n

Leda fires for this rule when it finds an index that is not in the
interval of the width range.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Error

Example
The following example of invalid Verilog code exhibits this problem:
//Example:index0
moduletop(a,b);
input[2:1]a;
output[2:1]b;
reg[2:1]b;
always@(a[1]ora[0])
b<=a;
endmodule

E304

Message: Drive strength cannot be given to a net

Description

None.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Error

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
wire(weak1,pull0)b=a;
modulewarn;
wirea;
wire(weak1,pull0)b=a;
endmodule

E368
Message: Variable previously declared as vector
Descriptio
n

This rule fires when Leda finds a variable previously declared

as a vector.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:

//Example:wirea;
moduletest(a,y);
input[7:0]a;
output[7:0]y;
wirea; //E368
wire[7:0]y;
assigny=~a;
endmodule

W19
Message: Truncation of error bits
Descriptio
n

Flags if size of literal is too small for value. For example:In

3'h10, hex 10 requires 8 bits, but bit size of literal is specified
to 3 bits.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

W20
Message: Assign statement may not be synthesizable

Descriptio
n

Leda fires for this rule when it finds a statement that may not
be synthesizable. This applies only to procedural continuous
assignment statements. Continuous assignments are
synthesizable.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example
moduleproc_conti_assignment(D,Clr,Clk,Q);
inputD,Clr,Clk;
outputQ;
regQ;
always
@(Clr)begin
if(Clr==0)
assignQ=0; //W20
else
deassignQ;//W21
end
always
@(negedgeClk)Q=D;
endmodule

W21
Message: Deassign statement may not be synthesizable
Descriptio
n

Leda fires for this rule when it finds a statement that may not
be synthesizable.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example

The following example of invalid Verilog code exhibits this problem:

//Example:
moduleproc_conti_assignment(D,Clr,Clk,Q);
inputD,Clr,Clk;
outputQ;
regQ;
always
@(Clr)begin
if(Clr==0)
assignQ=0;//W20
else
deassignQ;//W21
end
always
@(negedgeClk)Q=D;
endmodule

W43
Message: Wait statement may not be synthesizable
Description

None.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:wait(reset)
moduletest(clk,reset,q);
inputclk,reset;
outputq;
always@(clk)

wait(reset)//W43, wait is not synthesized

q<=1'b1;
endmodule

W67
Message: Not a constant expression

Descriptio
n

Leda fires for this rule when it finds a variable expression

where a constant expression is expected. A constant
expression is suspicious if it is used as the conditional
expression in a control statement. Similarly, a constant
expression is not expected in an event expression. Note that
constant expressions can be made of literals and/or
parameters. This rule is only checked in MinTypMax
expressions.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:nand#(i:5:7,5:6:7)(out,in1,in2);
moduletest(in1,in2,out);
inputin1,in2;
outputout;
integeri;
nand#(i:5:7,5:6:7)(out,in1,in2);//W67
endmodule

W69
Message: Case statement without default clause but all the
cases are covered

Descriptio
n

Leda fires for this rule when it finds a case statement that has
no default clause, but which appears to cover all cases. Even if
all cases that have 1's and 0's are covered, there may be
others that are not covered. A default clause can cover these
additional cases.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
regr;
...
case(r)
1'b0:...
1'b1:...
endcase
moduletest(clk,reset,gate,phase);
inputclk,reset;
input[1:0]gate;
output[3:0]phase;
wireclk,reset;
wire[1:0]gate;
reg[3:0]phase;
always@(posedgeclk)begin
if(reset)begin
phase<=4'b0000;
end
elsebegin
case(gate)
2'b00:phase<=4'b0001;
2'b10:phase<=4'b0100;
2'b01:phase<=4'b0010;
2'b11:phase<=4'b0001;
endcase
end
end

endmodule

W71
Message: Case statement without default clause and not all
cases are covered
Descriptio
n

Leda fires for this rule when it finds a case statement that does
not have a default clause, and not all cases are covered.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
reg[1:0]r;
...
case(r)
2'b00:...
2'b01:...
2'b10:...
//W71, 2'b11 is missing
endcase

W110
Message: Incompatible width
Descriptio
n

Leda fires for this rule when it finds an instance port

expression that has a different width than the module port.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:i1,o1
moduletop(i1,o1);
input[5:0]i1;
output[5:0]o1;
mmu1(i1,o1); //W110
endmodule
modulemm(i,o);
input[3:0]i;
output[3:0]o;
assigno=~i;
endmodule

W112
Message: Nested event control construct
Description

None.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:

//Example:@(posedgeclkorposedgereset)inalwaysblock
moduletest(clk,reset,gate,phase);
inputclk,reset;
input[1:0]gate;
output[3:0]phase;
wireclk,reset;
wire[1:0]gate;
reg[3:0]phase;
always@(posedgeclk)begin
if(reset)begin
phase<=4'b0000;
end
elsebegin:block1
@(posedgeclkorposedgereset); //W112
case(gate)
2'b00:phase<=4'b0001;
2'b10:phase<=4'b0100;
2'b01:phase<=4'b0010;
default:;
endcase
end
end
endmodule

W121
Message: Variable hides a variable in outer scope <%item>
Description

None.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of Verilog code exhibits this problem:
//VariableNGisinbothoutsideandinsideoffunction
moduleTEST(A,RST,ENV,B);

inputA,RST,ENV;
outputB;
regNG;

functionlatch;
inputA,RST,ENV;
regNG;
if(RST)begin
latch=1'b0;
end
elseif(ENV)begin
latch=A;
end
endfunction

assignB=latch(A,RST,ENV);

endmodule

W122
Message: Variable is not in the sensitivity list
Description

None.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

W126
Message: Non integer delay
Descriptio
n

Leda fires for this rule when it finds a delay that is not an
integer, but a real type.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of Verilog code exhibits this problem:
moduletest(in1,out1,out2);
inputin1;
outputout1,out2;
regout1,out2;
parameterTP1=0.5;
parameterTP2=5;
always@(posedgein1)
begin
out1<=#TP1in1;//Rule W126 fires
out2<=#TP2in1;
end
endmodule

W127
Message: Delay has X or Z
Descriptio
n

Leda fires for this rule when it finds a delay that is not a
positive integer, because it contains an X or Z.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:

//Example:#(1'bz)
`timescale1ns/100ps
moduletest(in1,in2,out1,out2,out3);
inputin1,in2;
outputout1,out2,out3;
integeri;
assign#(0.987)out1=in1&in2;
assign#(1'bz)out2=in1&in2;//W127, delay has x or z
assign#(i)out3=in1&in2;//W129,delayisnotaconstant
endmodule

W129
Message: Delay is not a constant
Description

None.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:#(i)
`timescale1ns/100ps
moduletest(in1,in2,out1,out2,out3);
inputin1,in2;
outputout1,out2,out3;
integeri;
assign#(0.987)out1=in1&in2;
assign#(1'bz)out2=in1&in2;//W127,delayhasxorz
assign#(i)out3=in1&in2;//W129, delay is not a constant
endmodule

W131

Message: Potential loss of precision in multiplication

Descriptio
n

Leda fires for this rule when there is a potential loss of

precision in multiplication. This can be caused by an incorrect
wire scale declaration.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:out=in1*in2;out,in1andin2areallonebit.
moduletest(in1,in2,out);
inputin1,in2;
outputout;
wirein1,in2;
wireout;
assignout=in1*in2;//W131
endmodule

W154
Message: Implicit wire declaration

Descriptio
n

Leda fires for this rule when it finds an implicitly declared wire
that is not declared explicitly, but appears in the argument list
of an instantiation. Leda flags such wires because undeclared
variables can be caused by typos. If your netlist is generated
automatically (for example, from a schematic), you can
suppress this warning.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
wirei,b,c;
and(j,b,c);//W154, should have been and (i, b, c);

W159
Message: Constant condition expression

Descriptio
n

Leda fires for this rule when it finds a constant expression used
as the conditional expression in a control statement. Similarly,
a constant expression is not expected in an event expression.
Note that constant expressions can be made of literals and/or
parameters.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
if(2>1)

W161

Message: Constant expression in conditional select

Descriptio
n

Leda fires for this rule if the condition in a conditional

expression is constant.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
a=(1'b0)?b:c;

W163
Message: Truncation of bits in constant. Most significant bits
are lost
Descriptio
n

Leda fires for this rule when it finds an integer converted to a

vector that is shorter than 32 bits, and some of the bits that
are discarded are non-zero.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:

//Example:
r[3:0]=16;

W175
Message: A parameter/generic has been defined but is not
used
Descriptio
n

Leda fires for this rule when it finds a parameter/generic has

been defined but not used in the file.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog/VHDL

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
moduletest(inputwirereset,clk,D,outputregQ);
ParameterP=5;//W175, parameter declared but not used
always@(posedgeclk)
begin
if(!reset)
Q<=1'b0;
else
Q<=D;
end
endmodule

W182
Message: Illegal statement for synthesis
Descriptio

Leda fires for this rule when it finds a statement that cannot be

synthesized. This rule applies to the following statements:

o repeat
o while -> (event triggering)
o fork

o force
o release

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
modulew182(go,clk,inp);
inputgo,clk;
input[9:0]inp;
reg[15:0]r1;
always@(posedgego)
r1<=repeat(2)@(posedgeclk)inp*2;//W182
endmodule

W187
Message: Default clause is not the last clause in case
statement
Description

None.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
case(...)
...
default:...
...
2'b0x:...
endcase

W188
Message: Destination variable is input

Descriptio
n

Leda fires for this rule when it finds a destination variable

declared as an input port. This rule is flagged only if the
destination variable is a vector or a part-select of a vector.
Leda does not flag this rule if the destination variable is a bitselect. You can use rule W397 to identify destination variable
that are bit-select.To solve this problem, declare the
destination variable as an inout or output.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:

//Example:inputx;assignx=.....;
modulew188(a,b,ps,bs,x);
inputa,b;
input[3:0]ps;
input[1:0]bs;
inputx;
assignps[1:0]=a&b;// Rule W188 is flagged here
assignbs[1]=a|b;//RuleW188doesnotflaghere
assignx=a&b;// Rule W188 is flagged here
endmodule

W192
Message: Empty block
Descriptio
n

Leda fires for this rule when it finds a "begin ..end" block
without any statements.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:begin...end
moduletest(enable);
inputenable;
always@(enable)begin //W192, empty block
end
endmodule

W215
Message: Bit select for integer or time variable

Descriptio
n

Bit-selects are taken from integer variables. Integers should

not be treated as vectors. If you want to take a bit-select or
part-select from a variable, declare the variable as a vector.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
integeri;
initiali[0]=1'b0; // W215
initiali[2:1]=2'b11;//W216

W216
Message: Range select for integer or time variable
Descriptio
n

Part-selects are taken from integer variables. Integers should

not be treated as vectors. If you want to take a bit-select or
part-select from a variable, declare the variable as a vector.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example

The following example of invalid Verilog code exhibits this problem:

//Example:
integeri;
initiali[0]=1'b0;//W215
initiali[2:1]=2'b11;// W216

W218
Message: Illegal event expression
Description Leda flags this rule when it finds an illegal event expression.
Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

W224
Message: Multi-bit expression when one bit expression is
expected
Descriptio
n

The condition expression in an if statement or in a conditional

expression is wider than 1 bit.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example

The following example of invalid Verilog code exhibits this problem:

//Example:
if(a[3:0])//W224, should be if (a[3:0]!=4'b0000)

W225
Message: Case item expression is not constant
Descriptio
n

Some of the case items have constant expressions and some

do not.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
case(a)
2'b01:b=a;
2'b10:b=a;
c+d:b=1;//W225, c+d is not constant
...
endcase

W226
Message: Case-select expression is constant.
Description

The case expression is constant.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
case(1)
2:...
...
endcase

W228
Message: While condition expression is constant

Descriptio
n

A variable expression was found where a constant expression

was expected. A constant expression is suspicious if it is used
as the conditional expression in a control statement. Similarly,
a constant expression is not expected in an event expression.
Note that constant expressions can be made of literals and/or
parameters.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example
while(1)//W228, always true--forever loop

W239
Message: Hierarchical references may not be synthesizable
Descriptio
n

Leda flags this rule if it finds hierarchical refernces as they are

not synthesizable.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
moduleTEST(inputin1);
endmodule
modulemW239(inputin1,outputout1);
TESTT1(in1);
assignout1=T1.in1;// Rule W239 fails here
endmodule

W244
Message: Shift by non-constant

Descriptio
n

Leda fires for this rule when it finds a shift expression that has
a non-constant shift operand. In synthesized code, this may be
translated into a selector; whereas, a shift by constant does
not generate any hardware, only wiring. Note that constant
expressions can be made of literals and/or parameters.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//wire[2:0]a;
wire[7:0]b;
...b<<a...

W250
Message: Disable statement is not synthesizable
Description

None.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
moduletest(in1,in2,out1);
input[7:0]in1,in2;
output[7:0]out1;
wire[7:0]in1,in2;
reg[7:0]out1;
always@(in1orin2)
begin:b1
integeri;
for(i=0;i<=10;i=i+1)

begin:b2
if(i>7)disableb2;
//W250, disable statement is not synthesizable
out1[i]=in1[i]^in2[i];
end
end
endmodule

W256
Message: A notifier must be a one-bit register
Description

A notifier must be a one-bit register.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//This test case has a notifier which is 2 bits wide.
modulemW256(inputclk,outputout2);
wire[1:0]notifier=2'b10;
always@(clk)
$setup(out2,clk,2,notifier);//FAIL: notifier is 2 bits wide
endmodule

W257
Message: Delays ignored by synthesis tools
Descriptio
n

Leda fires for this rule when it finds a statement that cannot be
synthesized.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:assign#3out1=in1^in2;
`timescale1ns/100ps
moduletest(in1,in2,out1,out2);
inputin1,in2;
outputout1,out2;
assign#3out1=in1^in2;//W257, delays ignored by synthesis tool
and#(2,3)AL(out2,in1,in2);//noW257.
endmodule

W263
Message: Case expression out of range
Descriptio
n

Leda fires for this rule when it finds an integer constant used
in a case item expression that is larger than the largest
representable case expression.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:

case(a[2:0])//numbersbetween0and7
1:...;//W263, number too small
9:...;//W263, number too big

W280
Message: Delay in non blocking assignment
Description

This test is done only in sequential always blocks.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
c<=#1d;//W280, could be a blocking assignment

W287
Message: Unconnected port
Descriptio
n

Leda fires for this rule when it finds a port that is not
connected in a module instantiation.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

W289
Message: Multiply connected port
Description

None.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
modulem(a,b);
inputa;
outputb;
assignb=~a;
endmodule
modulemm(x,y);
inputx;
outputy;
mu1(.a(x),.a(y));//W289, port a is connected twice
endmodule

W292
Message: Real operands in comparison
Description

Leda flags this rule when it finds real operand comparison.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

W294
Message: Unsynthesizable real variable
Descriptio
n

Leda fires for this rule when it finds a statement that cannot be
synthesized.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:K
moduletop(a,b);
input[2:1]a;
output[2:1]b;
wirec;
realK;//W294
assignb[2]=a[1];
endmodule

W299
Message: Blocking repeat assignment
Descriptio
n

Leda fires for this rule when it finds a repeat event control as
the intra-assignment delay of a blocking assignment. These
statements cannot be synthesized.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

W300
Message: Non-blocking repeat assignment
Descriptio
n

Leda fires for this rule when it finds a repeat event control as
the intra-assignment delay of a non-blocking assignment.
These statements cannot be synthesized.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:r1<=repeat(2)@(posedgeclk)inp*2;
modulewarn(go,clk,inp);
inputgo,clk;
input[9:0]inp;
reg[15:0]r1;
always@(posedgego)
r1<=repeat(2)@(posedgeclk)inp*2;
endmodule

W306
Message: Converting integer to real

Descriptio
n

Verilog allows type mixing in expressions. When

subexpressions of different types are used in an expression,
they may be converted to a common type. This conversion is
done automatically by the Verilog processor (that is,
simulator). Additionally, expressions are converted to different
types depending on the context in which they are used. For
example, if an expression is assigned to a variable, then the
expression is converted to the same type as the variable. Leda
detects such conversions and issues warnings.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:rl1=int1;
modulewarn;
integerint1;
realrl1;
initialbegin
rl1=int1;//W306
end
endmodule

W307
Message: Converting unsigned to real
Descriptio
n

Verilog allows type mixing in expressions. When

subexpressions of different types are used in an expression,
they may be converted to a common type. This conversion is
done automatically by the Verilog processor (that is,
simulator). Additionally, expressions are converted to a
different type depending on the context in which they are
used. For example, if an expression is assigned to a variable,

then the expression is converted to the same type as the

variable. Leda detects such conversions and issues warnings.
Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:f_time_xin=(f_time_sysc*1.5);
moduleec;
timef_time_xin,f_time_sysc;
initial
f_time_xin=(f_time_sysc*1.5);
endmodule

W308
Message: Converting real to integer

Descriptio
n

Verilog allows type mixing in expressions. When

subexpressions of different types are used in an expression,
they may be converted to a common type. This conversion is
done automatically by the Verilog processor (that is,
simulator). Additionally, expressions are converted to different
types depending on the context in which they are used. For
example, if an expression is assigned to a variable, then the
expression is converted to the same type as the variable. Leda
detects such conversions and issues warnings.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:int1=rl1;
modulewarn;
integerint1;
realrl1;
initialbegin
int1=rl1;//W308
end
endmodule

W311
Message: Converting real to unsigned

Descriptio
n

Verilog allows type mixing in expressions. When

subexpressions of different types are used in an expression,
they may be converted to a common type. This conversion is
done automatically by the Verilog processor (that is,
simulator). Additionally, expressions are converted to a
different type depending on the context in which they are
used. For example, if an expression is assigned to a variable,
then the expression is converted to the same type as the
variable. Leda detects such conversions and issues warnings.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:r1=rl1;

modulewarn;
reg[1:0]r1;
realrl1;
initialbegin
r1=rl1;//W311
end
endmodule

W312
Message: Converting real to single bit (logical)

Descriptio
n

Verilog allows type mixing in expressions. When

subexpressions of different types are used in an expression,
they may be converted to a common type. This conversion is
done automatically by the Verilog processor (that is,
simulator). Additionally, expressions are converted to different
types depending on the context in which they are used. For
example, if an expression is assigned to a variable, then the
expression is converted to the same type as the variable. Leda
detects such conversions and issues warnings.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:r1=rl1;
modulewarn;
regr1;
realrl1;
initialbegin
r1=rl1;//W312
end
endmodule

W313
Message: Converting integer to single bit (logical)
Descriptio
n

Leda fires for this rule when it finds an integer that is set to a
one-bit signal.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:6issettoonebitsignalx.
moduletop(clk,f);
inputclk;
outputf;
functiontop;
inputx;
top=x; //W313, x=6, and top is a bit wire.
endfunction
regf;
always@clk
f=top(6);
endmodule

W314
Message: Converting vector (unsigned) to single bit (logical)
Descriptio
n

Verilog allows type mixing in expressions. When

subexpressions of different types are used in an expression,
they may be converted to a common type. This conversion is
done automatically by the Verilog processor (that is,
simulator). Additionally, expressions are converted to different

types depending on the context in which they are used. For

example, if an expression is assigned to a variable, then the
expression is converted to the same type as the variable. Leda
detects such conversions and issues warnings.
Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:vector"in"issettoonebit"out".
moduletest(in,out);
input[1:0]in;
outputout;
wire[1:0]in;
assignout=~in; //W314
endmodule

W322
Message: Multiple event control statement
Descriptio
n

Leda fires for this rule when it detects multiple event control
statements in an always block.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
modulewarn;
wirea,b;
rego;
always#5begin
@(posedgea);
@(posedgeb);
o=a^b;
end
endmodule

W332
Message: Not all possible cases covered but default case
exists
Descriptio
n

You may want to use the default to catch Xs and Zs but not to
catch missing cases.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
case(a[1:0])
2'b00:...;
2'b01:...;
2'b10:...;
default:...;
endcase//W332, 2'b11 is not covered

W335
Message: Non blocking delay assignment in combinational
always block

Descriptio
n

Leda fires for this rule when it finds a non-blocking delay

assignment in a combinational always block. Synthesis tools
ignore delays, causing simulation mismatches between preand post-synthesis. Avoid using delays in non-blocking
assignments.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
moduletop(a,b);
inputa;
outputb;
regb;
always@(a)
b<=#1a;
endmodule

W336
Message: Blocking delay assignment. In sequential always
blocks consider using nonblocking assignment
Descriptio
n

Blocking assignment. In sequential always blocks, consider

using nonblocking assignment. This rule is flagged for
unintentional latches also.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code demonstrates the potential
race condition using a two-stage shift register.
//Example:
always@(posedgeclk)begin
c=b;
end
always@(posedgeclk)begin
b=a;
end

W337
Message: Real comparison in case item
Description

None.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:

case(a)
2.0:...;// Reals are typically not used in comparisons

W339
Message: Non synthesizable operator
Descriptio
n

Leda fires for this rule when it finds a statement that cannot be
synthesized. This applies to the === and !== operators.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:if(w1===w2)
modulewarn;
wire[3:0]w1,w2;
regresult;
initialbegin
if(w1===w2)//W339
result=1;
end
endmodule

W341
Message: Extension of zero bits in a constant
Description

None.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:assigna=4'b0;

moduletest(set,d,a,b,c);
inputset;
input[3:0]d;
output[3:0]a,b,c;
wireset;
wire[3:0]a,b,c,d;
assigna=4'b0;//W341
assignb=set?4'bx:d;//W342
assignc=set?4'bz:d;//W343
endmodule

W342
Message: Extension of X bits in a constant
Description

None.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:assignb=set?4'bx:d;
moduletest(set,d,a,b,c);
inputset;
input[3:0]d;

output[3:0]a,b,c;
wireset;
wire[3:0]a,b,c,d;
assigna=4'b0;//W341
assignb=set?4'bx:d;//W342
assignc=set?4'bz:d;//W343
endmodule

W343
Message: Extension of Z bits in a constant
Description

None.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:assignc=set?4'bz:d;
moduletest(set,d,a,b,c);
inputset;
input[3:0]d;
output[3:0]a,b,c;
wireset;
wire[3:0]a,b,c,d;
assigna=4'b0;//W341
assignb=set?4'bx:d;//W342
assignc=set?4'bz:d;//W343
endmodule

W359
Message: For-condition expression is constant

Descriptio
n

A constant expression was found where a variable expression

was expected. A constant expression is suspicious if it is used
as the conditional expression in a control statement. Similarly,
a constant expression is not expected in an event expression.
Note that constant expressions can be made of literals and/or
parameters.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
for(i=1;3;i=i+1)

W372
Message: Undefined PLI task
Description

None.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:$pli(1);

moduletest;
regr1;
initial
$pli(1); //W372, $pli is an undefined PLI task
endmodule

W373
Message: Undefined PLI function
Description

None.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:r1=$pli(1);
regr1;
initial
r1 = $pli(1); //W373, $pli is an undefined PLI function module test
endmodule

W389
Message: Multiple clocks in the module

Descriptio
n

Leda infers clock and reset signals in a way that is similar to

synthesis. This may not apply to all design methodologies.For
a description of Leda 's interpretation of Verilog hardware
semantics, see the sections on "About Hardware-Based Rules"
and "Verilog Hardware Semantics" in the Leda User Guide.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
moduletop(clk1,clk2,reset,a,b);
inputclk1,clk2,reset,a;
outputb;
regb;
always@(posedgeclk2)
b=a;
always@(posedgeclk1)
if(reset)
b<=1'b00;
else
b<=a;
endmodule

W390
Message: Multiple resets in the module

Descriptio
n

Leda infers clock and reset signals in a way that is similar to

synthesis. This may not apply to all design methodologies.
Verilint only checks asynchronous resets.For a description of
Leda 's interpretation of Verilog hardware semantics, see the
sections on "About Hardware-Based Rules" and "Verilog
Hardware Semantics" in the Leda User Guide.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
moduletop(clk,reset1,reset2,a,b,c);
inputclk,reset1,reset2,a;
outputb,c;
regb,c;
always@(posedgeclkorposedgereset1)
if(reset1)
b<=1'b0;
else
b<=a;
always@(posedgeclkorposedgereset2)
if(reset2)
c<=1'b0;
else
c<=~a;
endmodule

W392
Message: Wrong reset polarity

Descriptio
n

The same reset is used both as a positive edge and a negative

edge. Some methodologies require that all reset and clock
lines be primary inputs to the module. If they are generated
internally to the module, Leda issues this message.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:posedgereset
moduletest(clk,reset,q);
inputclk,reset;
outputq;
wireclk,reset;
regq;
always@(posedgeclkorposedgereset)//W392, wrong reset polarity
if(reset==1'b0)
q<=1'b0;
endmodule

W394
Message: Multiple clocks in the always block
Descriptio
n

Leda issues this message when it detects more than one signal
used as a clock in an always block.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
moduletop(clk1,clk2,a,b);
inputclk1,clk2,a;
outputb;
regb;
always@(posedgeclk1orposedgeclk2)

b<=a;
endmodule

W396
Message: A flipflop without reset

Descriptio
n

Leda infers clock and reset signals in a way that is similar to

synthesis. This may not apply to all design methodologies.For
a description of Leda 's interpretation of Verilog hardware
semantics, see the sections on "About Hardware-Based Rules"
and "Verilog Hardware Semantics" in the Leda User Guide.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
moduletest(clk,reset,d,q);
inputclk,reset,d;
outputq;
regq;
always@(posedgeclk)
begin:block
if(reset==0)
//q=0;
//else
q=d;
end
endmodule

W397
Message: Destination bit is input

Descriptio
n

Leda fires for this rule when it finds a destination bit variable is
used as an input port. This rule is flagged does not flag for if
the destination variable is a vector or a part-select of a vector.
Leda flags this rule only if the destination variable is a bitselect. You can use rule W188 to identify destination variable
that are part-select or vectors.To solve this problem, declare
the destination variable as an inout or output.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
modulew188(a,b,ps,bs,x);
inputa,b;
input[3:0]ps;
input[1:0]bs;
inputx;
assignps[1:0]=a&b;//RuleW397doesnotflaghere
assignbs[1]=a|b;// Rule W397 is flagged here
assignx=a&b;/RuleW397doesnotflaghere
endmodule

W401
Message: Clock is not an input to the module

Descriptio
n

Leda fires for this rule when it finds a clock that is not an input
to the module, but an internal signal. For a description of Leda
's interpretation of Verilog hardware semantics, see the
sections on "About Hardware-Based Rules" and "Verilog
Hardware Semantics" in the Leda User Guide.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
clkInt
modulew401(clkExt1,clkExt2,dataIN,dataOUT,testMode);
inputclkExt1,clkExt2,dataIN,testMode;
outputdataOUT;
reg dataOUT;

wireclkInt;

assignclkInt=testMode?clkExt2:clkExt1;
always@(posedgeclkInt)
begin
dataOUT<=dataIN;
end
endmodule

W402
Message: Reset is not an input to the module

Descriptio
n

Leda fires for this rule when it finds a reset that is not an input
to the module, but an internal signal. For a description of Leda
's interpretation of Verilog hardware semantics, see the
sections on "About Hardware-Based Rules" and "Verilog
Hardware Semantics" in the Leda User Guide.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
resetInt
modulew402(clk,dataIN,dataOUT,testMode);
inputclk,dataIN,testMode;
outputdataOUT;
reg dataOUT;

wireresetInt;

assignresetInt=testMode?1'b1:1'b0;
always@(posedgeclkorposedgeresetInt)
begin
if(resetInt)
dataOUT<=0;
else
dataOUT<=dataIN;
end

endmodule

W403
Message: Clock is used as data

Descriptio
n

Leda fires for this rule when it finds a clock used as data. A
signal used as a clock is also providing data to a register input,
either directly or through combinational logic. This can cause
timing violations and race conditions. To solve this problem,
check for clocks that are not in the sensitivity list of an always
block. To check this rule on the entire design, you must specify
a top design unit using the -top option.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Chip-level

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:b=clk;
moduletop(clk,reset,a,b);
inputclk,reset,a;
outputb;
regb;
always@(posedgeclk)
b=clk;
always@(posedgeclk)
if(reset)
b<=1'b00;
else
b<=a;
endmodule

W410
Message: A latch is inferred

Descriptio
n

Leda fires for this rule if it finds a latch in the design. A latch is
inferred if, within a combinational always block, there is a
variable assigned in some, but not all threads of the block. The
algorithm is similar to the algorithm used in synthesis.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example

The following example of invalid Verilog code exhibits this problem:

//Example:
always@(dorg)
if(g)q=d;//W410, if g is 0, then q is not assigned
always@(a)
case2'b00:c=2'b11;
case2'b01:c=~a;
case2'b10:c=a;
//Thecasea=2'b11ismissing
endcase

W414
Message: Non blocking assignment in combinational block

Descriptio
n

Leda infers always blocks as either combinational or

sequential. For sequential always blocks, Leda issues a warning
if there is blocking assignment. For combinational blocks, Leda
issues a warning if there is a non-blocking assignment. Using
non-blocking assignments in sequential blocks removes the
risk of a race condition in the simulation.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
always@(aorb)begin
c=a+b;
d<=ab;//W414
end
always@(posedgeclk)begin
c=a+b;//W336

d<=ab;
end

W415
Message: Multiple drivers to a net

Descriptio
n

Leda fires for this rule when it finds a net that has more than
one driver. The driver can be an output from a gate, an output
from a module instance, a left-hand side of a continuous
assignment, or a left-hand side of an assignment in a
combinational always block.Leda checks the compatibility
between the declaration of a port and the declaration of the
net or reg to which the port is connected.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Chip-level

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
assignw=a;
and(w,b,c);

W416
Message: Instance connections not by name

Descriptio
n

Leda fires for this rule when it finds a module instantiation that
is connected by position rather than by name. Some
companies require that all instances be connected by name to
reduce the probability of switching connections.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
mmu1(a,b);//W416
mmu2(.port2(b),.port1(a));//noW416

W421
Message: Non event-control statement (@) in always block
Descriptio
n

The first statement in an always block is not an event-control

statement (that is, not an @).

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
alwaysbegin
a=b; //W421, <-- The first statement is an assignment.
@(cord) //Only the second statement is an event-control.
...

end

W424
Message: Function sets a global variable
Descriptio
n

Leda fires for this rule when it detects a function that sets a
variable outside of the function.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:out
modulew424(in,out);
inputin;
outputout;

reg out;

functionval;
inputin;
out=in;

endfunction//val

endmodule

W425
Message: Function uses a global variable
Descriptio
n

Leda fires for this rule when it finds a function which uses a
variable that does not come from the input of the function.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:in
modulew425(in,out);
inputin;
outputout;

reg out;

functionval;
inputfunc_in;
val=in;

endfunction//val

initial
out=val(in);

endmodule

W426
Message: Task sets a global variable

Descriptio
n

Leda fires for this rule when it finds a variable set outside of
the task. This breaks the task. To solve this problem, use a
function to replace the task, and make the global variable a
value of the function.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:out

modulew426(reset,out);
inputreset;
outputout;

regout;

tasktest;
inputreset;

begin
if(reset)
out=1'b0;
end
endtask//test

initial
test(reset);

endmodule

W427
Message: Task uses a global variable
Descriptio
n

Leda fires for this rule when it finds a variable used outside of
the task. This breaks the task. To solve this problem, make the
global variable an input to the task.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:reset

modulew427;
wirereset;

tasktest;
rega;

begin
if(reset)
a=1'b0;
end
endtask//test

initial
test;

endmodule

W430
Message: Initial statement is not synthesizable
Descriptio
n

Leda fires for this rule when it finds an initial statement that
cannot be synthesized.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:

moduleTop(clock);
outputclock;
initial
clock=1'b0;
always
#5clock=~clock;
endmodule

W434
Message: Top level module is a primitive
Descriptio
n

Leda fires for this rule when there is only a primitive in the
design or the top-level module of the design is a primitive.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:primitiveMUX2x1
primitiveMUX2x1(Z,Hab,Bay,Sel);
outputZ;
inputHab,Bay,Sel;
table
endtable
endprimitive

W438
Message: Tristate is not in a top level module
Descriptio

You must specify the top-level module name using the -top

option of the Leda Checker, or its name must begin with "TOP".

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
moduletop(clock,a,b);
inputclock,a;
outputb;
regb;
subtest(clock,a,b);
endmodule
modulesub(clk,c,d);
inputclk,c;
outputd;
always@(posedgeclk)begin
if(clk)
d=c;
else
d=1'bZ;
end
endmodule

W443
Message: X in based number constant
Descriptio
n

Leda fires for this rule if it finds a constant with a value

including an X (even if the constant is used in a case item of a
casex/casez statement).

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
modulew443();
wired;
assignd=1'bX;
endmodule

W444
Message: High Z in based number constant
Descriptio
n

Leda fires for this rule if it finds a constant with a value

including a Z.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
moduletop(clock,a,b);
inputclock,a;
outputb;
regb;
subtest(clock,a,b);

endmodule
modulesub(clk,c,d);
inputclk,c;
outputd;
always@(posedgeclk)begin
if(clk)
d=c;
else
d=1'bZ;//W444, High Z
end
endmodule

W445
Message: Output or inout tied to supply
Descriptio
n

Leda fires for this rule when it finds an output or inout port
declared as supply0 or supply1 net.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
modulew445(OUT,INO);
outputOUT;
inoutINO;
supply0OUT;
supply1INO;
endmodule

W446
Message: Reading from an output port

Descriptio
n

Leda fires for this rule when it finds an output signal used as
an input signal.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
moduletop(clk,reset,a,b);
inputclk,reset,a;
outputb;
regb;
always@(posedgeclk)
if(reset)
b<=1'b00;
else
b<=a&b;
endmodule

W450
Message: Multi-bit expression (e.g., a[2:0]) used as clock
Descriptio
n

Leda fires for this rule when it finds more than one bit used as
a clock.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
modulew450(q,d,clock);
outputq;
inputd;
input[2:0]clock;
reg q;
always@(posedgeclock)
q<=d;
endmodule

W455
Message: Not all cases are covered in full case
Descriptio
n

Leda fires for this rule when it finds a full case (that is, one
that has the comment //synopsys full_case) which has some
cases that are not covered.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
modulem(in,out);
inputin;
outputout;regout;
always@in
case(in)//Synopsysfull_case
1'b0:out=1'b1;
endcase
endmodule

W456
Message: Variable in the sensitivity list but not used in the
block
Description

None.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
moduleww(clk,a,b);
inputclk;
input[2:0]a;
output[2:0]b;
reg[2:0]b;
always@(clkora[0])
b<=a;
endmodule

W459
Message: Constant is extended to the implied width of 32
bits
Descriptio
n

Leda fires for this rule when it detects that the size of the basic
constant is not defined. To solve this problem, set the size of
the constant

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
modulew459;
integeri;

initial
i='b0;
endmodule

W464
Message: Unrecognized synthesis directive
Descriptio
n

Leda flags this rule if it any unrecognized synthesis directive

used in the design. This rule is flagged for all synthesis
directives that DC does not supports.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
moduletest(inputwirereset,clk,D,outputregQ);
always@(posedgeclkorreset)
//synopsysrule_testing//unsupported synthesis directive by DC

begin
if(!reset)
Q<=1'b0;
else
Q<=D;
end
endmodule

W467
Message: '?' in based number constant
Descriptio
n

Leda fires for this rule if it finds a constant with a value

including a ?, (even if the constant is used in a case item of a
casex/casez statement).

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
modulew467(i);
outputi;

assigni=1'b?;
endmodule

W468
Message: Index variable is too short
Descriptio
n

Leda fires for this rule if it detects that some bits of the bus
cannot be reached because the index variable is too small. To

solve this problem, make the index variable bigger.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
modulew468(clock,enable,i,DI,memory);
inputclock,enable;
input[0:2]i;//W468, index variable i is too short
inputDI;
output[0:8]memory;
reg[0:8] memory;//memorycells
always@(posedgeclock)
begin
if(~enable)
memory[i]<=DI;
end
endmodule

W473
Message: A port without range is re-declared with a range
Description

None.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example

The following example of invalid Verilog code exhibits this problem:

//Example:
inputi;
wire[3:0]i;//W473, i was declared as input without a range

W478
Message: Bad loop initialization statement
Descriptio
n

Leda fires for this rule when it finds an incorrect initial

assignment in a for statement.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
modulew478(clk);
inputclk;
reg[7:0]r1;
always@clk
begin
for({r1[0],r1[2:1]}=0;r1<10;r1=r1+1)beginend
for(r1[2:1]=0;r1<10;r1=r1+1)beginend
for(r1[1]=0;r1<10;r1=r1+1)beginend
end
endmodule

W479
Message: Bad loop step statement
Descriptio

Leda fires for this rule when it finds an incorrect step

assignment in a for statement.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
modulew479(CLK);
inputCLK;
reg[7:0]r1;
always@(CLK)begin
for(r1=0;r1<10;{r1[0],r1[2:1]}=r1+1)beginend
for(r1=0;r1<10;r1[2:1]=r1+1)beginend
for(r1=0;r1<10;r1[1]=r1+1)beginend
end
endmodule

W483
Message: Assigning to self. This could imply a latch in
synthesis
Description

None.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:

//Example:
modulew483(in,sel,out);
inputin,sel;
outputout;
wirein,sel;
reg tmp;
assignout=tmp;

always@(selorin)
case(sel)
1'b0:tmp=in;
1'b1:tmp=tmp;//W483
endcase
endmodule

W484
Message: Possible loss of carry/borrow in
addition/subtraction

Descriptio
n

This rule fires when Leda detects an operand whose left-hand

side is smaller than right-hand side. It flag a warning for
conditional expressions in declarations except those whose
condition is a unary operations | or &. For example wire A =
(&B)?C:D;

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
moduletest(in1,in2,out);
inputin1,in2;
outputout;
wirein1,in2;

wireout;
assignout=in1+in2; //W484, one-bit signals
endmodule

W485
Message: Non-negative (reg) is compared to 0
Descriptio
n

Because the reg is non-negative, there is no need to compare

it to 0.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
modulew485(out);
outputout;
reg out;
reg r1;
always
begin
if(r1<=0)//W485
out=1;
end
endmodule

W488
Message: Bus variable in the sensitivity list but not all its bits
are used in the block
Descriptio
n

Leda fires for this rule when it finds a bus variable in the
sensitivity list, but not all its bits are used in the block. To

solve this problem, put only the used bits in the sensitivity list.
Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
modulew488(portr,out);
input[11:0]portr;
output
out;
wire[11:0] portr;
reg
out;

always@(portr)
begin
if(portr[1]==1'b0)//W488
out=1'b1;
end
endmodule

W489
Message: Last function statement does not assign to the
function
Descriptio
n

Leda fires for this rule when it detects that the value of a
function is not assigned in some condition.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
modulew489();
functionval;
inputsel;
inputin;

regel;

if(sel==1'b1)
val=in;
else
el = 1'b0; //W489, el = 1'b0 not assigned to val
endfunction
endmodule

W490
Message: Tristate control expression is not a variable name
Description

None.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
modulew490(bus,ctl,inbus);
output[7:0]bus;
input[1:0] ctl;

input[7:0] inbus;

assignbus=(ctl[1]&ctl[0])?inbus:8'hzz;
endmodule

W491
Message: Extension of ? bits in a constant
Descriptio
n

Leda fires for this rule when it finds that the most significant
bit is ?. The most significant bit is extended up to the size of
the expression.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:8'b?
modulew491(a,ctrl,y);
input[7:0]a;
inputctrl;
output[7:0]y;
assigny=ctrl?a:8'b?;

endmodule

W496
Message: Comparison to three state are treated as false

Descriptio
n

For the logical equality and logical inequality operators (==

and !=), if, due to unknown or high-impedance bits in the
operands, the relation is ambiguous, the result is a one-bit
unknown value (X).

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:1'bx
modulew496(in);
input
in;

always@(in)
begin
if(in==1'bx)begin
end
end
endmodule

W499
Message: Last function statement does not assign to all the
bits of the function
Descriptio
n

Leda fires for this rule when it finds that not all the bits of a
function are assigned.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example

The following example of invalid Verilog code exhibits this problem:

//Example:function[15:0]f1
f1[7:0]=inp;
modulew499;
function[15:0]f1;
input[7:0]inp;
begin
f1[7:0]=inp;
end
endfunction
endmodule

W502
Message: A variable in the sensitivity list is modified inside
the block
Descriptio
n

Leda fires for this rule when it finds a variable in the sensitivity
list that is modified inside the block.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
moduleDspIP(gate);
outputgate;
reggate;
always@(gate)
gate=1'b1;//W502, gate is modified
endmodule

W503

Message: An event variable is never triggered

Descriptio
n

Leda flags this rule if it finds an event variable declared but

never triggered. Event variables that are never triggered are
redundant.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Thistestcasehasaneventtempwhichisnottriggeredanywhere.
moduleW503(inputin1,outputout1);
eventtemp;//FAIL
always@(temp)
out1=in1;
endmodule

W504
Message: Integer is used in port expression
Description

None.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
modulem;
integeri;
mmu1(i);//W504
endmodule
moduletop(clk,reset,q);
inputclk,reset;
outputq;
integerd;
testt1(clk,reset,d,q);
endmodule
moduletest(clk,reset,d,q);
inputclk,reset,d;
outputq;
regq;
always@(posedgeclkorposedgereset)
if(reset==1'b1)
q<=1'b0;
else
q<=d;
endmodule

W505
Message: Mixed assignment styles (delay and nonblocking)

Descriptio
n

It is good coding style to use either non-blocking or delay

assignments in sequential blocks, but not both. If Leda finds a
mixture of these types of assignments in the same always
block, it issues this message.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
always@(posedgeclk)begin
a=#1b;
c<=d;
end

W505_a
Message: Value assigned inconsistently - may not be
synthesizable
Description

None.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Thisexamplehasasignalassignedwithbothblockingandnon
blockingassignmentsinsamealwaysblock.
modulemW_505(inputin1,in2,in3,outputout1);
regtemp;
always@(in1orin2|in3)
if(in2)

temp=in1;
else

temp<=in2;
endmodule
//Thisexamplehasasignalassignedwithbothblockingandnon
blockingassignmentsindifferentalwaysblock.

modulemW_505_1(inputin1,in2,in3,outputout1);
regtemp;
always@(in1)

temp=in1;
always@(in2)

temp<=in2;
endmodule

W507
Message: Too many strengths for a pullup/pulldown gate
(only one is needed)
Description

None.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

W509
Message: Defparam may not be synthesizable
Descriptio
n

Leda fires for this rule when it finds a statement that cannot be
synthesized.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:

//Example:
moduletop;
defparamk=1; //W509
endmodule

W521
Message: Not all the bits of the variable are in the sensitivity
list
Descriptio
n

Some of the bits of a vector that are used in a combinational

always block are not present in the sensitivity list.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

W526
Message: Nested ifs. Consider using case or casex statement
instead
Descriptio
n

It is good coding practice to use a case statement instead of a

sequence of nested if statements.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example

The following example of invalid Verilog code exhibits this problem:

//Example:
if(a)
if(b)
$display(aandb);
else
$display(aand~b);
else
if(b)
$display(~aandb);
else
$display(~aand~b);
// This can be rewritten as:
case({a,b})
2'b11:$display(aandb);
2'b10:$display(aand~b);
2'b01:$display(~aandb);
2'b00:$display(~aand~b);
endcase

W527
Message: 'if' without an 'else' when one may be expected
(dangling 'else' for a nested 'if'). Make sure the nesting is
correct

Descriptio
n

A dangling else in the code occurs when an else is missing

inside a nested if-else statement. A dangling else can be
misinterpreted, as the following example shows. To solve this
problem, make sure the nesting is correct.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:

//Example:if:(if(...)...else...)
moduletest(clk,a,b);
inputclk,a,b;
always@(posedgeclk)
if(a)
if(b)
$display("aandb");
else//W527, indentation is wrong. This else belongs to the second if.
$display("Nota");
endmodule

W529
Message: `ifdef may not be supported by some synthesis
tools
Descriptio
n

Leda fires for this rule when it finds a statement that cannot be
synthesized.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:`ifdefword
`ifdefword//W529, ifdef cannot be synthesized
`else
`defineword7
`endif
moduletest;
endmodule

W531
Message: Truncating leading zeros (or x's or z's)

Descriptio
n

Leading zeros are truncated in a constant. For example, the

construct 3'h0 causes this warning. This is a relatively benign
situation; the more serious ones like 3'hf or 3'h00 generate
different messages.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:assigna=6'h11;
moduletest(a,b);
output[5:0]a,b;
wire[5:0]a,b;
assigna=6'h11;//W531
assignb=6'hff;//noW531
//Truncationofextrabits:6'hffW19
endmodule

W541
Message: Tristate is inferred
Descriptio
n

Leda fires for this rule when it finds a variable assigned to a

conditional expression in which one of the branches is Z, as
shown in the example below.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
assigna=ctl?b:8'hzz;

W547
Message: Redundant case expression
Description

None.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
case(a)
2'b01,2'b01://Harmless,possiblyanoversight
...
moduletest(gate,q);
inputgate;
outputq;
regq;
always@gatebegin
case(gate)
1'b1,
1'b1:q=1'b1;//W547, redundant case expression
default:q=1'b0;
endcase
end

always@gatebegin
case(gate)
1'b1:q=1'b1;
1'b0:q=1'b1;//no W547
default:q=1'b0;
endcase
end

W548
Message: Synchronous flipflop is inferred
Descriptio
n

Leda fires for this rule when it finds a flip-flop that has a
synchronous reset.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
moduletest(clk,reset,d,q);
inputclk,reset,d;
outputq;
wireclk,reset,d;
regq;
always@(posedgeclk)//W548, synchronous flip-flop is inferred
if(reset==1'b0)
q<=1'b0;
else
q<=d;
endmodule

W549
Message: Asynchronous flipflop is inferred

Descriptio
n

Leda fires for this rule when it finds a flip-flop that has an
asynchronous reset.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
always@(posedgeclkorposedgerst)
if(rst)
q<=1'b0;
else
q<=d;

W550
Message: Mux is inferred
Description

None.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:case(gate)...endcase

moduletest(gate,q);
inputgate;
outputq;
wiregate;
regq;
always@(gate)begin
case(gate)
1'b0:
q=1'b0;
1'b1:
q=1'b1;
endcase//W550, mux is inferred: case (gate) ... endcase
end
endmodule

W551
Message: full_case has a default clause

Descriptio
n

A Synopsys full_case directive implies that only the cases that

are specified can occur. Therefore, a default clause is
redundant and can cause a discrepancy between simulation
and synthesis.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
case(a[1:0])//synopsysfull_case
2'b00:...;
2'b01:...;
2'b10:...;
default:...;//W551
endcase

W554
Message: Unconventional assigning to a function. Consider
using regular assignment statement ('=')
Description

None.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
moduletop(clk,f);
inputclk;
outputf;
functiontop;
inputx;
if(!x)
assigntop=1'b1; //W554, assign should not be used in function
else
deassigntop; //W555,deassignshouldnotbeusedinfunction
endfunction
regf;
always@clk
f=top(1'b1);
endmodule

W555
Message: Unconventional deassigning to a function

Description

None.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
functionf;
inputi;
begin
assignf=i;//W554
deassignf;//W555
end
endfunction

W556
Message: Complex condition expression. Could be as a result
of wrong interpretation of operator precedence

Descriptio
n

Leda fires for this rule if the expression for a condition is too
complicated. Sometimes a complex expression results from a
misinterpretation of the operator precedence. A complex
expression is any expression that contains an arithmetic
operator, shift operator.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
abc=a+c?d:e;//W556
//Theintentionwas:abc=a+(c?d:e);
//Buttheresultis:abc=(a+c)?d:e;

W557
Message: Illegal use of range for scalar parameter

Descriptio
n

Bit-selects or part-selects are taken from integer parameters.

Such parameters should not be treated as vectors. To take a
bit-select or part-select from a parameter, declare the
parameter as a vector.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
parameterp=12'hf23;
//parameter[11:0]p=12'hf23;//Thiseliminatesthewarning
initial$display(p[2:1]);//W557
initial$display(p[0]);//W558

W558

Message: Illegal use of bit select for scalar parameter

Descriptio
n

Bit-selects or part-selects are taken from integer parameters.

Such parameters should not be treated as vectors. To take a
bit-select or part-select from a parameter, declare the
parameter as a vector.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
parameterp=12'hf23;
//parameter[11:0]p=12'hf23; //Thiseliminatesthewarning
initial$display(p[2:1]);//W557
initial$display(p[0]); //W558

W561
Message: Based number with 0 width is extended to the
implied width of 32 bits
Descriptio
n

Leda fires for this rule when it finds a based number with 0
width extended to the implied width of 32 bits.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
regr;
initial
if(a==0'bz)// W561

W562
Message: Variable is assigned in both blocking and
nonblocking assignments
Descriptio
n

Leda fires for this rule when it finds a variable assigned in both
blocking and non-blocking assignments. Statements like this
cannot be synthesized.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
always@(posedgeclkorposedgerst)
if(rst)
q=1'b0;//blockingassignment
else
q<=d;//nonblockingassignment

W563

Message: Reduction of a single bit expression is redundant

Description

None.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
regr;
...
a=|r; //W563. this is equivalent to a = r;

W565
Message: Inferred a shift register
Description

None.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:

always@(posedgeclk)
s=s<<1;

W570
Message: Inferred a counter
Description

None.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
always@(posedgeclk)
s=s+1;

W575
Message: Logical NOT_OP operating on a vector
Description

None.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:

//Example:
reg[3:0]r;
regs;
...
s=!r;//W575, should use s = (r!=4'b0000);

W576
Message: Multibit operand in a logical expression
Description

None.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
reg[3:0]r,s;
regt;
t=r&&s;//W576, should be t=(r!=4'b0000)&&(s!=4'b0000);

W592
Message: Constant (parameter or specparam) is used in
event control expression
Descriptio
n

Leda fires for this rule when it finds a constant (parameter or

specparam) used in an event control expression. To solve this
problem, remove the redundant statement.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
parameterp=1;
always@p//W592, p is constant
...

W594
Message: Not all cases are covered in full case, but default
case exists
Description

None.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
case(exp)//Synopsysfull_case
case1:...
case2:...
...
default:
endcase

W599
Message: This construct is not supported by Synopsys
Description

None.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

W601
Message: The loop index is being modified

Descriptio
n

Leda fires for this rule when it finds a loop index variable being
modified. A loop index is typically not supposed to be modified
inside the loop. In fact, some languages do not allow this. Leda
checks to make sure the loop index is not modified, except in
the loop increment statement.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:
for(i=0;i<8;i=i+1)begin
i=i+2;
end

W631
Message: Assigning to self. This is harmless but can reduce
simulation speed
Description

None.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

W639
Message: For synthesis, operands of a division or modulo
operation need to be constants
Descriptio
n

Leda fires for this rule when it finds a statement that cannot be
synthesized.

Policy

VERILINT

Ruleset

CHECKER_ERROR

Language

Verilog

Type

Block-level

Severity

Warning

Example
The following example of invalid Verilog code exhibits this problem:
//Example:if(a%2==1)
moduletest(clk,a,b);
inputclk,a;
outputb;
regb;

always@(posedgeclk)
if(a%2==1) //W639, detect variable
b<=1'b0;
endmodule

Example
The following example of invalid Verilog code exhibits this problem:
//Example:always@(posedgeclk&a[1:0])
modulew17(clk,a,b);
inputclk;
input[2:0]a;
output[2:0]b;
reg[2:0]b;
always@(posedgeclk&a[1:0])
b<=a;
endmodule