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Exam2 (Example With Solutions)

The exam will cover material from lectures 12 and 14-26. It will contain 15 problems: 10 multiple choice and 5 written questions. Sample exam questions are provided covering topics like truth tables, number conversions, circuit analysis, VHDL code, and digital logic design problems.

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radhakodirekka8732
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© © All Rights Reserved
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298 views

Exam2 (Example With Solutions)

The exam will cover material from lectures 12 and 14-26. It will contain 15 problems: 10 multiple choice and 5 written questions. Sample exam questions are provided covering topics like truth tables, number conversions, circuit analysis, VHDL code, and digital logic design problems.

Uploaded by

radhakodirekka8732
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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ECE380: Digital Logic

Sample Exam 2 (KEY)

The exam will be closed book and closed notes. The following questions are representative of the
type of questions that will be on the exam. The exam will cover the lectures 12 and 14-26 from the
class notes. A sheet showing Boolean theorems will be provided. There will be fifteen problems on
the exam: 10 multiple choice (similar to samples 1-11) and 5 written (similar to samples 12-18).
1. Which of the following is the correct truth table for the tri-state buffer shown below:

a)

NONE

e
0
0
1
1

x
0
1
0
1

f
Z
Z
1
1

b)

e
0
0
1
1

x
0
1
0
1

f
Z
Z
0
0

c)

e
0
0
1
1

x
0
1
0
1

f
0
0
Z
Z

d)

2. Convert (A3)16 to octal.


a)
b)
c)
d)
e)

(243)8
(123)8
(223)8
(33)8
none of the above

3. The unsigned number (1111101)2 is equal to which of the following?


a) (175)10
b) (7D)16
c) (175)8
d) Both a and b
e) Both a and c
4. Convert (78)10 the 8-bit 2 complement binary representation.
a)
b)
c)
d)
e)

(01001110)2
(10111110)2
(00110001)2
(10111111)2
none of the above

5. What value is represented by the following 32-bit IEEE


single precision floating point number?
10111111110100000000000000000000
a)
b)
c)
d)
e)

(0.8125)10
(-0.8125)10
(1.625)10
(-1.625)10
none of the above

e
0
0
1
1

x
0
1
0
1

f
1
1
Z
Z

6. Which of the following is the correct truth table for the circuit shown below:

a)

x
0
0
0
0
1
1
1
1

y
0
0
1
1
0
0
1
1

z
0
1
0
1
0
1
0
1

f
0
0
1
1
1
0
0
1

b)

x
0
0
0
0
1
1
1
1

y
0
0
1
1
0
0
1
1

z
0
1
0
1
0
1
0
1

f
0
1
1
0
1
0
0
1

c)

x
0
0
0
0
1
1
1
1

y
0
0
1
1
0
0
1
1

z
0
1
0
1
0
1
0
1

f
1
0
0
1
1
0
0
1

d)

x
0
0
0
0
1
1
1
1

y
0
0
1
1
0
0
1
1

z
0
1
0
1
0
1
0
1

f
1
0
0
1
0
1
1
0

7. Which circuit below implements the function f(x,y,z)=xy+xz+yz?


a)

b)

c)

d) All of the above


e) None of the above
8. Which of the following is the correct truth table for a JK flip-flop?
a)

J
0
0
1
1

K
0
1
0
1

Q(t+1)
Q(t)
0
1
X

b)

J
0
0
1
1

K
0
1
0
1

Q(t+1)
0
1
1
0

c)

J
0
0
1
1

K
0
1
0
1

Q(t+1)
Q(t)
0
1
Q(t)

d)

J
0
0
1
1

K
0
1
0
1

Q(t+1)
Q(t)
1
0
Q(t)

9. Which of the following is the correct truth table for the gated SR latch circuit shown?

a)

Clk
0
1
1
1
1

S
X
0
0
1
1

R
X
0
1
0
1

Q(t+1)
Q(t)
Q(t)
0
1
X

b)

Clk
0
1
1
1
1

S
X
0
0
1
1

R
X
0
1
0
1

Q(t+1)
Q(t)
0
1
Q(t)
X

c)

Clk
0
1
1
1
1

10. Which of the following statements is false?


a) A binary decoder has n inputs and 2n outputs.
b) A binary encoder has 2n inputs and n outputs.
c) A 74138 is a 3-to-8 decoder
d) a demultiplexer is the same circuit as an encoder.
e) None of the above
11. The timing diagram below shows the function of which of the following?

a)
b)
c)
d)
e)

A gated D latch
A positive edge triggered D-type flip-flop
A negative edge triggered D-type flip-flop
All of the above
None of the above

S
X
0
0
1
1

R
X
0
1
0
1

Q(t+1)
Q(t)
Q(t)
1
0
X

12. Write the behavioral VHDL code for a 32-bit adder.


LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all; -- provides arithmetic functions for vectors
ENTITY adder32 IS
PORT ( X, Y : IN UNSIGNED(31 DOWNTO 0);
S
: OUT UNSIGNED(31 DOWNTO 0));
END adder32;
ARCHITECTURE Behavior OF adder32 IS
BEGIN
S <= X + Y;
END Behavior;
13. Give the VHDL architecture construct for a 2-bit priority encoder. Use a PROCESS statement in
your description.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY priority IS
PORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
z : OUT STD_LOGIC );
END priority;
ARCHITECTURE Behavior OF priority IS
BEGIN
PROCESS ( w )
BEGIN
IF w(3) = '1' THEN
y <= "11" ;
ELSIF w(2) = '1' THEN
y <= "10" ;
ELSIF w(1) = '1' THEN
y <= "01" ;
ELSE
y <= "00" ;
END IF ;
END PROCESS ;
z <= '0' WHEN w = "0000" ELSE '1';
END Behavior ;
14. Write and explain the expression for the carry-output of a 4-bit carry lookahead adder.

15. Complete the given timing diagram for the circuit shown below.

16. Add the following 8-bit 2complement numbers.


(11001100)2+(01110011)2
a) What is the 8-bit sum?
b) Is there an overflow?
c) What is the carry-output?
11000000
11001100
01110011
00111111
a) SUM=00111111B
b) No overflow
c) Carry output=1

17. Analyze the following counter circuit to determine the count sequence for the circuit.

Q2
0
0
0
1
1
1
1
0

Q1
0
1
1
0
0
1
1
0

Q0
0
1
0
1
0
1
0
1

18. Convert the following to a NAND-only multilevel circuit. Do not simplify.

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