February 2007
AS6C62256
32K X 8 BIT LOW POWER CMOS SRAM
FEATURES
GENERAL DESCRIPTION
Access time : 55ns
Low power consumption:
Operation current :
15mA (TYP.), VCC = 3.0V
Standby current :
1 A (TYP.), VCC = 3.0V
Wide range power supply : 2.7 ~ 5.5V
Fully Compatible with all Competitors 5V product
Fully Compatible with all Competitors 3.3V product
All inputs and outputs TTL compatible
Fully static operation
Tri-state output
Data retention voltage :1.5V (MIN.)
All products ROHS Compliant
Package : 28-pin 600 mil PDIP
28-pin 330 mil SOP
28-pin 8mm x 13.4mm sTSOP
FUNCTIONAL BLOCK DIAGRAM
DECODER
DQ0-DQ7
I/O DATA
CIRCUIT
CE#
WE#
OE#
CONTROL
CIRCUIT
02/FEB/07, v1.0
The AS6C62256 is well designed for low power
application, and particularly well suited for battery
back-up nonvolatile memory application.
The AS6C62256 operates with wide range power
supply 2.7 ~ 5.5V
.
PIN DESCRIPTION
Vcc
Vss
A0-A14
The AS6C62256 is a 262,144-bit low power CMOS
static random access memory organized as 32,768
words by 8 bits. It is fabricated using very high
performance, high reliability CMOS technology. Its
standby current is stable within the range of
operating temperature.
32Kx8
MEMORY ARRAY
SYMBOL
DESCRIPTION
A0 - A14
Address Inputs
DQ0 DQ7
Data Inputs/Outputs
CE#
Chip Enable Input
WE#
Write Enable Input
OE#
Output Enable Input
VCC
Power Supply
VSS
Ground
COLUMN I/O
Alliance Memory Inc.
Page 1 of 12
February 2007
AS6C62256
32K X 8 BIT LOW POWER CMOS SRAM
PIN CONFIGURATION
1
28
Vcc
A12
27
WE#
A7
26
A13
A6
25
A8
A5
24
A9
A4
A3
A2
A1
AS6C62256
A14
23
A11
22
OE#
21
A10
20
CE#
19
DQ7
18
DQ6
A0
10
DQ0
11
DQ1
12
17
DQ5
DQ2
13
16
DQ4
Vss
14
15
DQ3
OE#
A11
A9
A8
A13
WE#
Vcc
A14
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AS6C62256
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
Vss
DQ2
DQ1
DQ0
A0
A1
A2
sTSOP
PDIP/SOP
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Terminal Voltage with Respect to VSS
SYMBOL
VTERM
Operating Temperature
RATING
-0.5 to 7.0
0 to 70(C grade)
UNIT
V
-40 to 85(I grade)
-65 to 150
1
50
260
TA
Storage Temperature
Power Dissipation
DC Output Current
Soldering Temperature (under 10 sec)
TSTG
PD
IOUT
TSOLDER
W
mA
*Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE
Standby
Output Disable
Read
Write
Note:
CE#
H
L
L
L
OE#
X
H
L
X
WE#
X
H
H
L
I/O OPERATION
High-Z
High-Z
DOUT
DIN
SUPPLY CURRENT
ISB,ISB1
ICC,ICC1
ICC,ICC1
ICC,ICC1
H = VIH, L = VIL, X = Don't care.
02/FEB/07, v1.0
Alliance Memory Inc.
Page 2 of 12
February 2007
AS6C62256
32K X 8 BIT LOW POWER CMOS SRAM
DC ELECTRICAL CHARACTERISTICS
SYMBOL
TEST CONDITION
PARAMETER
Supply Voltage
VCC
*1
Input High Voltage
VIH
*2
Input Low Voltage
VIL
Input Leakage Current
ILI
VCC >= VIN >= VSS
Output Leakage
VCC >= VOUT >= VSS,
ILO
Current
Output Disabled
Output High Voltage
VOH IOH = -1mA
Output Low Voltage
VOL
IOL = 2mA
ICC
Average Operating
Power supply Current
ICC1
Standby Power
Supply Current
ISB
ISB1
Cycle time = Min.
CE# = VIL , II/O = 0mA
MIN.
2.7
2.4 V
- 0.5
-1
-55
Cycle time = 1s
CE#0.2V and II/O = 0mA
other pins at 0.2V or VCC-0.2V
CE# = VIH
-C
CE# >= VCC - 0.2V
-I
TYP.
3.3
-
*5
MAX.
5.5
VCC+0.5
0.6
1
UNIT
V
V
V
A
-1
2.4
-
3.0
-
0.4
V
V
15
45
mA
.
10
mA
1
1
1
3
*4
50
*4
80
mA
A
A
Notes: C = Commercial Temperature I = Industrial Temperature
1. VIH(max) = VCC + 3.0V for pulse width less than 10ns.
2. VIL(min) = VSS - 3.0V for pulse width less than 10ns.
3. Over/Undershoot specifications are characterized, not 100% tested.
4. 10A for special request
5. Typical values are included for reference only and are not guaranteed or tested.
Typical valued are measured at V CC = VCC(TYP.) and TA = 25C
CAPACITANCE (TA = 25? , f = 1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
CIN
CI/O
MIN.
MAX
6
8
UNIT
pF
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
02/FEB/07, v1.0
0.2V to VCC - 0.2V
3ns
1.5V
CL = 50pF + 1TTL, IOH/IOL = -1mA/2mA
Alliance Memory Inc.
Page 3 of 12
February 2007
AS6C62256
32K X 8 BIT LOW POWER CMOS SRAM
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
PARAMETER
SYM
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
tRC
tAA
tACE
tOE
tCLZ*
tOLZ*
tCHZ*
tOHZ*
tOH
(2) WRITE CYCLE
PARAMETER
SYM
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High-Z
tWC
tAW
tCW
tAS
tWP
tWR
tDW
tDH
tOW*
tWHZ*
AS6C62256-55
MIN
MAX.
55
55
55
30
10
5
20
20
10
-
UNIT
AS6C62256-55
MIN.
MAX.
55
50
50
0
45
0
25
0
5
20
UNIT
*These parameters are guaranteed by device characterization, but not production tested.
02/FEB/07, v1.0
Alliance Memory Inc.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Page 4 of 12
February 2007
AS6C62256
32K X 8 BIT LOW POWER CMOS SRAM
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
tRC
Address
tAA
Dout
tOH
Previous Data Valid
Data Valid
READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)
tRC
Address
tAA
CE#
tACE
OE#
tCLZ
Dout
High-Z
tOLZ
tOE
tOH
tOHZ
tCHZ
Data Valid
High-Z
Notes :
1.WE# is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low.
3.Address must be valid prior to or coincident with CE# = low ,; otherwise tAA is the limiting parameter.
4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured 500mV from steady state.
5.At any given temperature and voltage condition, t CHZ is less than tCLZ , tOHZ is less than tOLZ.
02/FEB/07, v1.0
Alliance Memory Inc.
Page 5 of 12
February 2007
AS6C62256
32K X 8 BIT LOW POWER CMOS SRAM
WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)
tWC
Address
tAW
CE#
tCW
tAS
tWP
tWR
WE#
tWHZ
Dout
TOW
High-Z
(4)
tDW
Din
(4)
tDH
Data Valid
WRITE CYCLE 2 (CE# Controlled) (1,2,5,6)
tWC
Address
tAW
CE#
tAS
tWR
tCW
tWP
WE#
tWHZ
Dout
(4)
High-Z
tDW
Din
tDH
Data Valid
Notes :
1.WE#, CE# must be high during all address transitions.
2.A write occurs during the overlap of a low CE#, low WE#.
3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be
placed on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CE# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state.
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured 500mV from steady state.
02/FEB/07, v1.0
Alliance Memory Inc.
Page 6 of 12
February 2007
AS6C62256
32K X 8 BIT LOW POWER CMOS SRAM
DATA RETENTION CHARACTERISTICS
PARAMETER
VCC for Data Retention
Data Retention Current
Chip Disable to Data
Retention Time
Recovery Time
tRC* = Read Cycle Time
SYMBOL
TEST CONDITION
VDR CE# VCC - 0.2V
VCC = 2.0V
IDR
CE# VCC - 0.2V
See Data Retention
tCDR
Waveforms (below)
tR
MIN.
1.5
TYP.
-
MAX.
5.5
UNIT
V
0.5
20
ns
tRC*
ns
DATA RETENTION WAVEFORM
VDR 1.5V
Vcc
Vcc(min.)
Vcc(min.)
tCDR
CE#
02/FEB/07, v1.0
VIH
tR
CE# Vcc-0.2V
Alliance Memory Inc.
VIH
Page 7 of 12
February 2007
AS6C62256
32K X 8 BIT LOW POWER CMOS SRAM
PACKAGE OUTLINE DIMENSION
28 pin 600 mil PDIP Package Outline Dimension
SYM.
A1
A2
B
B1
c
D
E
E1
e
eB
L
S
Q1
02/FEB/07, v1.0
UNIT
INCH.(BASE)
0.010 (MIN)
0.1500.005
0.020 (MAX)
0.055 (MAX)
0.012 (MAX)
1.430 (MAX)
0.6 (TYP)
0.52 (MAX)
0.100 (TYP)
0.625 (MAX)
0.180(MAX)
0.06 (MAX)
0.08(MAX)
o
15 (MAX)
MM(REF)
0.254 (MIN)
3.8100.127
0.508(MAX)
1.397(MAX)
0.304 (MAX)
36.322 (MAX)
15.24 (TYP)
13.208 (MAX)
2.540(TYP)
15.87 (MAX)
4.572(MAX)
1.524 (MAX)
2.032(MAX)
o
15 (MAX)
Alliance Memory Inc.
Page 8 of 12
February 2007
AS6C62256
32K X 8 BIT LOW POWER CMOS SRAM
28 pin 330 mil SOP Package Outline Dimension
SYM.
A
A1
A2
b
c
D
E
E1
e
L
L1
S
y
02/FEB/07, v1.0
UNIT
INCH(BASE)
0.120 (MAX)
0.002(MIN)
0.0980.005
0.016 (TYP)
0.010 (TYP)
0.728 (MAX)
0.340 (MAX)
0.4650.012
0.050 (TYP)
0.05 (MAX)
0.0670.008
0.047 (MAX)
0.003(MAX)
o
o
0 10
MM(REF)
3.048 (MAX)
0.05(MIN)
2.4890.127
0.406(TYP)
0.254(TYP)
18.491 (MAX)
8.636 (MAX)
11.8110.305
1.270(TYP)
1.270 (MAX)
1.702 0.203
1.194 (MAX)
0.076(MAX)
o
o
0 10
Alliance Memory Inc.
Page 9 of 12
February 2007
AS6C62256
32K X 8 BIT LOW POWER CMOS SRAM
28 pin 8mm x 13.4mm sTSOP Package Outline Dimension
SYM.
A
A1
A2
b
c
Db
E
e
D
L
L1
y
UNIT
INCH(BASE)
MM(REF)
0.047 (MAX)
0.0040.002
0.0390.002
0.006 (TYP)
0.010 (TYP)
0.4650.004
0.3150.004
0.022 (TYP)
0.5280.008
0.0200.004
0.03150.004
0.08(MAX)
o
o
0 5
1.20 (MAX)
0.100.05
1.000.05
0.15(TYP)
0.254(TYP)
11.800.10
8.000.10
0.55(TYP)
13.400.20
0.500.10
0.800.10
0.003(MAX)
o
o
0 5
NoteE dimension is not including end flash. The total of both sides end flash is not above 0.3mm.
02/FEB/07, v1.0
Alliance Memory Inc.
Page 10 of 12
February 2007
AS6C62256
32K X 8 BIT LOW POWER CMOS SRAM
ORDERING INFORMATION
Ordering Codes
Alliance
Organization VCC range
Operating
Speed
Temp
ns
Commercial ~
0 C to 70 C
55
Commercial ~
0 C to 70 C
55
Industrial ~
-40C to 85 C
55
Commercial ~
0 C to 70 C
55
Industrial ~
-40C to 85 C
55
Package
AS6C62256-55PCN
32k x 8
2.7-5.5V
28pin 600mil PDIP
AS6C62256-55SCN
32k x 8
2.7-5.5V
28pin 330mil SOP
AS6C62256-55SIN
32k x 8
2.7-5.5V
28pin 330mil SOP
AS6C62256-55STCN
32k x 8
2.7-5.5V
28pin sTSOP (8 x 13.4 mm)
AS6C62256-55STIN
32k x 8
2.7-5.5V
28pin sTSOP (8 x 13.4 mm)
Part numbering system
AS6C
62256
low Device
power Number
SRAM 62256
prefix
- 55
Package Options:
P = 28 pin 600 mil P-DIP
Access S = 28 pin 330 mil SOP
Time ST = 28 pin sTSOP (8mm x 13.4 mm)
02/FEB/07, v1.0
Alliance Memory Inc.
Temperature Range:
N = Lead
C = Commercial
Free ROHS
(0C to +70 C)
Compliant
I = Industrial
Part
(-40 to +85 C)
Page 11 of 12
February 2007
AS6C62256
Rev 1
Alliance Memory, Inc.
1116 South Amphlett, #2,
San Mateo, CA 94402
Tel: 650-525-3737
Fax: 650-525-0449
Copyright Alliance Memory
All Rights Reserved
Part Number: AS6C62256
Document Version: v. 1.0
www.alliancememory.com
Copyright 2003 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of
Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this
document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data
contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any
time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in
this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide,
any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any
product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or
warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in
Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's
Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights,
trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in
life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of
Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all
claims arising from such use.
02/FEB/07, v1.0
Alliance Memory Inc.
Page 12 of 12
