Doc.

No: 04U1-02034
Rev.:2d2

Approved Date: 12 / 3 / 2002

UMC 0.18m 1P6M SALICIDE

Mixed-Mode/RF CMOS MODEL

Rev: 2d2

1.Contents
1.Contents

Page
0

2.Revision History

3.Description

Doc. No: 04U1-02034

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2.Revision History:

Ver.

2d0

Date

From

To

11/12/2002

1.

The parameter of MOS is Nf_N

1.

in ADS

2d1

11/30/2002

Nf in ADS

2.

Model name is MIMCAPS_RF

2.

3.

W/O Cjgate in MOS model

4.

W/O voltage coefficient and

3.

Add Cjgate into MOS model

temperature coefficient in

4.

Add voltage coefficient and temperature

5.

1.

coefficient into resistor model

W/O voltage coefficient in MIM

5. Add voltage coefficient in MIM model

model

6. Re-extract Inductor and MIS models

Different MIM trend for

1.

HSPICE and ELDO

12/3/2002

2.

2.

RESISTOR model

coefficient into model card

b. Rsh for N+poly=110 ohm/sq

b. Rsh for N+poly=113 ohm/sq

PAD model: w/o indexa

3. PAD model: add indexa

The range of spiral top metal

4.

width (W): 6um ~ 25um.

5.

RESISTOR model
a. Add absolute value of voltage

coefficient

4.

Modify the voltage coefficient of

MIM model

a. W/O absolute value of voltage

3.

Model name has modified to

MIMCAPM_RF.

resistor model

2d2

The parameter of MOS is modified to

The range of spiral top metal

width (W): 6um ~ 20um.

The range of SR Capacitor :

5.

The range of SR Capacitor :

10um < l, w < 70um and the

10um <= l, w <= 70um and the

range of MR Capacitor :

range of MR Capacitor :

1 < nx, ny < 7

1 < =nx, ny <= 7

Remark
(purpose)
original

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This document provides information on the RF model, including N/P MOSFET

(1.8V & 3.3V), Spiral inductor (circular), MIM capacitor (multi-rectangle &
single-rectangle), MIS varactor, P+/N-Well varactor, Resistor (N+ Poly & P+ Poly
& HR Poly), and Shielding Pad (PAD). These devices are fabricated using the
UMC 0.18 um 1P6M salicide Mixed-Mode/ RF process.
Four standard simulators (HSPICE, ELDO, SPECTRE, and ADS) are used to
verify the RF models and the accuracy is acceptable for RF modeling. Layout
structures of the devices are recommended to be the same as those of devices in the
PCELL library provided for the purpose of avoiding model characteristic
distortion.
The models used in this document are described simply as follows:

1. Description

2. N/P MOSFET 1.8V Model

3. N/P MOSFET 3.3V Model

23

4. Spiral Inductor Model

40

5. MIS Varactor Model

50

6. P+/N-well Varactor Model

57

7. MIM Capacitor Model

63

8. N+/P+ non-salicided Poly Resistor Model

70

9. HR non-salicided Poly Resistor Model

79

10. Shielding Pad

86

Appendix

90

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2. N/P MOSFET 1.8V Model

2.1 Contents

UMC 0.18 m RF CMOS Process

N_L18W500_18_RF/N_PO7W500_18_RF
P_L18W500_18_RF/P_PO7W500_18_RF

2.1 Contents
2.2 Criteria of N/P MOSFET model
2.3 Model Description and Parameters
2.4 Spice parameter list
2.5 Model verification

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Approved Date: 12 / 3 / 2003

2.2 Criteria of N/P MOSFET Model

The 1.8V Model is divided into 4 sections. The first one, N_L18W500_18_RF, is valid for 1.8V
NMOS devices with scaling gate finger numbers from 5 to 21 at a fixed length of 0.18um and a
fixed finger width of 5um. The second, N_PO7W500_18_RF, is valid for 1.8V NMOS devices with
scaling gate lengths from 0.2um to 0.5um at a fixed finger number of 7 and a fixed finger width of
5um. The third section, P_L18W500_18_RF, is valid for 1.8V PMOS devices with scaling gate
finger numbers from 5 to 21 at a fixed length of 0.18um and a fixed finger width of 5um. The last
one, P_PO7W500_18_RF, is valid for 1.8V PMOS devices with scaling gate lengths from 0.2um to
0.5um at a fixed finger number of 7 and a fixed finger width of 5um.
l

Specific N/P MOSFET operation description:

a.
b.
c.
d.

e.
f.
g.
h.
i.
j.
l

Effective frequency range: 100MHz ~10GHz

Effective DC voltage range: |Vg| = 0.6 ~ 1.8V, |Vd| = 0V~1.8V
Effective applicable voltage range of s-parameters: |Vg| = 0.6 ~ 1.8V, |Vd| = 0.6V~1.8V
Gate length tuning range (L): 0.18 m ~ 0.5 m
** Notice: The recommended gate length range of the N_PO7W500_18_RF/ P_PO7W500_18_RF
model is from 0.2 m to 0.5 m **
Unit translated gate length (L_um): 0.18 ~ 0.5
Total gate width (Wtotal = W*NF): 25m ~ 105m
Single gate finger width (W): 5.0 m
Gate finger number range (NF): 5 ~ 21
Empirical scalable formula is used in the standard BSIM3v3.2 RF extension model.
Gate finger numbers can be even or odd. We suggest using an odd number.

Extracted parameters and simulation results:

a. Some specific parameters in this document can be calculated from the scalable formulas
by giving a specific L (gate length) or NF (finger number).
b. In this document, the MOSFET Based Band Models are released from UMC.
c. Please ignore the following simulation warning messages:
Warning: Pd=0 Ps=0 less than W.
Warning: Noff is too large.
Warning: Pdiblc2 is negative.
d. Please use the RMS error function to calculate the errors between the measured and
simulated data. (See Appendix A)

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Model validation:
a. Two port data is measured by 50 impedance system.
b. One port is defined as the output port connected to ground.
c. Simulation frequency is from 100MHz to 10GHz.

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2.3 Device Description and Model Parameters

2.3.1 Extension equivalent circuit model
The MOSFET extension equivalent circuit model is based on the BSIM3v3.2 model to extract
the desired RF model. The results of two-port S-parameters de-embedded with open pad are used
to extract the model parameters. Different geometry MOSFET devices are measured and the
results are used to verify the accuracy of the model. The schematic of the extended BSIM3v3 RF
model is showed in Fig. 2-1. Port1 is connected to poly gate and port2 is connected to drain. The
intrinsic dc, cv and noise characteristics are modeled by BSIM3v3.2. The passive parasitic
components and diode elements are described as follows:
(1) Rgate is used to model the equivalent gate resistance.
(2) Rsub1, Rsub2 & Rsub3 represent the substrate loss.
(3) Djdb_area and Djdb_perim are used to model source/drain bottom junction and sidewall
junction capacitance.
(4) Djdb_swg and Djsb_swg are used to model source/drain sidewall junction capacitance
per unit length at gate sidewall.
(5) Cd & Cgs_ext represent the total equivalent capacitance between drain, source and gate.
(6) Disable the junction diode in standard BSIM3v3 by setting AD = AS =PD = PS = 0.
(7) Lsouce and Ldrain are used to model the parasitic inductance effect.
G

Rgate
Cgs_ext
Cd

Ldrain

Lsource

S
Djsb_perim

Djdb_perim
Djsb_swg

Djdb_swg

Djsb_area

Djdb_area
Rsub3

Rsub2
Rsub1

Fig. 2-1 RF N/P MOSFET Extension Model

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2.3.2 RF MOSFET layout:

The layout of the RF MOSFET is shown in Fig. 2-2 and PCell layout is provided in the
corresponding electronic file. It is important to remember that model parameters are strongly
dependent on the device layouts at RF band. Therefore, to get the accurate characteristics of the
demonstrated devices, the layout structures should not be modified. The MOSFET layout has
some distinguishing characteristics, described as follows:
(1)
(2)
(3)
(4)
(5)

Reducing the overlap capacitance between Gate and Source.

Reducing the gate resistance by putting parallel metal upon the finger gate.
Double-ended gate structure is used to reduce RF noise.
Grounded substrate surrounds the core device and is viewed as a part of RF device.
Symmetrical S/D structure is used for the modeling purpose.

Drain

Gate

Bulk
Source
Diffusion Dummy Block

Fig. 2-2 RF N/P MOSFET 1.8V layout

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2.3.3 Simulated RMS errors

Table 2-1 RMS Errors of measured and simulated S-parameters of N MOSFETs

L_um*NF*W
RMS_S11 (%)
RMS_S22 (%)
RMS_S21 (%)
RMS_S12 (%)
0.18*5*5

2.643

2.558

1.661

7.196

0.18*7*5

4.102

3.614

1.647

8.419

0.18*9*5

5.813

5.066

1.324

10.660

0.18*13*5

9.011

6.176

0.975

13.770

0.18*17*5

11.670

6.922

1.776

15.540

0.18*21*5

13.460

6.812

2.423

16.100

0.25*7*5

3.385

2.473

1.105

5.878

0.35*7*5

3.863

2.160

1.205

5.908

0.5*7*5

5.209

2.373

1.500

6.596

Table 2-2 RMS Errors of measured and simulated S-parameters of P MOSFETs

L_um*NF*WF

RMS_S11
(%)

RMS_S22
(%)

RMS_S21
(%)

RMS_S12
(%)

0.18*5*5

1.516

1.022

1.030

2.843

0.18*7*5

1.960

1.468

0.794

3.492

0.18*9*5

2.740

1.996

1.399

3.957

0.18*13*5

3.566

2.987

1.256

6.184

0.18*17*5

4.498

3.931

1.568

8.230

0.18*21*5

5.118

4.517

1.822

10.200

0.25*7*5

2.351

1.295

2.572

3.951

0.35*7*5

3.207

1.524

3.495

4.403

0.5*7*5

5.054

1.813

4.768

8.173

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2.3.4 Empirical scaling formula

Scaling rule is a method for IC designers to predict device performance which has not been
measured during the modeling extraction. In this document, empirical scaling rule is provided and
the scaling rule is an optional choice for users. After modeling all of the devices, we use regression
analysis to obtain the relationship between the model parameters, gate length (L) and gate finger
number (NF). The scaling formulas are listed in Table 2-3 ~ Table 2-6. Table 2-7 shows the area
and perimeter parameters of extension S/D junction diodes.

Table 2-3 Scalable formulas for 1.8V NMOSFETs with different Finger Numbers
Parameter

Scaling formula

MOSFET

N MOSFET BSIM3v3 RF SPICE MODEL

P_RG ( )

-0.8966+107.7889/NF-364.622/(NF*NF)

P_CD (F)

(0.9008+0.2570*NF+0.2297*(NF*NF))*1E-15

P_CGS (F)

(-2.0811+1.4629*NF+0.009752*(NF*NF))*1E-15

P_LD = P_LS (H)

P_RSUB1 ( )
P_RSUB2 = P_RSUB3 ( )
P_WR

(24.8301+396.8130/NF-1112.3751/(NF*NF))*1E-12
120.783-258.189/NF+939.7544/(NF*NF)
2
(841.3723+1543.5167/NF-4288.7956/(NF*NF))*1E-3

Table 2-4 Scalable formulas for 1.8V NMOSFETs with different Gate Lengths
Parameter

Scaling formula

MOSFET

N MOSFET BSIM3v3 RF SPICE MODEL

P_RG ( )

30.0038-10.2118/L_um+0.9998/(L_um*L_um)

P_CD (F)

(16.3846-30.4825*L_um+21.6092*(L_um*L_um))*1E-15

P_CGS (F)

(0.5460+55.9389*L_um-66.3582*(L_um*L_um))*1E-15

P_LD = P_LS (H)

P_RSUB1 ( )
P_RSUB2 = P_RSUB3 ( )
P_NLX
P_PCLM

5.8E-11
93.1907-8.5107/L_um+1.8334/(L_um*L_um)
2
(475.2494-439.9303*L_um+1066.9945*(L_um*L_um))*1E-9
0.1422+0.0846/L_um+0.0043/(L_um*L_um)

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Table 2-5 Scalable formulas for 1.8V PMOSFETs with different Finger Numbers
Parameter

Scaling formula

MOSFET

P MOSFET BSIM3v3 RF SPICE MODEL

P_RG ( )

-6.3044+287.3248/NF-996.0158/(NF*NF)

P_CD (F)

(3.0460+2.0138*NF+0.0467*(NF*NF))*1E-15

P_CGS (F)

(0.6197+0.0205*NF+0.0344*(NF*NF))*1E-15

P_LD = P_LS (H)

P_RSUB1 ( )
P_RSUB2 = P_RSUB3 ( )
P_WR

(52.1818+160.1501/NF+649.7715/(NF*NF))*1E-12
70.5835-147.6535/NF-144.7453/(NF*NF)
1
(808.0254+2116.1626/NF-2687.8868/(NF*NF))*1E-3

Table 2-6 Scalable formulas for 1.8V PMOSFETs with different Gate Lengths
Parameter

Scaling formula

MOSFET

P MOSFET BSIM3v3 RF SPICE MODEL

P_RG ( )

72.7967-25.7375/L_um+2.8321/(L_um*L_um)

P_CD (F)

(15.8033+4.660*L_um-8.9333*(L_um*L_um))*1E-15

P_CGS (F)

(3.7967-18.190*L_um+36.7333*(L_um*L_um))*1E-15

P_LD = P_LS (H)

P_RSUB1 ( )
P_RSUB2 = P_RSUB3 ( )
P_NLX
P_PCLM

9E-11
157.35-17.0875/L_um+1.3563/(L_um*L_um)
1
(616.3333-1840*L_um+2266.6670*(L_um*L_um))*1E-9
2.7030-0.6375/L_um+0.1313/(L_um*L_um)

10

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Table 2-7 Junction Diode parameters

Parameter
P_Djdb_area

Definition
Drain bottom junction diode area

P_Djdb_perim Drain sidewall junction diode perimeter

P_Djdb_swg

Drain gate sidewall junction diode perimeter

P_Djsb_area

Source bottom junction diode area

P_Djsb_perim Source sidewall junction diode perimeter

P_Djsb_swg

Source gate sidewall junction diode perimeter

# Bottom junction diode area per source/drain region

= 0.85 m *5.0 m

# Source/Drain sidewall junction diode perimeter

Refer to the following parameter list

# Source/Drain gate sidewall junction diode perimeter

= 5.0 m * finger number

11

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2.4 Spice model parameter list

# UMC_18_NMOS_1p8 RF BSIM3v3 SPICE MODEL
# Scalable with Finger Number
*
*1= Drain 2=Gate 3= Source 4=Bulk
*
.SUBCKT N_L18W500_18_RF 1 2 3 4 NF=21
*
*
* #### Define Bsim3v3 Model Variable #####
*
.PARAM P_WR='(841.3723+1543.5167/NF-4288.7956/(NF*NF))*1E-3'
*
* #### Define RF Extension Model Variable #####
*
.PARAM P_RG='-0.8966+107.7889/NF-364.622/(NF*NF)'
.PARAM P_CD='(0.9008+0.2570*NF+0.2297*(NF*NF))*1E-15'
.PARAM P_CGS='(-2.0811+1.4629*NF+0.009752*(NF*NF))*1E-15'
.PARAM P_LD='(24.8301+396.8130/NF-1112.3751/(NF*NF))*1E-12'
.PARAM P_LS='(24.8301+396.8130/NF-1112.3751/(NF*NF))*1E-12'
.PARAM P_DJDB_A='(4.25*((NF+1)/2))*1E-12'
.PARAM P_DJDB_P='(1.7*((NF+1)/2)+5)*1E-6'
.PARAM P_DJDB_G='(5*NF)*1E-6'
.PARAM P_DJSB_A='(4.25*((NF+1)/2))*1E-12'
.PARAM P_DJSB_P='(1.7*((NF+1)/2)+5)*1E-6'
.PARAM P_DJSB_G='(5*NF)*1E-6'
.PARAM P_RSUB1='120.783-258.189/NF+939.7544/(NF*NF)'
.PARAM P_RSUB2=2
.PARAM P_RSUB3=2
*
* --------- Gate network -----------------------------Cgs_ext 21 30 P_CGS
Rgate 2 21 P_RG
*
* --------- Drain network ----------------------------Ldrain 1 11 P_LD
Lsource 30 3 P_LS
Cd 11 30 P_CD
*
* --------- Substrate network ------------------------* Diodes are for n-type MOS transistors
*
Djdb_area 12 11
+ bsim_diode_area
+ AREA = P_DJDB_A
Djdb_perim 12 11
+ bsim_diode_perim
+ AREA = P_DJDB_P
Djdb_swg 12 11
+ bsim_diode_swg
+ AREA = P_DJDB_G

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*
Djsb_area 31 30
+ bsim_diode_area
+ AREA = P_DJSB_A
Djsb_perim 31 30
+ bsim_diode_perim
+ AREA = P_DJSB_P
Djsb_swg 31 30
+ bsim_diode_swg
+ AREA = P_DJSB_G
*
RSUB2 12 40 P_RSUB2
RSUB3 31 40 P_RSUB3
RSUB1 40 4 P_RSUB1
*
* --------- Ideal mos transistor ---------------------MAIN 11 21 30 40
+ bsim_mos_transistor
+ L = 1.8E-07
+ W = 5E-6
+ AD = 0
+ AS = 0
+ PD = 0
+ PS = 0
+ M = NF
*
* -------- DIODES & NMOSFET SPICE PARAMETERS -----------*
.MODEL bsim_diode_area D
+ CJ0 = 0.00103 VJ = 0.813 M = 0.443 IS = 1E-06 N = 1
*
.MODEL bsim_diode_perim D
+ CJ0 = 1.34E-10 VJ = 0.88 M = 0.33 IS = 7E-11 N = 1
*
.MODEL bsim_diode_swg D
+ CJ0 = 5E-10 VJ = 0.88 M = 0.33 IS = 7E-11 N = 1
*
.model bsim_mos_transistor NMOS
+ LEVEL = 49 VERSION = 3.2 BINUNIT = 1 MOBMOD = 1
+ CAPMOD = 2 NQSMOD = 0 NOIMOD = 2 TOX = 4.2E-09
+ TOXM = 4.2E-09 XJ = 1.6E-07 NCH = 3.745E+17 RSH = 8
+ NGATE = 1E+23 VTH0 = 0.3075 K1 = 0.4578 K2 = -0.02638
+ K3 = -10.88 K3B = 0.2379 W0 = -8.813E-08 NLX = 4.279E-07
+ DVT0 = 0.4042 DVT1 = 0.3237 DVT2 = -0.8602 DVT0W = 0.383
+ DVT1W = 6E+05 DVT2W = -0.025 LINT = 1.587E-08 WINT = 1.022E-08
+ DWG = -3.396E-09 DWB = 1.346E-09 U0 = 332.1 UA = -1.17E-09
+ UB = 2.407E-18 UC = 4.355E-11 VSAT = 8.1E+04 A0 = 1.93
+ AGS = 0.5072 B0 = 1.486E-06 B1 = 9.064E-06 KETA = 0.01752
+ A1 = 0 A2 = 1 VOFF = -0.1208 NFACTOR = 1.038
+ CIT = -0.001511 CDSC = 0.002175 CDSCD = 0 CDSCB = 0.0008241
+ ETA0 = 0.005504 ETAB = -0.001459 DSUB = 0.001592 PCLM = 0.741
+ PDIBLC1 = 0.005061 PDIBLC2 = 0.006001 PDIBLCB = 0 DROUT = 0.001592
+ PSCBE1 = 4.866E+08 PSCBE2 = 3E-08 PVAG = -0.2958 RDSW = 9.905
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+ PRWG = 1.1 PRWB = 0 WR = P_WR ALPHA0 = 0

+ ALPHA1 = 0 BETA0 = 30 XPART = 1 CGSO = 1.55E-10
+ CGDO = 1.55E-10 CGBO = 0 CGSL = 3E-11 CGDL = 3E-11
+ CKAPPA = 0.6 CF = 2.33E-11 CLC = 1E-07 CLE = 0.6
+ DLC = 4E-08 DWC = 0 VFBCV = -1 NOFF = 1
+ VOFFCV = 0 ACDE = 1 MOIN = 15 NOIA = 1.31826E+19
+ NOIB = 1.44544E+05 NOIC = -1.24516E-12 EM = 4.1E+07 AF = 1
+ EF = 0.92 KF = 0 LMIN = 1.8E-07 LMAX = 1.805E-07
+ WMIN = 5E-06 WMAX = 1.05E-04 XL = -1.05E-08 XW = 0
+ JS = 1E-06 JSW = 7E-11 CJ = 0.00103 MJ = 0.443
+ PB = 0.813 CJSW = 1.34E-10 MJSW = 0.33 TNOM = 25
+ UTE = -1.286 KT1 = -0.2255 KT1L = -4.175E-09 KT2 = -0.02527
+ UA1 = 2.153E-09 UB1 = -2.673E-18 UC1 = -3.832E-11 AT = 1.449E+04
+ PRT = -46.18 XTI = 3 WL = 0 WLN = 1
+ WW = 7.262E-16 WWN = 1 WWL = 0 LL = -1.062E-15
+ LLN = 1 LW = 2.996E-15 LWN = 1 LWL = 0
+ LLC = -6.64E-15 LWC = 0 LWLC = 0 WLC = 0
+ WWC = 0 WWLC = 0 LVTH0 = -0.0001 WVTH0 = 0.06027
+ PVTH0 = 0 LNLX = -2.854E-08 WNLX = 0 PNLX = 0
+ LNFACTOR = 0.032 WUA = -1.88E-11 WU0 = 0.54 PUB = 3.8E-20
+ PW0 = 1.3E-09 LUA = 1.5E-11 LUB = 9.76E-20 WRDSW = 0
+ WETA0 = 0 WETAB = 0 LETA0 = 0.001574 LETAB = 0
+ PETA0 = 0 PETAB = 0 WPCLM = 0 WVOFF = -0.0004078
+ LVOFF = -0.004208 PVOFF = -0.0003788 WA0 = -0.04731 LA0 = -0.4667
+ PA0 = -0.02649 WAGS = 0.004242 LAGS = 0.3028 PAGS = 0
+ WKETA = 0 LKETA = -0.01942 PKETA = 0 WUTE = 0.06373
+ LUTE = 0 PUTE = 0 WVSAT = 5066 LVSAT = 0
+ PVSAT = 0 LPDIBLC2 = -0.004752 WAT = 7067 WPRT = 0
+ ACM = 3 LDIF = 8E-08 HDIF = 2.6E-07 N = 1
+ PHP = 0.88 CJGATE = 5E-10 CTP = 0.000914 PTP = 0.000924
+ CTA = 0.000919 PTA = 0.00158 ELM = 5 TLEVC = 1
.ENDS
*
# UMC_18_NMOS_1p8 RF BSIM3v3 SPICE MODEL
# Scalable with Gate Length
*
*1= Drain 2=Gate 3= Source 4=Bulk
.SUBCKT N_PO7W500_18_RF 1 2 3 4 L=0.5u
*
.PARAM L_um='L*1E6'
*
* #### Define Bsim3v3 Model Variable #####
*
.PARAM P_NLX='(475.2494-439.9303*L_um+1066.9945*(L_um*L_um))*1E-9'
.PARAM P_PCLM='0.1422+0.0846/L_um+0.0043/(L_um*L_um)'
*
* #### Define RF Extension Model Variable #####
*
.PARAM P_RG='30.0038-10.2118/L_um+0.9998/(L_um*L_um)'
.PARAM P_CD='(16.3846-30.4825*L_um+21.6092*(L_um*L_um))*1E-15'
.PARAM P_CGS='(0.5460+55.9389*L_um-66.3582*(L_um*L_um))*1E-15'
.PARAM P_LD=5.8E-11
.PARAM P_LS=5.8E-11

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Approved Date: 12 / 3 / 2003

.PARAM P_DJDB_A='(4.25*((7+1)/2))*1E-12'
.PARAM P_DJDB_P='(1.7*((7+1)/2)+5)*1E-6'
.PARAM P_DJDB_G='(5*7)*1E-6'
.PARAM P_DJSB_A='(4.25*((7+1)/2))*1E-12'
.PARAM P_DJSB_P='(1.7*((7+1)/2)+5)*1E-6'
.PARAM P_DJSB_G='(5*7)*1E-6'
.PARAM P_RSUB1='93.1907-8.5107/L_um+1.8334/(L_um*L_um)'
.PARAM P_RSUB2=2
.PARAM P_RSUB3=2
*
* --------- Gate network -----------------------------Cgs_ext 21 30 P_CGS
Rgate 2 21 P_RG
*
* --------- Drain network ----------------------------Ldrain 1 11 P_LD
Lsource 30 3 P_LS
Cd 11 30 P_CD
*
* --------- Substrate network ------------------------* Diodes are for n-type MOS transistors
*
Djdb_area 12 11
+ bsim_diode_area
+ AREA = P_DJDB_A
Djdb_perim 12 11
+ bsim_diode_perim
+ AREA = P_DJDB_P
Djdb_swg 12 11
+ bsim_diode_swg
+ AREA = P_DJDB_G
*
Djsb_area 31 30
+ bsim_diode_area
+ AREA = P_DJSB_A
Djsb_perim 31 30
+ bsim_diode_perim
+ AREA = P_DJSB_P
Djsb_swg 31 30
+ bsim_diode_swg
+ AREA = P_DJSB_G
*
RSUB2 12 40 P_RSUB2
RSUB3 31 40 P_RSUB3
RSUB1 40 4 P_RSUB1
*
* --------- Ideal mos transistor ---------------------MAIN 11 21 30 40
+ bsim_mos_transistor
+L=L
+ W = 5u
+ AD = 0
+ AS = 0
15

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+ PD = 0
+ PS = 0
+M=7
*
* -------- DIODES & NMOSFET SPICE PARAMETERS -----------*
.MODEL bsim_diode_area D
+ CJ0 = 0.00103 VJ = 0.813 M = 0.443 IS = 1E-06 N = 1
*
.MODEL bsim_diode_perim D
+ CJ0 = 1.34E-10 VJ = 0.88 M = 0.33 IS = 7E-11 N = 1
*
.MODEL bsim_diode_swg D
+ CJ0 = 5E-10 VJ = 0.88 M = 0.33 IS = 7E-11 N = 1
*
.model bsim_mos_transistor NMOS
+ LEVEL = 49 VERSION = 3.2 BINUNIT = 1 MOBMOD = 1
+ CAPMOD = 2 NQSMOD = 0 NOIMOD = 2 TOX = 4.2E-09
+ TOXM = 4.2E-09 XJ = 1.6E-07 NCH = 3.745E+17 RSH = 8
+ NGATE = 1E+23 VTH0 = 0.3075 K1 = 0.4578 K2 = -0.02638
+ K3 = -10.88 K3B = 0.2379 W0 = -8.813E-08 NLX = P_NLX
+ DVT0 = 0.4042 DVT1 = 0.3237 DVT2 = -0.8602 DVT0W = 0.383
+ DVT1W = 6E+05 DVT2W = -0.025 LINT = 1.587E-08 WINT = 1.022E-08
+ DWG = -3.396E-09 DWB = 1.346E-09 U0 = 332.1 UA = -1.17E-09
+ UB = 2.407E-18 UC = 4.355E-11 VSAT = 8.1E+04 A0 = 1.93
+ AGS = 0.5072 B0 = 1.486E-06 B1 = 9.064E-06 KETA = 0.01752
+ A1 = 0 A2 = 1 VOFF = -0.1208 NFACTOR = 1.038
+ CIT = -0.001511 CDSC = 0.002175 CDSCD = 0 CDSCB = 0.0008241
+ ETA0 = 0.005504 ETAB = -0.001459 DSUB = 0.001592 PCLM = P_PCLM
+ PDIBLC1 = 0.005061 PDIBLC2 = 0.006001 PDIBLCB = 0 DROUT = 0.001592
+ PSCBE1 = 4.866E+08 PSCBE2 = 3E-08 PVAG = -0.2958 RDSW = 9.905
+ PRWG = 1.1 PRWB = 0 WR = 0.97 ALPHA0 = 0
+ ALPHA1 = 0 BETA0 = 30 XPART = 0 CGSO = 1.35E-10
+ CGDO = 1.35E-10 CGBO = 0 CGSL = 2E-11 CGDL = 2E-11
+ CKAPPA = 0.6 CF = 1.533E-10 CLC = 1E-07 CLE = 0.6
+ DLC = 4E-08 DWC = 2E-07 VFBCV = -1 NOFF = 1
+ VOFFCV = 0 ACDE = 1 MOIN = 15 NOIA = 1.31826E+19
+ NOIB = 1.44544E+05 NOIC = -1.24516E-12 EM = 4.1E+07 AF = 1
+ EF = 0.92 KF = 0 LMIN = 2E-07 LMAX = 5E-07
+ WMIN = 5E-06 WMAX = 3.5E-05 XL = -1.05E-08 XW = 0
+ JS = 1E-06 JSW = 7E-11 CJ = 0.00103 MJ = 0.443
+ PB = 0.813 CJSW = 1.34E-10 MJSW = 0.33 TNOM = 25
+ UTE = -1.286 KT1 = -0.2255 KT1L = -4.175E-09 KT2 = -0.02527
+ UA1 = 2.153E-09 UB1 = -2.673E-18 UC1 = -3.832E-11 AT = 1.449E+04
+ PRT = -46.18 XTI = 3 WL = 0 WLN = 1
+ WW = 7.262E-16 WWN = 1 WWL = 0 LL = -1.062E-15
+ LLN = 1 LW = 2.996E-15 LWN = 1 LWL = 0
+ LLC = -6.64E-15 LWC = 0 LWLC = 0 WLC = 0
+ WWC = 0 WWLC = 0 LVTH0 = -0.0001 WVTH0 = 0.06027
+ PVTH0 = 0 LNLX = -2.854E-08 WNLX = 0 PNLX = 0
+ LNFACTOR = 0.032 WUA = -1.88E-11 WU0 = 0.54 PUB = 3.8E-20
+ PW0 = 1.3E-09 LUA = 1.5E-11 LUB = 9.76E-20 WRDSW = 0
+ WETA0 = 0 WETAB = 0 LETA0 = 0.001574 LETAB = 0
16

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+ PETA0 = 0 PETAB = 0 WPCLM = 0 WVOFF = -0.0004078

+ LVOFF = -0.004208 PVOFF = -0.0003788 WA0 = -0.04731 LA0 = -0.4667
+ PA0 = -0.02649 WAGS = 0.004242 LAGS = 0.3028 PAGS = 0
+ WKETA = 0 LKETA = -0.01942 PKETA = 0 WUTE = 0.06373
+ LUTE = 0 PUTE = 0 WVSAT = 5066 LVSAT = 0
+ PVSAT = 0 LPDIBLC2 = -0.004752 WAT = 7067 WPRT = 0
+ ACM = 3 LDIF = 8E-08 HDIF = 2.6E-07 N = 1
+ PHP = 0.88 CJGATE = 5E-10 CTP = 0.000914 PTP = 0.000924
+ CTA = 0.000919 PTA = 0.00158 ELM = 5 TLEVC = 1
.ENDS
*
# UMC_18_PMOS_1p8 RF BSIM3v3 SPICE MODEL
# Scalable with Finger Number
*
*1= Drain 2=Gate 3= Source 4=Bulk
*
.SUBCKT P_L18W500_18_RF 1 2 3 4 NF=21
*
*
* #### Define Bsim3v3 Model Variable #####
*
.PARAM P_WR='(808.0254+2116.1626/NF-2687.8868/(NF*NF))*1E-3'
*
* #### Define RF Extension Model Variable #####
*
.PARAM P_RG='-6.3044+287.3248/NF-996.0158/(NF*NF)'
.PARAM P_CD='(3.0460+2.0138*NF+0.0467*(NF*NF))*1E-15'
.PARAM P_CGS='(0.6197+0.0205*NF+0.0344*(NF*NF))*1E-15'
.PARAM P_LD='(52.1818+160.1501/NF+649.7715/(NF*NF))*1E-12'
.PARAM P_LS='(52.1818+160.1501/NF+649.7715/(NF*NF))*1E-12'
.PARAM P_DJDB_A='(4.25*((NF+1)/2))*1E-12'
.PARAM P_DJDB_P='(1.7*((NF+1)/2)+5)*1E-6'
.PARAM P_DJDB_G='(5*NF)*1E-6'
.PARAM P_DJSB_A='(4.25*((NF+1)/2))*1E-12'
.PARAM P_DJSB_P='(1.7*((NF+1)/2)+5)*1E-6'
.PARAM P_DJSB_G='(5*NF)*1E-6'
.PARAM P_RSUB1='70.5835-147.6535/NF-144.7453/(NF*NF)'
.PARAM P_RSUB2=1
.PARAM P_RSUB3=1
*
* --------- Gate network -----------------------------Cgs_ext 21 30 P_CGS
Rgate 2 21 P_RG
*
* --------- Drain network ----------------------------Ldrain 1 11 P_LD
Lsource 30 3 P_LS
Cd 11 30 P_CD
*
* --------- Substrate network ------------------------* Diodes are for p-type MOS transistors
*
Djdb_area 11 12
+ bsim_diode_area
+ AREA = P_DJDB_A
Djdb_perim 11 12
+ bsim_diode_perim
+ AREA = P_DJDB_P
Djdb_swg 11 12
+ bsim_diode_swg

17

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+ AREA = P_DJDB_G
*
Djsb_area 30 31
+ bsim_diode_area
+ AREA = P_DJSB_A
Djsb_perim 30 31
+ bsim_diode_perim
+ AREA = P_DJSB_P
Djsb_swg 30 31
+ bsim_diode_swg
+ AREA = P_DJSB_G
*
RSUB2 12 40 P_RSUB2
RSUB3 31 40 P_RSUB3
RSUB1 40 4 P_RSUB1
*
* --------- Ideal mos transistor ---------------------MAIN 11 21 30 40
+ bsim_mos_transistor
+ L = 1.8E-07
+ W = 5E-6
+ AD = 0
+ AS = 0
+ PD = 0
+ PS = 0
+ M = NF
*
* -------- DIODES & PMOSFET SPICE PARAMETERS -----------*
.MODEL bsim_diode_area D
+ CJ0 = 0.00114 VJ = 0.762 M = 0.395 IS = 3E-06 N = 1
*
.MODEL bsim_diode_perim D
+ CJ0 = 1.74E-10 VJ = 0.665 M = 0.324 IS = 4.12E-11 N = 1
*
.MODEL bsim_diode_swg D
+ CJ0 = 4.2E-10 VJ = 0.665 M = 0.324 IS = 4.12E-11 N = 1
*
.model bsim_mos_transistor PMOS
+ LEVEL = 49 MOBMOD = 3 VERSION = 3.2 CAPMOD = 2
+ BINUNIT = 1 NQSMOD = 0 NOIMOD = 2 TOX = 4.2E-09
+ TOXM = 4.2E-09 XJ = 1E-07 NCH = 6.131E+17 NGATE = 1E+23
+ VTH0 = -0.4325 K1 = 0.5704 K2 = 0.006973 K3 = -2.833
+ K3B = 1.326 W0 = -1.943E-07 NLX = 2.56E-07 DVT0 = 0.4885
+ DVT1 = 0.09578 DVT2 = 0.1287 DVT0W = -0.1261 DVT1W = 2.479E+04
+ DVT2W = 0.6915 LINT = -1.041E-08 WINT = -1.525E-07 DWG = -1.151E-07
+ DWB = -1.039E-07 U0 = 90 UA = 1.49E-09 UB = 4.646E-19
+ UC = -0.09587 VSAT = 4.75E+04 A0 = 1.35 AGS = 0.3818
+ B0 = -3.088E-07 B1 = 0 KETA = 0.01044 A1 = 0
+ A2 = 1 VOFF = -0.1073 NFACTOR = 0.984 CIT = -0.001067
+ CDSC = 0.0007578 CDSCD = 0 CDSCB = 0.0001 ETA0 = 1.071
+ ETAB = -0.9291 DSUB = 1.919 PCLM = 0.553 PDIBLC1 = 0.007
+ PDIBLC2 = 0.008005 PDIBLCB = 0 DROUT = 0.157 PSCBE1 = 4.866E+08
+ PSCBE2 = 2.8E-07 PVAG = -0.888 RDSW = 202.1 PRWG = 1.2
+ PRWB = 0 WR = P_WR ALPHA0 = 0 ALPHA1 = 0
+ BETA0 = 30 CGDO = 1.254E-10 CGBO = 0 CGSO = 1.254E-10
+ XPART = 0 CF = 1.533E-10 DLC = 7.01E-08 CGSL = 2E-11
+ CGDL = 2E-11 CKAPPA = 0.6 CLC = 1E-07 CLE = 0.6
+ DWC = 2.3E-07 VFBCV = -1 NOFF = 1 VOFFCV = 0
+ ACDE = 1 MOIN = 15 NOIA = 4.6E+17 NOIB = 2.5E+03
+ NOIC = 2.6126E-11 EM = 4.1E+07 AF = 1 EF = 1.1388
+ KF = 0 LMIN = 1.8E-07 LMAX = 1.805E-07 WMIN = 5E-06

18

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Approved Date: 12 / 3 / 2003

+ WMAX = 1.05E-04 XL = -2E-09 XW = 0 JS = 3E-06

+ JSW = 4.12E-11 CJ = 0.00114 MJ = 0.395 PB = 0.762
+ CJSW = 1.74E-10 MJSW = 0.324 TNOM = 25 UTE = -0.4484
+ KT1 = -0.2194 KT1L = -8.204E-09 KT2 = -0.009487 UA1 = 4.571E-09
+ UB1 = -6.026E-18 UC1 = -0.0985 AT = 1.203E+04 PRT = 0
+ XTI = 3 WW = 1.236E-14 LW = -2.873E-16 LL = 6.635E-15
+ WL = 0 WLN = 1 WWN = 1 WWL = 0
+ LLN = 1 LWN = 1 LWL = 0 LLC = -1.31E-14
+ LWC = 0 LWLC = 0 WLC = 0 WWC = 0
+ WWLC = 0 LVTH0 = 0.0057 WVTH0 = -0.0148 LU0 = -3
+ LNFACTOR = 0.03 PVTH0 = 0.0031 LNLX = -1.584E-08 WRDSW = 10.07
+ WETA0 = 0 WETAB = 0 WPCLM = 0 WUA = 2.7E-09
+ LUA = -2.37E-10 PUA = 5.855E-11 WUB = 0 LUB = 0
+ PUB = 0 WUC = 0 LUC = 0 PUC = 0
+ WVOFF = -0.009816 LVOFF = -0.0009871 PVOFF = -9.833E-05 WA0 = -0.04807
+ LA0 = -0.281 PA0 = 0.08661 WAGS = -0.04177 LAGS = 0.04454
+ PAGS = -0.04076 WKETA = 0 LKETA = -0.012 PKETA = 0
+ WUTE = -0.2682 LUTE = 0 PUTE = 0 WVSAT = -1.42E+04
+ LVSAT = 0 PVSAT = -350 LPDIBLC2 = 0.003012 WAT = -6405
+ WPRT = 216.6 N = 1 PHP = 0.665 CTA = 0.001
+ CTP = 0.000753 PTA = 0.00155 PTP = 0.00124 ACM = 3
+ LDIF = 8E-08 RSH = 8 RD = 0 RSC = 0
+ RDC = 0 HDIF = 2.6E-07 RS = 0
.ENDS
*
# UMC_18_PMOS_1p8 RF BSIM3v3 SPICE MODEL
# Scalable with Gate Length
*
*1= Drain 2=Gate 3= Source 4=Bulk
*
.SUBCKT P_PO7W500_18_RF 1 2 3 4 L=0.5u
*
.PARAM L_um='L*1E6'
*
* #### Define Bsim3v3 Model Variable #####
*
.PARAM P_NLX='(616.3333-1840*L_um+2266.6670*(L_um*L_um))*1E-9'
.PARAM P_PCLM='2.7030-0.6375/L_um+0.1313/(L_um*L_um)'
*
* #### Define RF Extension Model Variable #####
*
.PARAM P_RG='72.7967-25.7375/L_um+2.8321/(L_um*L_um)'
.PARAM P_CD='(15.8033+4.660*L_um-8.9333*(L_um*L_um))*1E-15'
.PARAM P_CGS='(3.7967-18.190*L_um+36.7333*(L_um*L_um))*1E-15'
.PARAM P_LD=9E-11
.PARAM P_LS=9E-11
.PARAM P_DJDB_A='(4.25*((7+1)/2))*1E-12'
.PARAM P_DJDB_P='(1.7*((7+1)/2)+5)*1E-6'
.PARAM P_DJDB_G='(5*7)*1E-6'
.PARAM P_DJSB_A='(4.25*((7+1)/2))*1E-12'
.PARAM P_DJSB_P='(1.7*((7+1)/2)+5)*1E-6'
.PARAM P_DJSB_G='(5*7)*1E-6'
.PARAM P_RSUB1='157.35-17.0875/L_um+1.3563/(L_um*L_um)'
.PARAM P_RSUB2=1
.PARAM P_RSUB3=1
*
* --------- Gate network -----------------------------19

Doc. No: 04U1-02034

Rev.:2d2

Approved Date: 12 / 3 / 2003

Cgs_ext 21 30 P_CGS
Rgate 2 21 P_RG
*
* --------- Drain network ----------------------------Ldrain 1 11 P_LD
Lsource 30 3 P_LS
Cd 11 30 P_CD
*
* --------- Substrate network ------------------------* Diodes are for p-type MOS transistors
*
Djdb_area 11 12
+ bsim_diode_area
+ AREA = P_DJDB_A
Djdb_perim 11 12
+ bsim_diode_perim
+ AREA = P_DJDB_P
Djdb_swg 11 12
+ bsim_diode_swg
+ AREA = P_DJDB_G
*
Djsb_area 30 31
+ bsim_diode_area
+ AREA = P_DJSB_A
Djsb_perim 30 31
+ bsim_diode_perim
+ AREA = P_DJSB_P
Djsb_swg 30 31
+ bsim_diode_swg
+ AREA = P_DJSB_G
*
RSUB2 12 40 P_RSUB2
RSUB3 31 40 P_RSUB3
RSUB1 40 4 P_RSUB1
*
* --------- Ideal mos transistor ---------------------MAIN 11 21 30 40
+ bsim_mos_transistor
+L=L
+ W = 5u
+ AD = 0
+ AS = 0
+ PD = 0
+ PS = 0
+M=7
*
* -------- DIODES & PMOSFET SPICE PARAMETERS -----------*
.MODEL bsim_diode_area D
+ CJ0 = 0.00114 VJ = 0.762 M = 0.395 IS = 3E-06 N = 1
*
.MODEL bsim_diode_perim D
+ CJ0 = 1.74E-10 VJ = 0.665 M = 0.324 IS = 4.12E-11 N = 1
20

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Approved Date: 12 / 3 / 2003

*
.MODEL bsim_diode_swg D
+ CJ0 = 4.2E-10 VJ = 0.665 M = 0.324 IS = 4.12E-11 N = 1
*
.model bsim_mos_transistor PMOS
+ LEVEL = 49 MOBMOD = 3 VERSION = 3.2 CAPMOD = 2
+ BINUNIT = 1 NQSMOD = 0 NOIMOD = 2 TOX = 4.2E-09
+ TOXM = 4.2E-09 XJ = 1E-07 NCH = 6.131E+17 NGATE = 1E+23
+ VTH0 = -0.4325 K1 = 0.5704 K2 = 0.006973 K3 = -2.833
+ K3B = 1.326 W0 = -1.943E-07 NLX = P_NLX DVT0 = 0.4885
+ DVT1 = 0.07578 DVT2 = 0.1287 DVT0W = -0.1261 DVT1W = 2.479E+04
+ DVT2W = 0.6915 LINT = -1.041E-08 WINT = -1.525E-07 DWG = -1.151E-07
+ DWB = -1.039E-07 U0 = 113 UA = 1.54E-09 UB = 6.46E-20
+ UC = -0.09587 VSAT = 4.55E+04 A0 = 1.35 AGS = 0.3818
+ B0 = -3.088E-07 B1 = 0 KETA = 0.01044 A1 = 0
+ A2 = 1 VOFF = -0.1073 NFACTOR = 0.984 CIT = -0.001067
+ CDSC = 0.0007578 CDSCD = 0 CDSCB = 0.0001 ETA0 = 1.071
+ ETAB = -0.9291 DSUB = 1.919 PCLM = P_PCLM PDIBLC1 = 0.005
+ PDIBLC2 = 0.01401 PDIBLCB = 0 DROUT = 1.457 PSCBE1 = 4.866E+08
+ PSCBE2 = 2.8E-07 PVAG = 1.162 RDSW = 202.1 PRWG = 0
+ PRWB = 0 WR = 1 ALPHA0 = 0 ALPHA1 = 0
+ BETA0 = 30 CGDO = 1.254E-10 CGBO = 0 CGSO = 1.254E-10
+ XPART = 0 CF = 1.533E-10 DLC = 7.01E-08 CGSL = 2E-11
+ CGDL = 2E-11 CKAPPA = 0.6 CLC = 1E-07 CLE = 0.6
+ DWC = 0 VFBCV = -1 NOFF = 1 VOFFCV = 0
+ ACDE = 1 MOIN = 15 NOIA = 4.6E+17 NOIB = 2.5E+03
+ NOIC = 2.6126E-11 EM = 4.1E+07 AF = 1 EF = 1.1388
+ KF = 0 LMIN = 2E-07 LMAX = 5E-07 WMIN = 5E-06
+ WMAX = 3.5E-05 XL = -2E-09 XW = 0 JS = 3E-06
+ JSW = 4.12E-11 CJ = 0.00114 MJ = 0.395 PB = 0.762
+ CJSW = 1.74E-10 MJSW = 0.324 TNOM = 25 UTE = -0.4484
+ KT1 = -0.2194 KT1L = -8.204E-09 KT2 = -0.009487 UA1 = 4.571E-09
+ UB1 = -6.026E-18 UC1 = -0.0985 AT = 1.203E+04 PRT = 0
+ XTI = 3 WW = 1.236E-14 LW = -2.873E-16 LL = 6.635E-15
+ WL = 0 WLN = 1 WWN = 1 WWL = 0
+ LLN = 1 LWN = 1 LWL = 0 LLC = -1.31E-14
+ LWC = 0 LWLC = 0 WLC = 0 WWC = 0
+ WWLC = 0 LVTH0 = 0.0057 WVTH0 = -0.0148 LU0 = -3
+ LNFACTOR = 0.03 PVTH0 = 0.0031 LNLX = -1.584E-08 WRDSW = 10.07
+ WETA0 = 0 WETAB = 0 WPCLM = 0 WUA = 2.7E-09
+ LUA = -2.37E-10 PUA = 5.855E-11 WUB = 0 LUB = 0
+ PUB = 0 WUC = 0 LUC = 0 PUC = 0
+ WVOFF = -0.009816 LVOFF = -0.0009871 PVOFF = -9.833E-05 WA0 = -0.04807
+ LA0 = -0.281 PA0 = 0.08661 WAGS = -0.04177 LAGS = 0.04454
+ PAGS = -0.04076 WKETA = 0 LKETA = -0.012 PKETA = 0
+ WUTE = -0.2682 LUTE = 0 PUTE = 0 WVSAT = -1.42E+04
+ LVSAT = 0 PVSAT = -350 LPDIBLC2 = 0.003012 WAT = -6405
+ WPRT = 216.6 N = 1 PHP = 0.665 CTA = 0.001
+ CTP = 0.000753 PTA = 0.00155 PTP = 0.00124 ACM = 3
+ LDIF = 8E-08 RSH = 8 RD = 0 RSC = 0
+ RDC = 0 HDIF = 2.6E-07 RS = 0
.ENDS
*
21

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2.5 Model Validation:

Please refer to the attachment.

22

Approved Date: 12 / 3 / 2003

Doc. No: 04U1-02034

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Approved Date: 12 / 3 / 2003

3. N/P MOSFET 3.3V Model

3.1 Contents

UMC 0.18 m RF CMOS Process

N_L34W500_33_RF/N_PO7W500_33_RF
P_L34W500_33_RF/P_PO7W500_33_RF

3.1 Contents
3.2 Criteria of N/P MOSFET model
3.3 Model Description and Parameters
3.4 Spice parameter list
3.5 Model verification

23

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3.2 Criteria of N/P MOSFET Model

The 3.3V Model is divided into 4 sections. The first one, N_L34W500_33_RF, is valid for 3.3V
NMOS devices with scaling gate finger number from 5 to 21 at a fixed length of 0.34um and a
fixed finger width of 5um. The second one, N_PO7W500_33_RF, is valid for 3.3V NMOS devices
with scaling gate lengths from 0.34um to 0.8um at a fixed finger number of 7 and a fixed finger
width of 5um. The third section, P_L34W500_33_RF , is valid for 3.3V PMOS devices with scaling
gate finger number from 5 to 21 at a fixed length of 0.34um. The last one, P_PO7W500_33_RF, is
valid for 3.3V PMOS devices with scaling gate lengths from 0.34um to 0.8um at a fixed finger
number of 7 and a fixed finger width of 5um.
.
l

Specific N/P MOSFET operation description:

a.
b.
c.
d.
e.
f.
g.
h.
i.
j.

Effective frequency range: 100MHz ~10GHz

Effective DC voltage range: |Vg| = 0.8 ~ 3.3V |Vd| = 0V~3.3V
Effective applicable voltage range of s-parameters: |Vg| = 08~3.3V |Vd| = 0.8~3.3V
Gate length tuning range (L): 0.34 m ~ 0.8 m
Unit translated gate length (L_um): 0.34 ~ 0.8
Total gate width (Wtotal = W*NF): 25m ~ 105m
Single gate finger width (W): 5.0 m
Gate finger number range (NF): 5 ~ 21
Empirical scalable formula is used in the standard BSIM3v3.2 RF extension model.
Gate finger numbers can be even or odd. We suggest using an odd number.

Extracted parameters and simulation results:

a. Some specific parameters in this document can be calculated from the scalable formulas
by giving a specific L (gate length) or NF (finger number).
b. In this document, the MOSFET Based Band Models are released from UMC.
c. Please ignore the following simulation warning messages:
Warning: Pd=0 Ps=0 less than W.
Warning: Noff is too large.
d. Please use the RMS error function to calculate the errors between the measured and
simulated data. (See Appendix A)

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Model validation:
a. Two port data is measured by 50 impedance system.
b. One port is defined as the output port connected to ground.

c.

Simulation frequency is from 100MHz to 10GHz.

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3.3 Device Description and Model Parameters

3.3.1 Extension equivalent circuit model
The MOSFET extension equivalent circuit model is based on the BSIM3v3.2 model to extract
the desired RF model. The results of two-port S-parameters de-embedded with open pad are used
to extract the model parameters. Different geometry MOSFET devices are measured and the
results are used to verify the accuracy of the model. The schematic of the extended BSIM3v3 RF
model is showed in Fig. 3-1. Port1 is connected to poly gate and port2 is connected to drain. The
intrinsic dc, cv and noise characteristics are modeled by BSIM3v3.2. The passive parasitic
components and diode elements are described as follows:
(1) Rgate is used to model the equivalent gate resistance.
(2) Rsub1, Rsub2 & Rsub3 represent the substrate loss.
(3) Djdb_area and Djdb_perim are used to model source/drain bottom junction and
sidewall junction capacitance.
(4) Djdb_swg, and Djsb_swg are used to model source/drain sidewall junction
capacitance per unit length at gate sidewall.
(5) Cd & Cgs_ext represent the total equivalent capacitance between drain, source and
gate
(6) Disable the junction diode in standard BSIM3v3 by setting AD= AS=PD= PS= 0.
(7) Lsouce and Ldrain are used to model the parasitic inductance effect.
G

Rgate
Cgs_ext
Cd

Ldrain

Lsource

S
Djsb_perim

Djdb_perim
Djsb_swg

Djdb_swg

Djsb_area

Djdb_area
Rsub3

Rsub2
Rsub1

Fig. 3-1 RF N/P MOSFET Extension Model

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3.3.2 RF MOSFET layout:

The layout of the RF MOSFET is shown in Fig. 3-2 and PCell layout is provided in the
corresponding electronic file. It is important to remember that model parameters are strongly
dependent on the device layouts at RF band. Therefore, to get the accurate characteristics of the
demonstrated devices, the layout structures should not be modified. The MOSFET layout has
some distinguishing characteristics, described as follows:
(1) Reducing the overlap capacitance between Gate and Source.
(2) Reducing the gate resistance by putting parallel metal upon the finger gate.
(3) Double-ended gate structure is used to reduce RF noise.
(4) Grounded substrate surrounds the core device and is viewed as a part of RF device.
(5) Symmetrical S/D structure is used for the modeling purpose.

Drain

Gate

Bulk
Source
Diffusion Dummy Block

Fig.3-2 RF N/P MOSFET 3.3V layout

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3.3.3 Simulated RMS errors

Table 3-1 RMS Errors of measured and simulated S-parameters of N MOSFETs

L_um*NF*W
RMS_S11 (%)
RMS_S22 (%)
RMS_S21 (%)
RMS_S12 (%)
0.34*5*5

0.645

1.594

2.882

2.002

0.34*7*5

0.751

1.635

2.925

2.419

0.34*9*5

1.801

2.261

3.993

3.974

0.34*13*5

1.432

3.546

3.582

4.111

0.34*17*5

2.037

5.033

4.451

5.694

0.34*21*5

2.291

5.437

4.068

6.404

0.34*7*5

0.973

3.096

2.283

2.432

0.5*7*5

1.836

1.91

5.379

3.029

0.8*7*5

3.973

3.837

8.06

8.422

Table 3-2 RMS Errors of measured and simulated S-parameters of P MOSFETs

L_um*NF*W

RMS_S11(%)

RMS_S22(%)

RMS_S21(%)

RMS_S12(%)

0.34*5*5

1.799

1.311

1.35

2.284

0.34*7*5

2.392

2.131

1.209

2.307

0.34*9*5

2.895

3.700

1.578

4.33

0.34*13*5

4.086

5.824

1.844

4.067

0.34*17*5

4.973

5.885

2.306

5.500

0.34*21*5

5.655

7.909

2.922

8.053

0.34*7*5

3.002

5.031

1.466

2.227

0.5*7*5

3.539

4.884

2.548

2.785

0.8*7*5

4.962

4.478

4.723

3.916

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3.3.4 Empirical scaling formula

Scaling rule is a method for IC designers to predict device performance that has not been
measured during the modeling process. In this document, empirical scaling rule is provided and
the scaling rule is an optional choice for users. After modeling all of the devices, we use regression
analysis to obtain the relationship between the model parameters, gate length (L) and gate finger
number (NF). The scaling formulas are listed in Table 3-3 and Table 3-6. Table 3-7 shows the area
and perimeter parameters of extension S/D junction diodes.
Table 3-3 Scalable formulas for 3.3V NMOSFETs with different Finger Numbers
Parameter

Scaling formula

MOSFET

N MOSFET BSIM3v3 RF SPICE MODEL

P_RG ( )

-7.0913+216.04/NF-411.06/(NF*NF)

P_CD (F)

(0.306+0.1838*NF+0.0049*(NF*NF))*1E-15

P_RSUB1 ( )

70.9+224.53/NF-396.9/(NF*NF)

Table 3-4 Scalable formulas for 3.3V NMOSFETs with different Gate Lengths
Parameter

Scaling formula

MOSFET

N MOSFET BSIM3v3 RF SPICE MODEL

P_RG ( )

33.476-13.353/L_um+2.0572/(L_um*L_um)

P_CD (F)

(20.609-34.728*L_um+19.022*(L_um*L_um))*1E-15

Table 3-5 Scalable formulas for 3.3V PMOSFETs with different Finger Numbers
Parameter

Scaling formula

MOSFET

P MOSFET BSIM3v3 RF SPICE MODEL

P_RG ( )

2.9978+41.357/NF-36.796/(NF*NF)

P_CD (F)

(9.4819-0.5777*NF+0.0508*(NF*NF))*1E-15

P_RSUB1 ( )

20.979+437.18/NF-705.05/(NF*NF)

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Table 3-6 Scalable formulas for 3.3V PMOSFETs with different Gate Lengths
Parameter

Scaling formula

MOSFET

P MOSFET BSIM3v3 RF SPICE MODEL

P_RG ( )

192.37-151.74/L_um+30.28/(L_um*L_um)

P_CD (F)

(33.148-64.815*L_um+37.037*(L_um*L_um))*1E-15

Table 3-7 Junction Diode parameters

Parameter
P_Djdb_area

Definition
Drain bottom junction diode area

P_Djdb_perim Drain sidewall junction diode perimeter

P_Djdb_swg

Drain gate sidewall junction diode perimeter

P_Djsb_area

Source bottom junction diode area

P_Djsb_perim Source sidewall junction diode perimeter

P_Djsb_swg

Source gate sidewall junction diode perimeter

# Bottom junction diode area per source/drain region

= 0.85 m *5.0 m

# Source/Drain sidewall junction diode perimeter

Refer to the following parameter list

# Source/Drain gate sidewall junction diode perimeter

= 5.0 m * finger number

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3.4 Spice model parameter list

# UMC_18_NMOS_3p3 RF BSIM3v3 SPICE MODEL
# Scalable with Finger Number
*
*1= Drain 2=Gate 3= Source 4=Bulk
*
.SUBCKT N_L34W500_33_RF 1 2 3 4 NF=21
*
* #### define RF Extension Model Varable #####
*
.PARAM P_RG='-7.0913+216.04/NF-411.06/(NF*NF)'
.PARAM P_CD='(0.306+0.1838*NF+0.0049*(NF*NF))*1E-15'
.PARAM P_CGS=2E-15
.PARAM P_LD=1E-11
.PARAM P_LS=6E-11
.PARAM P_DJDB_A='(4.25*((NF+1)/2))*1E-12'
.PARAM P_DJDB_P='(1.7*((NF+1)/2)+5)*1E-6'
.PARAM P_DJDB_G='(5*NF)*1E-6'
.PARAM P_DJSB_A='(4.25*((NF+1)/2))*1E-12'
.PARAM P_DJSB_P='(1.7*((NF+1)/2)+5)*1E-6'
.PARAM P_DJSB_G='(5*NF)*1E-6'
.PARAM P_RSUB1='70.9+224.53/NF-396.9/(NF*NF)'
.PARAM P_RSUB2=2
.PARAM P_RSUB3=2
*
* --------- Gate network -----------------------------Cgs_ext 21 30 P_CGS
Rgate 2 21 P_RG
*
* --------- Drain network ----------------------------Ldrain 1 11 P_LD
Lsource 30 3 P_LS
Cd 11 30 P_CD
*
* --------- Substrate network ------------------------*
Djdb_area 12 11
+ bsim_diode_area
+ AREA = P_DJDB_A
Djdb_perim 12 11
+ bsim_diode_perim
+ AREA = P_DJDB_P
Djdb_swg 12 11
+ bsim_diode_swg
+ AREA = P_DJDB_G
*
Djsb_area 31 30
+ bsim_diode_area
+ AREA = P_DJSB_A
Djsb_perim 31 30
+ bsim_diode_perim

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+ AREA = P_DJSB_P
Djsb_swg 31 30
+ bsim_diode_swg
+ AREA = P_DJSB_G
*
*
Rsub2 12 40 P_RSUB2
Rsub3 31 40 P_RSUB3
Rsub1 40 4 P_RSUB1
*
* --------- Ideal mos transistor ---------------------MAIN 11 21 30 40
+ bsim_mos_transistor
+ L = 3.4E-07
+ W = 5E-06
+ AD = 0
+ AS = 0
+ PD = 0
+ PS = 0
+ M = NF
*
.MODEL bsim_diode_area D
+ CJ0 = 0.0007673 VJ = 0.7131 M = 0.3299 IS = 1E-05 N = 1
*
.MODEL bsim_diode_perim D
+ CJ0 = 1.089E-10 VJ = 0.7131 M = 0.1037 IS = 5.1E-11 N = 1
*
.MODEL bsim_diode_swg D
+ CJ0 = 2.9E-10 VJ = 0.7131 M = 0.1037 IS = 5.1E-11 N = 1
*
.model bsim_mos_transistor NMOS
+ LEVEL = 49 VERSION = 3.2 MOBMOD = 1 BINUNIT = 2
+ CAPMOD = 3 NQSMOD = 0 TOX = 7E-09 XJ = 2.5E-07
+ NCH = 1.7E+17 RSH = 8 LINT = 0 WINT = 0
+ DWG = 3.553E-15 DWB = 6.2E-09 VTH0 = 0.5924 K1 = 0.7138
+ K2 = -0.02583 K3 = 62 DVT0 = 4.75 DVT1 = 0.634
+ DVT2 = -0.1139 DVT0W = 0.15 DVT1W = 5.95E+05 DVT2W = 0
+ NLX = 1.372E-07 W0 = 5.68E-06 K3B = 32 VSAT = 1.052E+05
+ UA = -4.855E-10 UB = 2.265E-18 UC = 5.518E-11 U0 = 0.03913
+ A0 = 0.651 KETA = 0.005 A1 = 0.1 A2 = 0.99 AGS = 0.06
+ B0 = 2E-08 B1 = 9E-07 VOFF = -0.1361 NFACTOR = 1
+ CIT = 0 CDSC = 0.00024 CDSCB = 0 CDSCD = 0
+ ETA0 = 0.02 ETAB = -0.0015 DSUB = 0.201 PCLM = 1.21
+ PDIBLC1 = 0.025 PDIBLC2 = 0.002 PDIBLCB = 0 DROUT = 0.46
+ PSCBE1 = 4.04E+08 PSCBE2 = 1E-05 PVAG = 0.2 DELTA = 0.02
+ RDSW = 495.9 PRWB = 0.05715 PRWG = 0.088 WR = 1.01
+ ALPHA0 = 0 ALPHA1 = 0 BETA0 = 30 CGDO = 2.7E-10
+ CGSO = 2.7E-10 CGBO = 0 XPART = 0 CF = 1.392E-10
+ XL = 2.5E-08 XW = 0 CJ = 0.0007673 MJ = 0.3299
+ PB = 0.7131 CJSW = 1.089E-10 MJSW = 0.1037 JS = 1E-05
+ JSW = 5.1E-11 TNOM = 27 KT1 = -0.3166 KT2 = -0.04461
+ AT = 500 UTE = -1.601 UA1 = 4.203E-11 UB1 = 3.8E-19
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+ UC1 = 2.8E-11 KT1L = 0 PRT = -271.3 LLN = 1

+ LWN = 1 WLN = 1 WWN = 1 LL = 1.214E-14 LW = 0
+ LWL = -2.886E-22 WL = 0 WW = -2.01E-16 WWL = -1.502E-21
+ ACM = 3 LDIF = 0 HDIF = 3.2E-07 LNFACTOR = 1E-07
+ LU0 = 0 LVSAT = -0.0045 LUA = 0 LUB = 0 PHP = 0.4347
+ CTA = 0.001082 CTP = 0.0007482 PTA = 0.001822 PTP = 0.002009
+ ELM = 5 CJGATE = 2.9E-10 TLEVC = 1 NOFF = 50 DWC = 0
+ LMIN = 3.4E-07 LMAX = 3.405E-07 WMIN = 5E-06 WMAX = 1.05E-04
+ NOIMOD= 2 NOIA= 1.2386E+21 NOIB= 44531.5473
+ NOIC= -1.05E-14 EF= 0.9396 EM= 2063059.9427
*
* ##### End of RF NMOSFET Structure #####
*
.ENDS
*
# UMC_18_NMOS_3p3 RF BSIM3v3 SPICE MODEL
# Scalable with Gate Length
*
*1= Drain 2=Gate 3= Source 4=Bulk
*
.SUBCKT N_PO7W500_33_RF 1 2 3 4 L=0.8u
*
.PARAM L_um='L*1E6'
*
* #### define RF Extension Model Varable #####
*
.PARAM P_RG='33.476-13.353/L_um+2.0572/(L_um*L_um)'
.PARAM P_CD='(20.609-34.728*L_um+19.022*(L_um*L_um))*1E-15'
.PARAM P_CGS=2E-15
.PARAM P_LD=1E-11
.PARAM P_LS=6E-11
.PARAM P_DJDB_A='(4.25*((7+1)/2))*1E-12'
.PARAM P_DJDB_P='(1.7*((7+1)/2)+5)*1E-6'
.PARAM P_DJDB_G='(5*7)*1E-6'
.PARAM P_DJSB_A='(4.25*((7+1)/2))*1E-12'
.PARAM P_DJSB_P='(1.7*((7+1)/2)+5)*1E-6'
.PARAM P_DJSB_G='(5*7)*1E-6'
.PARAM P_RSUB1=70
.PARAM P_RSUB2=2
.PARAM P_RSUB3=2
*
* --------- Gate network -----------------------------Cgs_ext 21 30 P_CGS
Rgate 2 21 P_RG
*
* --------- Drain network ----------------------------Ldrain 1 11 P_LD
Lsource 30 3 P_LS
Cd 11 30 P_CD
*
* --------- Substrate network ------------------------*
Djdb_area 12 11

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+ bsim_diode_area
+ AREA = P_DJDB_A
Djdb_perim 12 11
+ bsim_diode_perim
+ AREA = P_DJDB_P
Djdb_swg 12 11
+ bsim_diode_swg
+ AREA = P_DJDB_G
*
Djsb_area 31 30
+ bsim_diode_area
+ AREA = P_DJSB_A
Djsb_perim 31 30
+ bsim_diode_perim
+ AREA = P_DJSB_P
Djsb_swg 31 30
+ bsim_diode_swg
+ AREA = P_DJSB_G
*
Rsub2 12 40 P_RSUB2
Rsub3 31 40 P_RSUB3
Rsub1 40 4 P_RSUB1
*
* --------- Ideal mos transistor ---------------------MAIN 11 21 30 40
+ bsim_mos_transistor
+L=L
+ W = 5u
+ AD = 0
+ AS = 0
+ PD = 0
+ PS = 0
+M=7
*
* -------- DIODES & NMOSFET SPICE PARAMETERS -----------*
.MODEL bsim_diode_area D
+ CJ0 = 0.0007673 VJ = 0.7131 M = 0.3299 IS = 1E-05 N = 1
*
.MODEL bsim_diode_perim D
+ CJ0 = 1.089E-10 VJ = 0.7131 M = 0.1037 IS = 5.1E-11 N = 1
*
.MODEL bsim_diode_swg D
+ CJ0 = 2.9E-10 VJ = 0.7131 M = 0.1037 IS = 5.1E-11 N = 1
*
.MODEL bsim_mos_transistor NMOS
+ LEVEL = 49 VERSION = 3.2 MOBMOD = 1 BINUNIT = 2
+ CAPMOD = 3 NQSMOD = 0 TOX = 7E-09 XJ = 2.5E-07
+ NCH = 1.7E+17 RSH = 8 LINT = 0 WINT = 0 DWG = 3.553E-15
+ DWB = 6.2E-09 VTH0 = 0.6124 K1 = 0.7138 K2 = -0.02583 K3 = 62
+ DVT0 = 4.75 DVT1 = 0.634 DVT2 = -0.1139 DVT0W = 0.15
+ DVT1W = 5.95E+05 DVT2W = 0 NLX = 1.372E-07 W0 = 5.68E-06
+ K3B = 32 VSAT = 1.052E+05 UA = -4.855E-10 UB = 2.065E-18
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+ UC = 5.518E-11 U0 = 0.03913 A0 = 1.042 KETA = 0.005

+ A1 = 0.1 A2 = 0.99 AGS = 0.1603 B0 = 2E-08
+ B1 = 9E-07 VOFF = -0.1361 NFACTOR = 1 CIT = 0
+ CDSC = 0.00024 CDSCB = 0 CDSCD = 0 ETA0 = 0.02
+ ETAB = -0.0015 DSUB = 0.201 PCLM = 1.01 PDIBLC1 = 0.025
+ PDIBLC2 = 0.002 PDIBLCB = 0 DROUT = 0.46 PSCBE1 = 4.04E+08
+ PSCBE2 = 1E-05 PVAG = 0 DELTA = 4.441E-19 RDSW = 495.9
+ PRWB = 0.05715 PRWG = 0.088 WR = 1.01 ALPHA0 = 0
+ ALPHA1 = 0 BETA0 = 30 CGDO = 2.7E-10 CGSO = 2.7E-10
+ CGBO = 0 XPART = 0 CF = 1.392E-10 XL = 2.5E-08
+ XW = 0 CJ = 0.0007673 MJ = 0.3299 PB = 0.7131
+ CJSW = 1.089E-10 MJSW = 0.1037 JS = 1E-05 JSW = 5.1E-11
+ TNOM = 27 KT1 = -0.3166 KT2 = -0.04461 AT = 500
+ UTE = -1.601 UA1 = 4.203E-11 UB1 = 3.8E-19 UC1 = 2.8E-11
+ KT1L = 0 PRT = -271.3 LLN = 1 LWN = 1 WLN = 1
+ WWN = 1 LL = 1.214E-14 LW = 0 LWL = -2.886E-22 WL = 0
+ WW = -2.01E-16 WWL = -1.502E-21 ACM = 3 LDIF = 0
+ HDIF = 3.2E-07 LNFACTOR = 1E-07 LU0 = 0 LVSAT = -0.0045
+ LUA = 0 LUB = 0 PHP = 0.4347 CTA = 0.001082
+ CTP = 0.0007482 PTA = 0.001822 PTP = 0.002009 ELM = 5
+ CJGATE = 2.9E-10 TLEVC = 1 NOFF = 50 DWC = 1E-07
+ LMIN = 3.4E-07 LMAX = 8E-07 WMIN = 5E-06 WMAX = 3.5E-05
+ NOIMOD= 2 NOIA= 1.2386E+21 NOIB= 44531.5473
+ NOIC= -1.05E-14 EF= 0.9396 EM= 2063059.9427
*
* ##### End of RF NMOSFET Structure #####
*
.ENDS
*
# UMC_18_PMOS_3p3 RF BSIM3v3 SPICE MODEL
# Scalable with Finger Number
*
*1= Drain 2=Gate 3= Source 4=Bulk
*
.SUBCKT P_L34W500_33_RF 1 2 3 4 NF=21
*
*
* #### define RF Extension Model Varable #####
*
.PARAM P_RG='2.9978+41.357/NF-36.796/(NF*NF)'
.PARAM P_CD='(9.4819-0.5777*NF+0.0508*(NF*NF))*1E-15'
.PARAM P_CGS=1E-15
.PARAM P_LD=1E-11
.PARAM P_LS=6E-11
.PARAM P_DJDB_A='(4.25*((NF+1)/2))*1E-12'
.PARAM P_DJDB_P='(1.7*((NF+1)/2)+5)*1E-6'
.PARAM P_DJDB_G='(5*NF)*1E-6'
.PARAM P_DJSB_A='(4.25*((NF+1)/2))*1E-12'
.PARAM P_DJSB_P='(1.7*((NF+1)/2)+5)*1E-6'
.PARAM P_DJSB_G='(5*NF)*1E-6'
.PARAM P_RSUB1='20.979+437.18/NF-705.05/(NF*NF)'
.PARAM P_RSUB2=2
.PARAM P_RSUB3=2
*
* --------- Gate network -----------------------------Cgs_ext 21 30 P_CGS

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Rgate 2 21 P_RG
*
* --------- Drain network ----------------------------Ldrain 1 11 P_LD
Lsource 30 3 P_LS
Cd 11 30 P_CD
*
* --------- Substrate network ------------------------* Diodes are for p-type MOS transistors
*
Djdb_area 11 12
+ bsim_diode_area
+ AREA = P_DJDB_A
Djdb_perim 11 12
+ bsim_diode_perim
+ AREA = P_DJDB_P
Djdb_swg 11 12
+ bsim_diode_swg
+ AREA = P_DJDB_G
*
Djsb_area 30 31
+ bsim_diode_area
+ AREA = P_DJSB_A
Djsb_perim 30 31
+ bsim_diode_perim
+ AREA = P_DJSB_P
Djsb_swg 30 31
+ bsim_diode_swg
+ AREA = P_DJSB_G
*
Rsub2 12 40 P_RSUB2
Rsub3 31 40 P_RSUB3
Rsub1 40 4 P_RSUB1
*
* --------- Ideal mos transistor ---------------------MAIN 11 21 30 40
+ bsim_mos_transistor
+ L = 3.4E-7
+ W = 5E-6
+ AD = 0
+ AS = 0
+ PD = 0
+ PS = 0
+ M = NF
*
.MODEL bsim_diode_area D
+ CJ0 = 0.0012 MJSW = 0.4097 VJ = 0.7618 IS = 9E-05 N = 1
*
.MODEL bsim_diode_perim D
+ CJ0 = 2.243E-10 VJ = 0.7618 MJSW = 0.4745 IS = 4.9E-12 N = 1
*
.MODEL bsim_diode_swg D
+ CJ0 = 4.2E-10 VJ = 0.7618 MJSW = 0.4745 IS = 4.9E-12 N = 1
*
.model bsim_mos_transistor PMOS
+ LEVEL = 49 VERSION = 3.2 MOBMOD = 1 CAPMOD = 3
+ NQSMOD = 0 TOX = 7E-09 XJ = 1.8E-07 NCH = 4.31E+17
+ RSH = 8 LINT = 2.24E-08 WINT = 3.361E-08 DWG = -1.437E-08
+ DWB = 5.984E-09 VTH0 = -0.7104 K1 = 0.7667 K2 = 0.05429
+ K3 = 2.089 DVT0 = 7.395 DVT1 = 0.6635 DVT2 = 0.007805
+ DVT0W = 1.797 DVT1W = 2.876E+06 DVT2W = 0.1026 NLX = 5E-08
+ W0 = 2.125E-07 K3B = 1.003 VSAT = 9.09E+04 UA = -8E-13

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+ UB = 1.82E-18 UC = -3.65E-11 U0 = 0.008064 A0 = 0.8

+ KETA = -0.01035 A1 = 0.01 A2 = 0.99 AGS = 0.3138
+ B0 = 0 B1 = 1E-06 VOFF = -0.1239 NFACTOR = 0.4964
+ CIT = 0.0005334 CDSC = 0.003166 CDSCB = 0.002463 CDSCD = 0
+ ETA0 = 0.2 ETAB = -0.01893 DSUB = 0.9052 PCLM = 0.8
+ PDIBLC1 = 0.03524 PDIBLC2 = 0.02018 PDIBLCB = 0.1478 DROUT = 0.5
+ PSCBE1 = 4.643E+08 PSCBE2 = 1.07E-05 PVAG = 0 DELTA = 0.02
+ RDSW = 467 PRWB = 0 PRWG = 0 WR = 1.1
+ ALPHA0 = 0 BETA0 = 30 CGDO = 2.6E-10 CGSO = 2.6E-10
+ CGBO = 0 XPART = 0 CF = 1.392E-10 XL = -2E-08
+ XW = 0 CJ = 0.0012 MJ = 0.4097 PB = 0.7618 CJSW = 2.243E-10
+ MJSW = 0.4745 JS = 9E-05 JSW = 4.9E-12 TNOM = 27
+ KT1 = -0.3346 KT2 = -0.05747 AT = 4.95E+04 UTE = -1.128
+ UA1 = 1.402E-09 UB1 = -3.417E-18 UC1 = -1.393E-10 KT1L = 1E-08
+ PRT = 0 LLN = 1 LWN = 1 WLN = 1 WWN = 1
+ LL = 0 LW = 0 LWL = 0 WL = 0
+ WW = 0 WWL = 0 LMIN = 3.4E-07 LMAX = 3.405E-07
+ WMIN = 5E-06 WMAX = 1.05E-04 LUA = 0 LUB = 0
+ WUA = 0 LPCLM = 0 LVTH0 = 0 PHP = 0.9297
+ CTA = 0.0009969 CTP = 0.0007119 PTA = 0.001504 PTP = 0.001216
+ ELM = 10 TLEVC = 1 ACM = 3 HDIF = 3.2E-07
+ LU0 = 0.0004 WVSAT = 0 LVSAT = 0 WU0 = 0.001
+ VOFFCV = 0 DWC = 1E-07 NOFF = 20
+ NOIMOD = 2 NOIA= 4.8632E+19 NOIB= 142700
+ NOIC= 1.04E-11 EF= 1.117 EM= 5015000
.ENDS
*
*
# UMC_18_PMOS_3p3 RF BSIM3v3 SPICE MODEL
# Scalable with Gate Length
*
*1= Drain 2=Gate 3= Source 4=Bulk
*
.SUBCKT P_PO7W500_33_RF 1 2 3 4 L=0.8u
*
*
.PARAM L_um='L*1E6'
*
* #### define RF Extension Model Varable #####
*
.PARAM P_RG='192.37-151.74/L_um+30.28/(L_um*L_um)'
.PARAM P_CD='(33.148-64.815*L_um+37.037*(L_um*L_um))*1E-15'
.PARAM P_CGS=1E-15
.PARAM P_LD=1E-11
.PARAM P_LS=6E-11
.PARAM P_DJDB_A='(4.25*((7+1)/2))*1E-12'
.PARAM P_DJDB_P='(1.7*((7+1)/2)+5)*1E-6'
.PARAM P_DJDB_G='(5*7)*1E-6'
.PARAM P_DJSB_A='(4.25*((7+1)/2))*1E-12'
.PARAM P_DJSB_P='(1.7*((7+1)/2)+5)*1E-6'
.PARAM P_DJSB_G='(5*7)*1E-6'
.PARAM P_RSUB1=70
.PARAM P_RSUB2=2
.PARAM P_RSUB3=2
*
* --------- Gate network -----------------------------Cgs_ext 21 30 P_CGS
Rgate 2 21 P_RG
*
* --------- Drain network ----------------------------Ldrain 1 11 P_LD
Lsource 30 3 P_LS
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Cd 11 30 P_CD
*
* --------- Substrate network ------------------------* Diodes are for p-type MOS transistors
*
Djdb_area 11 12
+ bsim_diode_area
+ AREA = P_DJDB_A
Djdb_perim 11 12
+ bsim_diode_perim
+ AREA = P_DJDB_P
Djdb_swg 11 12
+ bsim_diode_swg
+ AREA = P_DJDB_G
*
Djsb_area 30 31
+ bsim_diode_area
+ AREA = P_DJSB_A
Djsb_perim 30 31
+ bsim_diode_perim
+ AREA = P_DJSB_P
Djsb_swg 30 31
+ bsim_diode_swg
+ AREA = P_DJSB_G
*
Rsub2 12 40 P_RSUB2
Rsub3 31 40 P_RSUB3
Rsub1 40 4 P_RSUB1
*
* --------- Ideal mos transistor ---------------------MAIN 11 21 30 40
+ bsim_mos_transistor
+L=L
+ W = 5u
+ AD = 0
+ AS = 0
+ PD = 0
+ PS = 0
+M=7
*
* -------- DIODES & PMOSFET SPICE PARAMETERS -----------*
.MODEL bsim_diode_area D
+ CJ0 = 0.0012 MJSW = 0.4097 VJ = 0.7618 IS = 9E-05 N = 1
*
.MODEL bsim_diode_perim D
+ CJ0 = 2.243E-10 VJ = 0.7618 MJSW = 0.4745 IS = 4.9E-12 N = 1
*
.MODEL bsim_diode_swg D
+ CJ0 = 4.2E-10 VJ = 0.7618 MJSW = 0.4745 IS = 4.9E-12 N = 1
*
.model bsim_mos_transistor PMOS
+ LEVEL = 49 VERSION = 3.2 MOBMOD = 1 CAPMOD = 3 NQSMOD = 0
+ TOX = 7E-09 XJ = 1.8E-07 NCH = 4.31E+17 RSH = 8
+ LINT = 2.24E-08 WINT = 3.361E-08 DWG = -1.437E-08 DWB = 5.984E-09
+ VTH0 = -0.7104 K1 = 0.7667 K2 = 0.05429 K3 = 2.089
+ DVT0 = 7.395 DVT1 = 0.6635 DVT2 = 0.007805 DVT0W = 1.797
+ DVT1W = 2.876E+06 DVT2W = 0.1026 NLX = 5E-08 W0 = 2.125E-07
+ K3B = 1.003 VSAT = 1.209E+05 UA = -8E-13 UB = 1.82E-18
+ UC = -3.65E-11 U0 = 0.008064 A0 = 1.2 KETA = -0.01035
+ A1 = 0.01 A2 = 0.99 AGS = 0.3138 B0 = 0
+ B1 = 1E-06 VOFF = -0.1239 NFACTOR = 0.4964 CIT = 0.0005334

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+ CDSC = 0.003166 CDSCB = 0.002463 CDSCD = 0 ETA0 = 0.2

+ ETAB = -0.01893 DSUB = 0.9052 PCLM = 0.8 PDIBLC1 = 0.03524
+ PDIBLC2 = 0.02018 PDIBLCB = 0.1478 DROUT = 0.5 PSCBE1 = 4.643E+08
+ PSCBE2 = 1.07E-05 PVAG = 0 DELTA = 0.02 RDSW = 467
+ PRWB = 0 PRWG = 0 WR = 1.1 ALPHA0 = 0
+ BETA0 = 30 CGDO = 2.6E-10 CGSO = 2.6E-10 CGBO = 0
+ XPART = 0 CF = 1.392E-10 XL = -2E-08 XW = 0
+ CJ = 0.0012 MJ = 0.4097 PB = 0.7618 CJSW = 2.243E-10
+ MJSW = 0.4745 JS = 9E-05 JSW = 4.9E-12 TNOM = 27
+ KT1 = -0.3346 KT2 = -0.05747 AT = 4.95E+04 UTE = -1.128
+ UA1 = 1.402E-09 UB1 = -3.417E-18 UC1 = -1.393E-10 KT1L = 1E-08
+ PRT = 0 LLN = 1 LWN = 1 WLN = 1 WWN = 1
+ LL = 0 LW = 0 LWL = 0 WL = 0 WW = 0
+ WWL = 0 LMIN = 3.4E-07 LMAX = 8E-07 WMIN = 5E-06
+ WMAX = 3.5E-05 LUA = 0 LUB = 0 WUA = 0 LPCLM = 0
+ LVTH0 = 0 PHP = 0.9297 CTA = 0.0009969 CTP = 0.0007119
+ PTA = 0.001504 PTP = 0.001216 ELM = 10 TLEVC = 1
+ ACM = 3 HDIF = 3.2E-07 LU0 = 0.0004 WVSAT = 0
+ WU0 = 0.001 VOFFCV = 0 DWC = 1E-07 NOFF = 20
+ NOIMOD = 2 NOIA= 4.8632E+19 NOIB= 142700
+ NOIC= 1.04E-11 EF= 1.117 EM= 5015000
*
* ##### End of RF PMOSFET Structure #####
*
.ENDS
*
*

3.5 Model Validation:

Please refer to the attachment.

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4. Circular Spiral Inductor Model

4.1 Contents

UMC 0.18m RF CMOS Process

L_SLCR20K_RF

4.1 Contents
4.2 Criteria of Inductor Model
4.3 Model Description and Parameters
4.4 SPICE parameter list
4.5 Model verification

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4.2 Criteria of Inductor Model

l

Specific Inductor operation description:

a. Empirical scalable formula is used to model the spiral inductor with different
geometries.
b. Operating frequency range: 100MHz ~ 10GHz .
The proper usage range should be below its corresponding self-resonance
frequency(Fsr). Please check Table 4-1 for detail.
c. Effective inductance range: 1nH ~ 12.0 nH at the frequency below 300MHz.
**Notice: Choose imaginary part of Z_One_port method to calculate the inductance
value.
** Z_One_Port is defined as the Z-parameter of one port structure
d. Geometry variables: W (top metal width), D (inner diameter) and N (turn number).
e. The range of spiral top metal width (W) : 6m ~ 20m.
f. The range of spiral inner diameter (D) : 126m ~ 238m.
g. The range of spiral turn number (N) : 1.5 ~ 5.5 (N is limited by 1.5, 2.5, 3.5 4.5, 5.5).
h. The range of spiral metal spacing (S) : fixed at 2m.
i. The top metal thickness is 20KA.
j. Unit translated spiral top metal width (W_um): W*1e6
k. Unit translated spiral inner diameter (D_um): (D/2)*1e6
l. Unit translated spiral metal spacing (S_um): 2
m. Unit translated spiral top metal thickness (T_um): 2
n. The using range in (e, f, g) must be limited by the real geometry listed in Table 4-1.
o. Parameter units: W(Meter), D(Meter), S(Meter), Rs(), Ls(H), Cp(F), Cox(F), Csub(F),
Rsub().
p. The Inductors have been modeled as three port component.
The node number of the third port in the model card is 999.
l Specific inductor structure description:
a. Port1 (top spiral metal, M6) is defined as the input port, and Port2 (underpass line, M5)
acts as the output port. (see Fig. 4-2).
b. Inductor substrate is connected to ground around the border with 30 m spacing.
c. Q is defined as (imaginary part / real part) of Z_One_port input impedance.

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4.3 Model Description and Parameters

4.3.1 Lump element equivalent circuit model
The lump element equivalent circuit model is used to model the spiral inductors based on
two-port S-parameter measurement. The results of two-port S-parameters de-embedded with
open pad are used to extract the model parameters. The equivalent circuit model of the spiral
inductor is shown in Fig. 4-1, where port1 is connected to spiral top metal M6 and port2 is defined
as underpass M5. The intrinsic inductor is represented by Ls. Rs is the series resistance of the
spiral metal and Cp models the fringing capacitance between metal strips and the overlap
capacitance between the spiral metal and underpass line. Cox1 and Cox2 represent the
capacitance between metal layer and grounded substrate. Rsub1, Rsub2, Csub1 and Csub2
describe the associated substrate loss while the inductor is operated at RF band.
C

2
R

L
Cox

Cox

Csub

Rsub

999

Csub

Rsub

999

999

999

Fig. 4-1 Inductor Equivalent Circuit Model.

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4.3.2 Inductor layout

Diffusion Dummy

D+W+S

M5
Port2

M6
Port1

S
GND

N=3.5

Fig. 4-2 Typical spiral circular inductor layout (N = 3.5)

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4.3.3 Measured and Simulation characteristics of specific inductors

Table 4-1 Measured characteristics and geometry parameters of circular spiral inductors
Device

(um) (um)

Inductance(nH)

Measurement

Quality Factor

(um) 2.4GHz 5.0GHz Qmax f@Qmax 2.4GHz 5.0GHz

Fsr
(GHz)

IND_C1

20

238

1.5

1.294

1.326

10.798

6.5

7.686

10.646

>20

IND_C2

20

136

2.5

1.737

1.826

10.010

4.9

8.093

9.969

16.5

IND_C3

18

136

2.5

1.738

1.816

10.140

4.9

7.941

10.126

17.3

IND_C4

18

168

2.5

2.147

2.307

9.879

3.9

8.488

9.664

14.7

IND_C5

15

195

2.5

2.540

2.768

9.644

3.9

8.432

9.243

13.8

IND_C6

15

126

3.5

3.058

3.416

8.854

3.3

8.369

7.895

12.5

IND_C7

13

141

3.5

3.413

3.832

8.708

3.9

8.129

7.952

12.3

IND_C8

10

163

3.5

4.245

4.896

8.365

3.2

7.874

7.398

11.4

IND_C9

10

180

3.5

4.503

5.298

8.226

3.1

7.927

6.809

10.8

IND_C10

194

3.5

4.986

5.873

8.256

3.3

7.856

7.045

10.8

IND_C11

131

3.5

3.214

3.438

9.364

4.5

7.730

9.354

15.3

IND_C12

138

4.5

5.543

6.589

7.962

3.0

7.723

6.566

10.6

IND_C13

144

4.5

5.815

7.019

7.917

3.0

7.787

6.275

10.2

IND_C14

160

4.5

6.556

8.290

7.909

2.5

7.893

5.496

9.3

IND_C15

164

4.5

6.833

8.440

7.600

3.0

7.395

5.979

9.8

IND_C16

177

4.5

7.488

9.579

7.465

2.7

7.412

5.359

9.2

IND_C17

128

5.5

7.725

9.756

7.600

2.6

7.554

4.015

9.4

IND_C18

144

5.5

8.856

11.886

7.411

2.4

7.411

4.499

8.5

IND_C19

159

5.5

9.989

14.337

7.180

2.3

7.177

3.660

7.7

IND_C20

180

5.5

11.711

18.585

6.961

2.0

6.770

2.606

6.9

IND_C21

210

5.5

14.479

25.501

6.594

1.8

6.087

1.380

5.9

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Table 4-2 Simulation characteristics and geometry parameters of circular spiral inductors
Device

(um) (um)

Inductance(nH)

Simulation

Quality Factor

(um) 2.4GHz 5.0GHz Qmax f@Qmax 2.4GHz 5.0GHz

Fsr
(GHz)

IND_C1

20

238

1.5

1.230

1.288

11.461

6.5

6.970

11.087

>20

IND_C2

20

136

2.5

1.720

1.860

10.288

4.5

8.268

10.132

15.8

IND_C3

18

136

2.5

1.694

1.814

10.307

4.8

7.914

10.264

17

IND_C4

18

168

2.5

2.159

2.379

10.025

3.9

8.772

9.422

14.3

IND_C5

15

195

2.5

2.563

2.846

9.764

3.7

8.715

8.995

13.8

IND_C6

15

126

3.5

3.145

3.610

9.393

2.9

9.177

7.359

12

IND_C7

13

141

3.5

3.489

4.013

9.184

2.9

8.967

7.172

12

IND_C8

10

163

3.5

4.073

4.693

8.832

3.1

8.489

7.131

12

IND_C9

10

180

3.5

4.600

5.462

8.650

2.8

8.518

6.377

10.9

IND_C10

194

3.5

5.068

6.005

8.347

3.1

8.023

6.608

11

IND_C11

131

3.5

3.114

3.371

9.212

4.5

7.335

9.050

16.1

IND_C12

138

4.5

5.646

6.793

8.263

2.6

8.215

5.642

10.5

IND_C13

144

4.5

5.937

7.253

8.193

2.5

8.177

5.337

10.1

IND_C14

160

4.5

6.743

8.618

8.014

2.3

8.005

4.565

9.2

IND_C15

164

4.5

6.913

8.522

7.715

2.8

7.554

5.555

10

IND_C16

177

4.5

7.618

9.738

7.539

2.7

7.481

4.959

9.3

IND_C17

128

5.5

7.890

10.014

7.633

2.4

7.633

4.546

9.4

IND_C18

144

5.5

9.084

12.254

7.423

2.2

7.388

3.732

8.4

IND_C19

159

5.5

10.279

14.814

7.232

2.1

7.088

3.035

7.7

IND_C20

180

5.5

12.089

19.351

6.983

1.9

6.596

2.156

6.8

IND_C21

210

5.5

14.993

27.144

6.658

1.6

5.831

1.061

5.9

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4.3.4 Simulated RMS errors

Table 4-3 RMS errors of measured and simulated s-parameters of circular spiral inductors
Device

RMS_S11(%)

RMS_S12(%)

RMS_S21(%)

RMS_S22(%)

IND_C1

7.614

1.652

1.753

8.03

IND_C2

8.1

2.635

2.615

8.3

IND_C3

7.141

1.61

1.61

7.328

IND_C4

6.49

2.705

2.688

6.79

IND_C5

4.73

1.75

1.78

4.96

IND_C6

5.81

4.25

4.23

6.3

IND_C7

4.46

3.16

3.15

4.75

IND_C8

3.095

1.802

1.742

3.186

IND_C9

3.46

2.53

2.47

3.39

IND_C10

1.8

2.08

1.75

IND_C11

2.368

1.124

1.107

2.36

IND_C12

1.937

1.916

1.842

2.088

IND_C13

1.82

2.14

2.07

1.93

IND_C14

1.609

2.86

2.79

1.745

IND_C15

1.245

2.895

2.831

1.155

IND_C16

1.164

3.566

3.509

1.11

IND_C17

1.075

2.89

2.83

1.3

IND_C18

1.593

4.314

4.264

1.455

IND_C19

1.377

5.58

5.54

1.218

IND_C20

1.037

7.43

7.396

1.028

IND_C21

1.37

8.16

8.27

0.902

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4.3.5 Scalable formula list

Table 4-4 Scalable formulas of spiral inductor scaling with D, N, W
Parameter

Scaling formula

L_spiral 0.5*(N*3.14159*(2*(2*D_um+W_um)+(2*N-1)*(W_um+S_um)))+(N+0.5)*(W_um+S_um)
d_plus

(W_um+S_um)*(3*N-2*(N-0.5)-1)*(N+0.5)/(3*(2*N-N-0.5))

p_lsef

log(2*L_spiral/(W_um+T_um))-0.2

p_M_neg 0.4418*N
p_M_d1 log(sqrt(1+(L_spiral/(4*N*d_plus))*(L_spiral/(4*N*d_plus)))+L_spiral/(4*N*d_plus))
p_M_d2 sqrt(1+(4*N*d_plus/L_spiral)*(4*N*d_plus/L_spiral))-4*N*d_plus/L_spiral
p_ls

(2*L_spiral*(p_lsef-p_M_neg+0.97*(N-1)*(p_M_d1-p_M_d2))+2923-3700*n+507*n*n)*1e-

p_rs

1+0.02*(L_spiral/W_um)+N*(0.34-0.0002273*L_spiral)

p_cp

(0.0402*(N-0.5)*W_um*W_um)*1e-15

p_cox

(0.0019725*(2*L_spiral*W_um+3.14159*W_um*W_um))*1e-15

p_csub1 ((0.24+0.098*N)*D_um)*1e-15
p_csub2 ((0.2205+0.055*N)*D_um)*1e-15
p_rsub1 530+49153/(D_um*N)
p_rsub2 680+55465/(D_um*N)'

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4.4 SPICE Model List

.SUBCKT L_SLCR20K_RF 1 2 999 D=148u N=5.5 W=6u
.PARAM D_um='(D/2)*1e6'
.PARAM W_um='W*1e6'
.PARAM S_um='2'
.PARAM T_um='2'
.PARAM
L_spiral='0.5*(N*3.14159*(2*(2*D_um+W_um)+(2*N-1)*(W_um+S_um)))+(N+0.5)*(W_um+S_um
)'
.PARAM d_plus='(W_um+S_um)*(3*N-2*(N-0.5)-1)*(N+0.5)/(3*(2*N-N-0.5))'
.PARAM p_lsef='log(2*L_spiral/(W_um+T_um))-0.2'
.PARAM p_M_neg='0.4418*N'
.PARAM
p_M_d1='log(sqrt(1+(L_spiral/(4*N*d_plus))*(L_spiral/(4*N*d_plus)))+L_spiral/(4*N*d_plus))'
.PARAM p_M_d2='sqrt(1+(4*N*d_plus/L_spiral)*(4*N*d_plus/L_spiral))-4*N*d_plus/L_spiral'
.PARAM
p_ls='(2*L_spiral*(p_lsef-p_M_neg+0.97*(N-1)*(p_M_d1-p_M_d2))+2923-3700*n+507*n*n)*1e-13'
.PARAM p_rs='1+0.02*(L_spiral/W_um)+N*(0.34-0.0002273*L_spiral)'
.PARAM p_cp='(0.0402*(N-0.5)*W_um*W_um)*1e-15'
.PARAM p_cox='(0.0019725*(2*L_spiral*W_um+3.14159*W_um*W_um))*1e-15'
.PARAM p_csub1='((0.24+0.098*N)*D_um)*1e-15'
.PARAM p_csub2='((0.2205+0.055*N)*D_um)*1e-15'
.PARAM p_rsub1='530+49153/(D_um*N)'
.PARAM p_rsub2='680+55465/(D_um*N)'
*
* --------- Equivalent network ------------------Rs 1 777 p_rs
Ls 2 777 p_ls
Cp 1 2 p_Cp
Cox1 1 771 p_Cox
Cox2 2 881 p_Cox
Rsub1 771 999 p_rsub1
Rsub2 881 999 p_rsub2
Csub1 771 999 p_csub1
Csub2 881 999 p_csub2
.ends

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4.4 Model verification plot

Please refer to the attachment

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5. MIS Varactor Model

5.1 Contents

UMC 0.18 m RF CMOS Process

VARMIS_RF

5.1 Contents
5.2 Criteria of MIS Varactor Model
5.3 Model Description and Parameters
5.4 SPICE parameter list
5.5 Model verification

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5.2 Criteria of MIS Varactor Model

l

Specific MIS varactor operation description:

a. The C-V formula of standard BSIM3v3 model is used to extract the characteristics of the
N+/NWell MIS varactor.
b. Two large resistors are added to terminate S/D behavior of BSIM 3v3 standard model.
c. Gate and bulk bias can be applied separately to get the accurate two port characteristics
of the varactor.
d. Gate finger length is fixed at 1.0 m, gate finger width is fixed at 5.0 m
e. Finger number (NF): 24 ~ 120
f. Effective bias range: VB = 0V, Vg = 1.8 V ~ -1.8V
g. Effective bias range: VG = 0V, Vb = 0 V ~ 1.8V
** Notice: The recommended bias range is VG-VB = -1V ~ 1V
h. Frequency range: 100MHz ~10GHz
i. The MIS varactors have been modeled as three port component.
The node number of the third port in the model card is 999.

Model validation:
a. Two port data is measured by 50 impedance system.
b. One port is defined as the output port connected to ground.
c. Simulation frequency is from 100MHz to 10GHz

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5.3 Model Description and Parameters

5.3.1 Extension equivalent circuit model
The C-V model equation of the standard BSIM3v3 model is used to model the RF MIS
varactor in this document. The results of two-port S-parameters measurement with open pad are
used to extract the model parameters. The schematic of extended MIS varactor model is showed in
Fig. 5-1 where port1 (Gate) is poly gate and port2 (Bulk) is N-Well. Fig. 5-2 shows the cross section
of MIS varactor and Fig 5-3 shows the typical layout. The descriptions of the MIS varactor model
parameters are as follows:
(1)Lg and Rg model the equivalent poly gate inductance and resistance.
(2)Lb and Rb model the equivalent serial inductance and resistance.
(3)Rdiso and Rsiso are resistors used to terminate Drain port and Source port effects in
BSIM3v3 standard model.
(4)Cbox, Rsub and Csub represent the varactors substrate loss at RF band.
(5)Disable the junction diode in standard BSIM3v3 by setting AD = AS =PD = PS = 0
(6)D_n_sub models the diode characteristics of N-Well/Psub.
999

Rdiso
Lg

Rg

Rb

Lb
Bulk

Gate
Cbox
Rsiso

D_n_su
Rsu
Csu

999

999

999

999

Fig. 5-1 MIS Varactor Equivalent Circuit Model

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5.3.2 MIS varactor cross section and layout:

Gate
Bulk
N+

N+

N+

N+

N-Well

Fig. 5-2 Cross section of MIS varactor

SUB
Well

Gate

Well

Fig. 5-3 MIS varactor layout

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5.3.3 Simulated RMS errors

Table 5-1 RMS Errors of measured and simulated S-parameters of MIS varactor
Device

RMS_S11 (%)

RMS_S21 (%)

RMS_S22 (%)

RMS_S12(%)

MIS_24

2.154

2.716

2.856

1.499

MIS_48

2.574

2.567

2.688

1.551

MIS_72

4.156

2.01

2.222

2.946

MIS_96

3.969

1.847

1.926

2.343

MIS_120

4.436

3.027

3.118

1.907

5.3.4 Scalable formula list

Table 5-2 MIS Varactor scaling with nf
Parameter

Scaling formula

p_l

(10.25+0.3854*nf)*1e-12

p_r

(0.9850+0.0038*nf)

p_cp

(-5.8082+0.4911*nf)*1e-15

p_cbox

(19.9+3.9733*nf)*1e-15

p_csub

(-56.4685+57.8069*log(nf))*1e-15

p_rsub

(150.7322-27.8594*log(nf))

p_sub_area ((10.14+(nf-1)*1.84)*17.94)*1e-12'
p_sub_pj 2*((10.14+(nf-1)*1.84)+17.94)*1e-6

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5.4: SPICE Model List

.subckt VARMIS_18_RF 1 2 999 nf=24
.param dt='temper-25'
.param p_l='(10.25+0.3854*nf)*1e-12'
.param p_r='(0.9850+0.0038*nf)'
.param p_cp='(-5.8082+0.4911*nf)*1e-15'
.param p_cbox='(19.9+3.9733*nf)*1e-15'
.param p_csub='(-56.4685+57.8069*log(nf))*1e-15'
.param p_rsub='(150.7322-27.8594*log(nf))'
.param p_sub_area='((10.14+(nf-1)*1.84)*17.94)*1e-12'
.param p_sub_pj='2*((10.14+(nf-1)*1.84)+17.94)*1e-6'
lgate 1 11 p_l
rgate 11 111 p_r
cp 11 999 p_cp
lbulk 2 22 p_l
rbulk 22 222 p_r
cbox 22 333 p_cbox
rsub 333 999 p_rsub
csub 333 999 p_csub
rd 3 999 1e+09
rs 4 999 1e+09
main 3 111 4 222 mosmode l=1u w=5u m=nf
d2 999 22 d_sub
*************************************************
* PMOS model
************************************************
.model mosmode pmos
+ level=49
version=3.2
capMod=3
+ tox=4.17e-09
xj=1.5e-07
a0=1.35
+ ags=0.3818
b0=-3.088e-07
b1=1.4e-08
+ keta=0.1044
voff=-0.08
vth0=-0.4075
+ nch=6.5e+16
nlx=5.717e-06
k1=0.8563
+ k2=-0.02497
k3=80
dvt0=2.2
+ dvt1=0.53
dvt2=-0.032
dsub=0.56
+ eta0=0.08
etab=-0.07
u0=0.025
+ ua=2.25e-09
ub=5.87e-19
uc=-4.65e-11

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+ vsat=80000
+ pclm=1.3
+ pdiblcb=0
+ drout=0.56
+ beta0=30
+ cgso=0
+ cf=1.00394e-10
+ toxm=4.17e-09
+ kt2=0
+ ub1=-6.026e-18
+ xw = 7e-9
*
.model d_sub d
+ level = 3
+ is = 4.204e-06
+ rs = 9.223e-06
+ bv = 14.38
+ tlev = 1
+ trs = 0.00249
+ pb = 0.75
+ php = 0.75
.ends

Approved Date: 12 / 3 / 2003

delta=0.01
pdiblc1=0.39
pscbe1=4.24e+08
nfactor=1
clc=1e-07
cgdo=0
acde='1.165-0.0016*dt'
kt1=0.085
ute=-0.4484
uc1=-0.0985
dwc=2.1e-7

wr=1
pdiblc2=0.0086
pscbe2=1e-05
cdsc=0.00024
cle=0.6
ckappa=0.6
moin=15
kt1l=0
ua1=4.57e-09
xl = 2.3e-9

area = 'p_sub_area'
jsw = 3.231e-12
ik = 400
ibv = 1e-3
eg = 1.17
cj = 0.000107
cjsw = 2.4e-11

pj = 'p_sub_pj'
n = 1.02
ikr = 3.4e+04
tlevc = 1
xti = 3
mj= 0.458
mjsw = 0.384

5.4: Model verification plot

Please refer to the attachment

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6.P+ / N-Well Varactor Model

6.1 Contents

UMC 0.18 m RF CMOS Process

VARDIOP_RF

6.1 Contents
6.2 Criteria of P+ / N-Well varactor
6.3 Model Description and Parameters
6.4 SPICE parameter list
6.5 Model verification

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6.2 Criteria of P+ / N-Well Varactor Model

l

Specific P+ / N-Well varactor operation description:

a. The standard diode model is used to predict P+ / N-Well varactor characteristics.
b. The extra components are added to the diode model to describe the well loss at RF band.
c. PN junction area: lf=2um, wf=5um /per finger.
Please refer to Fig 6.1 for detail definition.
d. Recommend bias range: -3V~0.1V
e. Number of PN junctions: 30 < nf <120

Model validation:
a. Two port data is measured by 50 impedance system.
b. One port is defined as the output port connected to ground.
c. Simulation frequency is from 100MHz to 10GHz

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6.3 Model Description and Parameters:

6.3.1 Extension equivalent circuit model
The standard diode model is used to model the finger-type P+/N-Well junction varactor. The
results of two-port S-parameters de-embedded with open pad are used to extract the model
parameters. The equivalent extension model for P+/N-Well varactor is shown in Fig. 6-1(a). Port1
is connected to P+ poly and port2 is connected to N-Well. L1 & L2 are used to precisely model the
effective capacitance of P+/N-Well varactor. Cox, Csub, and Rsub represent the well loss at RF
band.

P+

L1

Diode

L2

C2
D_n_sub
Rsub

Csub

(a)

PLUS

MINUS
(b)

Fig. 6-1 P+/N-Well varactor Extension equivalent circuit (a) and Layout (b)

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6.3.2 Simulated RMS errors

Table 6-1 RMS errors of measured and simulated s-parameters of P+ /N-Well varactors

nf

RMS_S11(%)

RMS_S21(%)

RMS_S22(%)

RMS_S12(%)

30

2.823

2.925

2.892

2.095

45

3.867

2.775

2.747

2.154

60

1.792

2.685

2.655

1.371

90

1.516

2.23

2.213

1.275

120

1.623

2.956

3.031

1.504

6.3.3 Scalable formula list

Table 6-2 Scalable formulas of P+/NWell Varactors scaling with nf

Parameter
p_nf_30

Scaling formula
nf/30

p_L1

(15.2*p_nf_30)*1e-12

p_L2

1.31e-11

p_C2

(86.62*p_nf_30)*1e-15

p_CSUB

(12.19*2*p_nf_30)*1e-15

p_RSUB

143.3/p_nf_30

p_DIODE_AREA nf*(2*5)*1e-12
p_DIODE_PJ

nf*(2*(2+5))*1e-6

p_SUB_AREA ((39.94*int(nf/15)+(nf-(int(nf/15)*15)*1.5)*1.5+1.94)*8.88)*1e-12
p_SUB_PJ

2*((39.94*int(nf/15)+(nf-(int(nf/15)*15)*1.5)*1.5+1.94)+8.88)*1e-6

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6.4 SPICE Model List

.subckt VARDIOP_RF 1 2 nf=60
.param p_nf_30='nf/30'
.PARAM p_L1='(15.2*p_nf_30)*1e-12'
.PARAM p_L2='1.31e-11'
.PARAM p_C2='(86.62*p_nf_30)*1e-15'
.PARAM p_CSUB='(12.19*2*p_nf_30)*1e-15'
.PARAM p_RSUB='143.3/p_nf_30'
.PARAM p_DIODE_AREA='nf*(2*5)*1e-12'
.PARAM p_DIODE_PJ='nf*(2*(2+5))*1e-6'
.PARAM p_SUB_AREA='((39.94*int(nf/15)+(nf-(int(nf/15)*15)*1.5)*1.5+1.94)*8.88)*1e-12'
.PARAM p_SUB_PJ='2*((39.94*int(nf/15)+(nf-(int(nf/15)*15)*1.5)*1.5+1.94)+8.88)*1e-6'
l1 1 11 p_L1
l2 2 22 p_L2
c2 22 223 p_C2
csub 223 0 p_CSUB
rsub 223 0 p_RSUB
d1 11 22 diode
.model diode d
+ level = 3
area = 'p_DIODE_AREA'
pj = 'p_DIODE_PJ'
+ is = 1.12e-7
xti = 3
tlevc = 1
+ jsw = 5e-15
bv = 11.75
ibv = 125
+ rs = 9.355e-10
cjo = 1.136e-3
pb = 0.6599
+ mj = 0.3307
cjsw = 1.56E-10
php = 0.665
+ mjsw = 0.324
fc = 0.5
eg = 1.165
+ cta = 7.3e-4
tpb = 1.2e-4
tm1 = 0.001
+n=1
ik = 3.383e+7
d2 0 22 d_sub
.model d_sub d
+ level = 3
area = 'p_ SUB_AREA '
pj = 'p_ SUB_PJ'
+ is = 4.204e-06
jsw = 3.231e-12
n = 1.02
+ rs = 9.223e-06
ik = 400
ikr = 3.4e+04
+ bv = 14.38
ibv = 1e-3
tlevc = 1
+ tlev = 1
eg = 1.17
xti = 3
+ trs = 0.00249
cj = 0.000107
mj= 0.458
+ pb = 0.75
cjsw = 2.4e-11
mjsw = 0.384
+ php = 0.75
.ends
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6.5 Model verification plot

Please refer to the attachment

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7. MIM Capacitor Model (with grounded M1 shield)

7.1 Contents

UMC 0.18 m RF CMOS Process

MIMCAPM_RF

7.1 Contents
7.2 Criteria of MIM Capacitor model
7.3 Model Description and Parameters
7.4 Spice parameter list
7.5 Model Validation

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7.2 Criteria of MIM Capacitor Model (with grounded M1 shield)

l

Specific MIM operation description:

a. The scalable formula is used to calculate the model parameters of single-rectangle (SR)
type & multi-rectangle (MR) type MIM capacitors.
b. Operating frequency range: 100MHz ~10GHz
c. Variable parameters:
l (Length of MMC)
w (Width of MMC)
nx (Number of multi-rectangle MMC in x axis)
ny (Number of multi-rectangle MMC in y axis)
d. The range of SR Capacitor: 10um <= l, w <= 70um
The range of MR Capacitor: 1 <= nx, ny <= 7
** Please follow the ratio limitation: 1<= (l*ny)/(w*nx)<=6
e. All parameters are used in MKS unit
f. The minimum size of MIM Capacitor is 10um*10um
g. While evaluating the MIM capacitor, you can combine the SR & MR capacitor to obtain
the desired value of capacitance.
h. Parameter units: l (Meter), rs(), ls (H), cs (F), cox1 (F)
i. The MIM devices have been modeled as three port component.
The node number of the third port in the model card is 999.

Extracted parameters and simulation results:

a. All of the MIM capacitor parameters in this document are extracted from the scalable
formulas by giving specific length (l), width (w) and numbers (nx, ny) of MIM capacitors.
b. Use the RMS error function to calculate the errors between the measured and simulated
data. (See Appendix)

Model validation:
a. Two port data is measured by 50 impedance system.
b. One port is defined as the output port connected to ground.
c. Simulation frequency is from 100MHz to 10GHz

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7.3 Model Description and Parameters:

7.3.1 Lump element equivalent circuit model
The lump element equivalent circuit model is used to model the single rectangle-type and
multi-rectangle type of Metal-Insulator-Metal (MIM) capacitors. Fig. 7-1 shows the equivalent
circuit of the MIM capacitor model. The results of two-port S-parameters de-embedded with open
pad are used to extract the model parameters. The cross section and layout of the MIM capacitor
model are shown in Fig. 7-2. Port1 is connected to top metal of MMC and Port2 is connected to
bottom metal (M5).
The intrinsic MIM capacitor is represented by Cs. Ls and Rs are the parasitic inductor and
resistor resulted from the electrodes. There should be a parasitic capacitor, here denoted by Cox,
which exists between the bottom metal and the field oxide.

Cs

Rs

Ls

Cox1

Cox2

999

Fig. 7-1 MIM capacitor equivalent circuit model

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7.3.2 MIM Capacitor cross-section and layout:

PORT1 (M6)

PORT2 (M6)

MMC
VIA5

Fig. 7-2 MIM Capacitor cross section

Metal 1 (GND)

nx=3

MMC

l
ny=3

w
MMC

Metal 6

Diffusion Dummy
Fig. 7-3 MIM Capacitor layout MR (left) & SR (right)

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7.3.3 Simulated RMS errors

Table 7-1 RMS errors of measured and simulated of Multi-Rectangle MIM capacitors
Device

RMS_S11
(%)

RMS_S12
(%)

RMS_21
(%)

RMS_S22
(%)

A10X10X1

111.8m

451.5m

404.1m

169.9m

A10X10X4

531.0m

658.9m

994.4m

A10X10X9

1.25

613.7m

679.1m

917.5m

A10X10X16

1.731

513.4m

560.3m

1.135

A10X10X25

2.111

475.7m

521.3m

1.300

A10X10X36

2.441

447.4m

491.6m

1.441

A10X10X49

2.290

388.1m

424.3m

1.469

558.7m

Table 7-2 RMS errors of S-parameters Single-Rectangle MIM capacitors

Device

RMS_S11
(%)

RMS_S12
(%)

RMS_21
(%)

RMS_S22
(%)

A10X10X1

111.8m

451.5m

404.1m

169.9m

A10X20X1

745.2m

536.9m

475.6m

1.125

A10X40X1

634.2m

329.8m

393.9m

1.391

A10X80X1

613.3m

253.3m

333.2m

1.192

A20X20X1

539.3m

353.6m

352.4m

928m

A20X40X1

643.0m

355.1m

428.0m

703.8m

A30X30X1

676.8m

351.7m

421.5m

646.8m

A40X40X1

1.103

336.9m

396.2m

623.2m

A50X50X1

1.317

321.3m

369.4m

758.4m

A60X60X1

1.625

330.8m

371.7m

984.7m

A70X70X1

1.858

362.8m

396.2m

1.295

A80X40X1

1.311

301.5m

350.8m

743.8m

A80X80X1

2.050

373.3m

419.5m

1.359

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7.3.4 Scalable formula

All parameters in the formulas are consistent with EDRs value. For process variation issue,
we need to add some fixing ratios in capacitance per square um during modeling extraction period.
However, the scaling formulas, which are listed in Table 7-3, are centered to EDRs value without
consideration of process variation.

Table 7-3 MIM capacitor scaling formulas

Formula
Cs

n*(l*w*0.001+1.5e-10*(l+w))*(1+3e-5*dt+1e-8*dt*dt)*(1.0027-0.0002*v+3e-5*v^2)

Rs

2.0667e-2*leb/wb

Ls

1e-7*leb/F*(0.0074*(leb/wb)+0.2399+0.7363/(leb/wb))

Cox1/Cox2
Remark

(leb*wb*cox+3.382e-11*(leb+wb))/2
dt=temp-25
n=nx*ny
leb=ny*(l+1.7e-6)+4.3e-6
wb=nx*(w+1.7e-6)+4.3e-6
F=1/(log(2*(1+sqrt(k1))/(1-sqrt(k1))))'
k1=sqrt(1-k*k)
k=wb/(wb+2*(1-4-wb/2-3.25e-5))

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7.4 Spice parameter list

# MIM CAPACITOR (MR/SR)
*
.SUBCKT MIMCAPM_RF 1 2 999 nx=1 ny=1 l=20e-6 w=20e-6
**********************************************
.PARAM dt='temper-25'
.PARAM leb='ny*(l+1.7e-6)+4.3e-6'
.PARAM wb='nx*(w+1.7e-6)+4.3e-6'
.PARAM cn='0.001'
.PARAM cox='5.4478e-6'
.PARAM n='nx*ny'
.PARAM cs='n*(l*w*cn+1.5e-10*(l+w))*(1+3e-5*dt+1e-8*dt*dt)'
.PARAM cox1='(leb*wb*cox+3.382e-11*(leb+wb))/2'
.PARAM cox2= 'cox1'
.PARAM rs='2.0667e-2*leb/wb'
.PARAM k='wb/(wb+2*(1e-4-wb/2-3.25e-5))'
.PARAM k1='sqrt(1-k*k)'
.PARAM F='1/(log(2*(1+sqrt(k1))/(1-sqrt(k1))))'
.PARAM ls='1e-7*leb/F*(0.0074*(leb/wb)+0.2399+0.7363/(leb/wb))'

* --------- Equivalent network ------------------*

C 1 11 cs*(1.0027-0.0002*v(2,1)+3e-5*v(2,1) *v(2,1))
L 11 12 ls
R 12 2 rs
C1 11 999 cox1
C2 2 999 cox2
*
.ENDS

7.5 Model Validation

Please refer to the attachment.

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8. N+/P+ Non-salicided Poly Resistor Model

8.1 Contents

UMC 0.18 m RF CMOS Process

RNNPO_RF
RNPPO_RF

8.1Contents
8.2 Criteria of N+/P+ non-salicided Resistor model
8.3 Model Description and Parameters
8.4 Spice parameter list
8.5 Model Validation

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8.2 Criteria of Resistor Model

l

Specific Resistor operation description:

a. The scalable formula is used to calculate the model parameters of the N+/P+ non-salicided
poly resistors.
b. Operating frequency range: 100MHz ~10GHz
c. Variable parameters:
l: Length of non-salicided poly resistor
w: Width of non-salicided poly resistor
d. N+/P+ non-salicided Poly strip width (w) should be larger than 2um.
e. The ratio of strip length to width should be less than 10.
f. Parameters units: l (Meter), w (Meter), rs( ), cox(F), rsub (), csub(F)
g. The N+/P+ non-salicided poly resistors have been modeled as three port component.
The node number of the third port in the model card is 999.

Extracted parameters and simulation results:

a. All of the resistor parameters in this document can be calculated from the scalable
formulas by giving specific poly strip length and width.
b. The RMS error function (See Appendix) is used to calculate the error values between the
measured and simulated data.
c. The one port data is used to analyze the characteristics of resistors because the values of
S21 & S12 are very small.
d. Z_One_Port is defined as the Z-parameter of one port structure for N+/P+
non-salicided poly resistor.

Model validation:
a. Two port data is measured by 50 impedance system.
b. One port is defined as the output port connected to ground.
c. Simulation frequency is from 100MHz to 10GHz

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8.3 Model Description and Parameters:

8.3.1 Lump element equivalent circuit model
The lump element equivalent circuit model is used to model the N+/P+ non-salicided poly
resistor based on two-port S-parameter measurement. The results of two-port S-parameters
de-embedded with open pad are used to extract the model parameters. The schematic of the N+/P+
non-salicided poly resistor model is shown in Fig. 8-1. Fig. 8-2 shows a typical layout of the N+/P+
non-salicided poly resistor. The resistance of the N+/P+ non-salicided poly resistor is represented by
Rs. The field oxide capacitor was divided into two parts, Cox1 and Cox2, for each side. The
substrate loss was modeled by using an RC network approximation at RF band.

Rs
2

Cox1

Csub1

Cox2

Csub2

Rsub1

999

Rsub2

999

Fig. 8-1 Equivalent circuit of N+/P+ non-salicided poly resistor

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(GND for N+
VDD for P+)

Metal 6

Fig. 8-2 Typical layout of N+/P+ non-salicided poly resistor

8.3.2 Simulated RMS errors

Table 8-1 RMS errors of measured and simulated impedance of N+_resistors
WxL_N

RMS of

S_11 (%)

RMS of mag(Z_One_Port) (%)

2x20_10

103.3m

1.378

5x5_1

269.3m

706.9m

5x20_4

132.6m

576.7m

5x40_8

210.0m

1.251

5x50_10

290.0m

2.289

10x100_10

118.3m

3.049

Table 8-2 RMS errors of measured and simulated impedance of P+_resistors

WxL_N

RMS of

S_11 (%)

RMS of mag(Z_One_Port) (%)

2x20_10

75.85m

4.291

5x5_1

244.3m

1.137

5x20_4

99.41m

2.091

5x40_8

116.5m

2.265

5x50_10

89.32m

2.667

10x100_10

707.8m

4.661

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8.3.3

Approved Date: 12 / 3 / 2003

Scalable formula:

In this document, a scaling rule is provided to describe the behaviors of the devices. For
process variation issues, the resistance we measured for modeling extraction is slightly
different from EDR. Therefore some parameters in the formulas are centered according to
EDRs value.
Table 8_3

N+ non-salicided poly resistor scaling formulas

Parameter
Rs
Cox1/ Cox2

Formula
(2*17e-6/wi+113*l/wi)*(1+tc1*dt+tc2*dt*dt)*(1.0-3.76e-9*v/l-8.474e-14*(v/l)^2)
((8.854e-12*Eeff*l/F)+(8e-16+8e-10*wi-1.8e-5*wi*wi))/2

Rsub1/Rsub2

2/(5*(5e-6+wi/2)*1.66e-3*F1)

Csub1/Csub2

2.944e-12/Rsub1

Remark

wi= w+dw ;dw=-0.097e-6 ; x= 4e-7/wi ;tc1= -1.6e-4 ; tc2=4.18e-7

Ep= 2.5+1.5/(sqrt(1+10*x)
F= 2/(1/x+2.42-0.44*x+pow(1-x,6))
Z0= 120*3.14159*F/sqrt(Ep)
fc= 1.9895e12*Z0*(sqrt(1/Ep))
Eeff= 4-(4-Ep)/(1+3e9/(fc*fc))
dgg=1e-5+2*wi ;dsg= 5e-6+wi ;rgg= l/dgg ;rsg= l/dsg
Ps=2*(wi+2e-7) ; Pg= 2*(wi+1.48e-6)
Ls= 2e-7*l*(log(4*l/Ps)+0.5)
Lg= 2e-7*l*(log(4*l/Pg)+0.5)
Mgg=2e-7*l*(log(rgg+sqrt(1+rgg^2))-sqrt(1+1*pow(rgg,-2)+1*pow(rgg,-1)))
Msg=2e-7*l*(log(rsg+sqrt(1+rsg*rsg))-sqrt(1+1*pow(rsg,-2)+1*pow(rsg,-1)))
Lsg=(Lg+Mgg)/2+Ls-2*Msg
F1=2.26e-6/Lsg

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Table 8-4

P+ non-salicided poly resistor scaling formulas

Parameter
Rs
Cox1/ Cox2

Formula
(2*105e-6/wi+352*l/wi)*(1+tc1*dt+tc2*dt*dt)*(1.0-1.06e-8*v/l-1.05e-13*(v/l)^2)
((8.854e-12*Eeff*l/F)+(2e-15+4e-10*wi-2e-5*wi*wi))/2

Rsub1/Rsub2

2/(5*(5e-6+wi/2)*1.66e-3*F1)

Csub1/Csub2

2.944e-12/Rsub

Remark

Approved Date: 12 / 3 / 2003

wi= w+dw ;dw=-0.046e-6 ; x= 4e-7/wi ;tc1=-2.84e-4 ;tc2=3e-7

Ep= 2.5+1.5/(sqrt(1+10*x)
F= 2/(1/x+2.42-0.44*x+pow(1-x,6))
Z0= 120*3.14159*F/sqrt(Ep)
fc= 1.9895e12*Z0*(sqrt(1/Ep))
Eeff= 4-(4-Ep)/(1+3e9/(fc*fc))
dgg=1e-5+2*wi ;dsg= 5e-6+wi ;rgg= l/dgg ;rsg= l/dsg
Ps=2*(wi+2e-7) ; Pg= 2*(wi+1.48e-6)
Ls= 2e-7*l*(log(4*l/Ps)+0.5)
Lg= 2e-7*l*(log(4*l/Pg)+0.5)
Mgg=2e-7*l*(log(rgg+sqrt(1+rgg^2))-sqrt(1+1*pow(rgg,-2)+1*pow(rgg,-1)))
Msg=2e-7*l*(log(rsg+sqrt(1+rsg*rsg))-sqrt(1+1*pow(rsg,-2)+1*pow(rsg,-1)))
Lsg=(Lg+Mgg)/2+Ls-2*Msg
F1=1.05e-6/Lsg

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8.4 Spice model parameter list

# UMC_18_RES_NPP_RF RESISTOR
*
.SUBCKT RNNPO_RF 1 2 999 l=100e-6 w=10e-6
*
.PARAM dw='-0.097e-6'
.PARAM wi='w+dw'
.PARAM dt='temper-25'
.PARAM tc1='-1.6e-4'
.PARAM tc2='4.18e-7'
.PARAM Rs='(2*17e-6/wi+113*l/wi)*(1+tc1*dt+tc2*dt*dt)'
.PARAM x='4e-7/wi'
.PARAM Ep='2.5+1.5/(sqrt(1+10*x))'
.PARAM F='2/(1/x+2.42-0.44*x+pow(1-x,6))'
.PARAM Z0='120*3.14159*F/sqrt(Ep)'
.PARAM fc='1.9895e12*Z0*(sqrt(1/Ep))'
.PARAM Eeff='4-(4-Ep)/(1+3e9/(fc*fc))'
.PARAM Cox='(8.854e-12*Eeff*l/F)+(8e-16+8e-10*wi-1.8e-5*wi*wi)'
.PARAM Cox1='Cox/2'
.PARAM Cox2='Cox1'
.PARAM dgg='1e-5+2*wi'
.PARAM dsg='5e-6+wi'
.PARAM rgg='l/dgg'
.PARAM rsg='l/dsg'
.PARAM Ps='2*(wi+2e-7)'
.PARAM Pg='2*(wi+1.48e-6)'
.PARAM Ls='2e-7*l*(log(4*l/Ps)+0.5) '
.PARAM Lg='2e-7*l*(log(4*l/Pg)+0.5)'
.PARAM Mgg='2e-7*l*(log(rgg+sqrt(1+rgg*rgg))-sqrt(1+1*pow(rgg,-2)+1*pow(rgg,-1)))'
.PARAM Msg='2e-7*l*(log(rsg+sqrt(1+rsg*rsg))-sqrt(1+1*pow(rsg,-2)+1*pow(rsg,-1)))'
.PARAM Lsg='(Lg+Mgg)/2+Ls-2*Msg'
.PARAM F1='2.26e-6/Lsg'
.PARAM Rsub='1/(5*(5e-6+wi/2)*1.66e-3*F1)'
.PARAM Rsub1='Rsub*2'
.PARAM Rsub2='Rsub1'

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.PARAM Csub='2.944e-12/Rsub'
.PARAM Csub1='Csub/2'
.PARAM Csub2='Csub1'
* --------- Equivalent network ------------------*
Rs 1 2 'Rs*(1.0-0.00376e-6*abs(v(1,2)/l)-0.08474e-12*abs(v(1,2)/l)*abs(v(1,2)/l))'
Cox1 1 11 Cox1
Cox2 2 22 Cox2
Rsub1 11 999 Rsub1
Csub1 11 999 Csub1
Rsub2 22 999 Rsub2
Csub2 22 999 Csub2
*
.ENDS
*

# UMC_18_RES_PPP_RF RESISTOR
*
.SUBCKT RNPPO_RF 1 2 999 l=20e-6 w=20e-6
*
.PARAM dw='-0.046e-6'
.PARAM wi='w+dw'
.PARAM dt='temper-25'
.PARAM tc1='-2.84e-4'
.PARAM tc2='3e-7'
.PARAM Rs='(2*105e-6/wi+352*l/wi)*(1+tc1*dt+tc2*dt*dt)'
.PARAM x='4e-7/wi'
.PARAM Ep='2.5+1.5/(sqrt(1+10*x))'
.PARAM F='2/(1/x+2.42-0.44*x+pow(1-x,6))'
.PARAM Z0='120*3.14159*F/sqrt(Ep)'
.PARAM fc='1.9895e12*Z0*(sqrt(1/Ep))'
.PARAM Eeff='4-(4-Ep)/(1+3e9/(fc*fc))'
.PARAM Cox='(8.854e-12*Eeff*l/F)+(2e-15+4e-10*wi-2e-5*wi*wi)'
.PARAM Cox1='Cox/2'
.PARAM Cox2='Cox1'
.PARAM dgg='1e-5+2*wi'
.PARAM dsg='5e-6+wi'

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.PARAM rgg='l/dgg'
.PARAM rsg='l/dsg'
.PARAM Ps='2*(wi+2e-7)'
.PARAM Pg='2*(wi+1.48e-6)'
.PARAM Ls='2e-7*l*(log(4*l/Ps)+0.5) '
.PARAM Lg='2e-7*l*(log(4*l/Pg)+0.5)'
.PARAM Mgg='2e-7*l*(log(rgg+sqrt(1+rgg*rgg))-sqrt(1+1*pow(rgg,-2)+1*pow(rgg,-1)))'
.PARAM Msg='2e-7*l*(log(rsg+sqrt(1+rsg*rsg))-sqrt(1+1*pow(rsg,-2)+1*pow(rsg,-1)))'
.PARAM Lsg='(Lg+Mgg)/2+Ls-2*Msg'
.PARAM F1='1.05e-6/Lsg'
.PARAM Rsub='1/(5*(5e-6+wi/2)*1.66e-3*F1)'
.PARAM Rsub1='Rsub*2'
.PARAM Rsub2='Rsub1'
.PARAM Csub='2.944e-12/Rsub'
.PARAM Csub1='Csub/2'
.PARAM Csub2='Csub1'
* --------- Equivalent network ------------------*
Rs 1 2 'Rs*(1.0-0.0106e-6*abs(v(1,2)/l)-0.105e-12*abs(v(1,2)/l)*abs(v(1,2)/l))'
Cox1 1 11 Cox1
Cox2 2 22 Cox2
Rsub1 11 999 Rsub1
Csub1 11 999 Csub1
Rsub2 22 999 Rsub2
Csub2 22 999 Csub2
*
.ENDS
*

8.5 Model Validation

Please refer to the attachment.

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9. HR Non-salicided Poly Resistor Model

9.1 Contents

UMC 0.18 m RF CMOS Process

RNHR_RF

9.1 Contents
9.2 Criteria of HR non-salicided poly resistor model
9.3 Model Description and Parameters
9.4 Spice parameter list
9.5 Model Validation

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9.2 Criteria of HR Non-Salicided Poly Resistor Model

l

Specific HR non-salicide Poly Resistor operation description:

a. The scalable formula is used to calculate the model parameters
of the HR non-salicided poly resistors.
b. Operating frequency range: 100MHz ~10GHz
c. Variable parameters:
l : Length of non-salicided poly resistor
w: Width of non-salicided poly resistor
d. HR Poly strip width (w) should be larger than 2um.
e. The ratio of strip length to width should be less than 10.
f. Parameters units: l (Meter), w (Meter), rs(), cox(F), rsub (), csub(F)
g. The HR non-salicided poly resistors have been modeled as three port components.
The node number of the third port in the model card is 999.
Extracted parameters and simulation results:
a. All of the resistor parameters in this document can be calculated from the scalable
formulas by giving specific poly strip length and width.
b. The RMS error function (See Appendix) is used to calculate the error values between the
measured and simulated data.
c. The one port data is used to analyze the characteristics of resistors because the values of
S21 & S12 are very small.
d. Z_One_Port is defined as the Z-parameter of one port structure for HR non-salicided
poly resistor.

Model validation:
a. Two port data is measured by 50 impedance system.
b. One port is defined as the output port connected to ground.
c. Simulation frequency is from 100MHz to 10GHz

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9.3 Model Description and Parameters:

The lump element equivalent circuit model is used to model the HR non-salicided poly
resistor based on two-port S-parameter measurement. The results of two-port S-parameters
de-embedded with open pad are used to extract the model parameters. The schematic of the HR
non-salicided poly resistor model is shown in Fig. 9-1. Fig. 9-2 shows a typical layout of the HR
non-salicided poly resistor. The resistance of the HR non-salicided poly resistor is represented by
Rs. The field oxide capacitor was divided into two parts, Cox1 and Cox2, for each side. The
substrate loss was modeled by using an RC network at RF band.

9.3.1 Lump element equivalent circuit model

Rs
2

Cox1

Csub1

Cox2

Csub2

Rsub1

999

Rsub2

999

Fig. 9-1 Equivalent circuit of HR non-salicided poly resistor

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(VDD)

Metal 6

HR Poly

Fig. 9-2 Typical layout of HR non-salicided poly resistor

9.3.2 Simulated RMS errors

Table 9-1 RMS errors of measured and simulated impedance of HR_resistor
w x l_n

RMS of

S_11 (%)

RMS of mag(Z_One_Port) (%)

2x20_10

72.58m

4.021

5x5_1

47.04m

699.2m

5x20_4

37.82m

2.116

5x40_8

93.76m

3.302

5x50_10

102.7m

4.548

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9.3.3

Approved Date: 12 / 3 / 2003

Scalable formula:

In this document, a scaling rule is provided to describe the behaviors of the devices. For
process variation issues, the resistance we measured for modeling extraction is slightly different
from EDR. Therefore some parameters in the formulas are centered according to EDRs value.

Table 9-2 HR non-salicided poly resistor scaling formulas

Parameter
Rs
Cox1/ Cox2

Formula
(2*120e-6/wi+1039*(l-0.4e-6)/wi)*(1+tc1*dt+tc2*dt*dt)*(1.0-3.5e-8*v/(l-0.4e-6)
-1.5e-13*(v/(l-0.4e-6))^2)
((8.854e-12*Eeff*l/F)+(-4e-17+1.8e-9*wi-1.4e-4*wi*wi))/2

Rsub1/Rsub2

2/(5*(5e-6+wi/2)*1.66e-3*F1)

Csub1/Csub2

2.944e-12/Rsub1

Remark

wi= w+dw ;dw=-0.043e-6 ; x= 4e-7/wi ;tc1=-8.34e-4 ;tc2=1.3e-6

Ep= 2.5+1.5/(sqrt(1+10*x)
F= 2/(1/x+2.42-0.44*x+pow(1-x,6))
Z0= 120*3.14159*F/sqrt(Ep)
fc= 1.9895e12*Z0*(sqrt(1/Ep))
Eeff= 4-(4-Ep)/(1+3e9/(fc*fc))
dgg=1e-5+2*wi ;dsg= 5e-6+wi ;rgg= l/dgg ;rsg= l/dsg
Ps=2*(wi+2e-7) ; Pg= 2*(wi+1.48e-6)
Ls= 2e-7*l*(log(4*l/Ps)+0.5)
Lg= 2e-7*l*(log(4*l/Pg)+0.5)
Mgg=2e-7*l*(log(rgg+sqrt(1+rgg^2))-sqrt(1+1*pow(rgg,-2)+1*pow(rgg,-1)))
Msg=2e-7*l*(log(rsg+sqrt(1+rsg*rsg))-sqrt(1+1*pow(rsg,-2)+1*pow(rsg,-1)))
Lsg=(Lg+Mgg)/2+Ls-2*Msg
F1='6.283e-7/Lsg

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9.4 Spice model parameter list

# UMC_18_RES_HR_RF RESISTOR
*
.SUBCKT RNHR_RF 1 2 999 l=20e-6 w=20e-6
*
.PARAM dw='-0.043e-6'
.PARAM wi='w+dw'
.PARAM dt='temper-25'
.PARAM tc1='-8.34e-4'
.PARAM tc2='1.3e-6'
.PARAM Rs='(2*120e-6/wi+1039*(l-0.4e-6)/wi)*(1+tc1*dt+tc2*dt*dt)'
.PARAM x='4e-7/wi'
.PARAM Ep='2.5+1.5/(sqrt(1+10*x))'
.PARAM F='2/(1/x+2.42-0.44*x+pow(1-x,6))'
.PARAM Z0='120*3.14159*F/sqrt(Ep)'
.PARAM fc='1.9895e12*Z0*(sqrt(1/Ep))'
.PARAM Eeff='4-(4-Ep)/(1+3e9/(fc*fc))'
.PARAM Cox='(8.854e-12*Eeff*l/F)+(-4e-17+1.8e-9*wi-1.4e-4*wi*wi)'
.PARAM Cox1='Cox/2'
.PARAM Cox2='Cox1'
.PARAM dgg='1e-5+2*wi'
.PARAM dsg='5e-6+wi'
.PARAM rgg='l/dgg'
.PARAM rsg='l/dsg'
.PARAM Ps='2*(wi+2e-7)'
.PARAM Pg='2*(wi+1.48e-6)'
.PARAM Ls='2e-7*l*(log(4*l/Ps)+0.5) '
.PARAM Lg='2e-7*l*(log(4*l/Pg)+0.5)'
.PARAM Mgg='2e-7*l*(log(rgg+sqrt(1+rgg*rgg))-sqrt(1+1*pow(rgg,-2)+1*pow(rgg,-1)))'
.PARAM Msg='2e-7*l*(log(rsg+sqrt(1+rsg*rsg))-sqrt(1+1*pow(rsg,-2)+1*pow(rsg,-1)))'
.PARAM Lsg='(Lg+Mgg)/2+Ls-2*Msg'
.PARAM F1='6.283e-7/Lsg'
.PARAM Rsub='1/(5*(5e-6+wi/2)*1.66e-3*F1)'
.PARAM Rsub1='Rsub*2'
.PARAM Rsub2='Rsub1'

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.PARAM Csub='2.944e-12/Rsub'
.PARAM Csub1='Csub/2'
.PARAM Csub2='Csub1'
* --------- Equivalent network ------------------*
Rs 1 2 'Rs*(1.0-3.5e-8*abs(v(1,2)/(l-0.4e-6))-1.5e-13*abs(v(1,2)/(l-0.4e-6))*abs(v(1,2)/(l-0.4e-6)))'
Cox1 1 11 Cox1
Cox2 2 22 Cox2
Rsub1 11 999 Rsub1
Csub1 11 999 Csub1
Rsub2 22 999 Rsub2
Csub2 22 999 Csub2
*
.ENDS
*

9.5 Model Validation

Please refer to the attachment.

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10. Shielding Pad Model

10.1 Contents

UMC 0.18 m RF CMOS Process

PAD_RF

10.1 Contents
10.2 Model Description and Parameters
10.3 Spice parameter list
10.4 Model Validation

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10.2 Model Description and Parameters:

10.2.1 Lump element equivalent circuit model
The lump element equivalent circuit model is used to model the shielding pad based on
one-port S-parameter measurement. The results of one-port S-parameter are used to extract the
model parameters. The equivalent circuit of shielding pad model is shown in Fig. 10-1. As an
example, Fig. 10-2 shows the layout of the shielding Pad. The capacitor between top metal (M6)
and shielding ground pad is represented by C. R represents the shielding ground pad loss at RF
band. Fig.10-3 shows the one port s-parameter (S_one port) of the simulated and measured
results.
1
C

999
Fig. 10-1 Equivalent circuit of shielding pad
Fig. 11-1 Equivalent circuit of shielding pad

65um

Metal 1 (GND)
Metal 6

Fig. 10-2 Typical layout of shielding pad

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Simulated RMS errors

Table 10-1 Parameters of Shielding Pad

index Real_S_11 (%) Imag_S_11 (%)

Description

128.6m

762.2m

Series by M6, M5, M4, M3, M2 (M1 GND)

49.78m

491.8m

Series by M6, M5, M4, M3

(M1 GND)

34.95m

2.016

Series by M6, M5, M4

(M1 GND)

58.97m

1.523

Series by M6, M5

(M1 GND)

88.55m

2.297

Series by M6

(M1 GND)

Table 10-2 Shielding Pad scaling formulas

Parameters
C (F)
R ()
Remark

Formula
(411.65-380.75*N+153.76*N^2-28.306*N^3+1.9421*N^4)*1e-15
65e-6*0.372*6.6711e-9/C
N=6-index

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10.3 Spice model parameter list

# UMC_18_PAD_SH_RF
*
.SUBCKT PAD_RF 1 999 index=1
*** index set from 1,2 3,4,5 ***
*******
Parameter cal
********
.PARAM indexa='6-index'
.PARAM P_C1='(411.65-380.75*indexa+153.76*indexa^2-28.306*indexa^3+
1.9421*indexa^4)*1e-15'
.PARAM P_R1='65e-6*0.372*6.6711e-9/P_C1'
*index set from 1,2 3,4,5
* --------- Equivalent network ------------------*
C 1 11 P_C1
R 11 999 P_R1
*
.ENDS
*

10.4 Model Validation

Please refer to the attachment .

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Appendix:
A: RMS Error Definition:
The errors between the simulation and measurement are calculated and used to illustrate
the accuracy of the model. The RMS error is defined as following:

2
2
[(
sim

meas
)
/
N
]
/

i
i
meas i / N
i =1

i =1
N

RMS error =

Where:
simi = the ith simulated data point,
measi = the ith measurement data point, and
N = the total number of data point.
The RMS error definition is used to describe the accuracy of RF model. The frequency range
is from 100MHz to 10GHz.

B: S Parameter Measurement Condition:

1. Source Power: 0db
2. Signal Attenuation: 20db
3. Frequency Range: 300MHz, 10.1GHz, 200MHz
4. Measured Average Factor: 256

C: Device Layout Note:

The layouts of devices in this document are just for reference. The real dimension and
structure of device layout are shown in the PCell layout file which will be provided by
UMC.

90