Multiplexer/Demultiplexer • Triple 2-Channel Analog Multiplexer/Demultiplexer

CD4051BC • CD4052BC • CD4053BC Single 8-Channel Analog Multiplexer/Demultiplexer • Dual 4-Channel Analog
November 1983
Revised April 2002

CD4051BC • CD4052BC • CD4053BC

Single 8-Channel Analog Multiplexer/Demultiplexer •
Dual 4-Channel Analog Multiplexer/Demultiplexer •
Triple 2-Channel Analog Multiplexer/Demultiplexer
General Description Features
The CD4051BC, CD4052BC, and CD4053BC analog mul- ■ Wide range of digital and analog signal levels:
tiplexers/demultiplexers are digitally controlled analog digital 3 – 15V, analog to 15Vp-p
switches having low “ON” impedance and very low “OFF” ■ Low “ON” resistance: 80Ω (typ.) over entire 15Vp-p
leakage currents. Control of analog signals up to 15Vp-p
signal-input range for VDD − VEE = 15V
can be achieved by digital signal amplitudes of 3−15V. For
example, if VDD = 5V, VSS = 0V and VEE = −5V, analog sig- ■ High “OFF” resistance:
nals from −5V to +5V can be controlled by digital inputs of channel leakage of ±10 pA (typ.) at VDD − VEE = 10V
0−5V. The multiplexer circuits dissipate extremely low qui- ■ Logic level conversion for digital addressing signals of
escent power over the full VDD−VSS and VDD−VEE supply 3 – 15V (VDD − VSS = 3 – 15V) to switch analog signals
voltage ranges, independent of the logic state of the control to 15 Vp-p (VDD − VEE = 15V)
signals. When a logical “1” is present at the inhibit input ter- ■ Matched switch characteristics:
minal all channels are “OFF”. ∆RON = 5Ω (typ.) for VDD − VEE = 15V
CD4051BC is a single 8-channel multiplexer having three
■ Very low quiescent power dissipation under all
binary control inputs. A, B, and C, and an inhibit input. The
digital-control input and supply conditions:
three binary signals select 1 of 8 channels to be turned
1 µ W (typ.) at VDD − VSS = VDD − VEE = 10V
“ON” and connect the input to the output.
CD4052BC is a differential 4-channel multiplexer having ■ Binary address decoding on chip
two binary control inputs, A and B, and an inhibit input. The
two binary input signals select 1 or 4 pairs of channels to
be turned on and connect the differential analog inputs to
the differential outputs.
CD4053BC is a triple 2-channel multiplexer having three
separate digital control inputs, A, B, and C, and an inhibit
input. Each control input selects one of a pair of channels
which are connected in a single-pole double-throw configu-
ration.

Ordering Code:
Order Number Package Number Package Description
CD4051BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CD4051BCSJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
CD4051BCMTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
CD4051BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
CD4052BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CD4052BCSJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
CD4052BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
CD4053BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CD4053BCSJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
CD4053BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

© 2002 Fairchild Semiconductor Corporation DS005662 www.fairchildsemi.com

CD4051BC • CD4052BC • CD4053BC
Connection Diagrams
Pin Assignments for DIP and SOIC

CD4051BC CD4052BC

CD4053BC

Truth Table
INPUT STATES “ON” CHANNELS
INHIBIT C B A CD4051B CD4052B CD4053B
0 0 0 0 0 0X, 0Y cx, bx, ax
0 0 0 1 1 1X, 1Y cx, bx, ay
0 0 1 0 2 2X, 2Y cx, by, ax
0 0 1 1 3 3X, 3Y cx, by, ay
0 1 0 0 4 cy, bx, ax
0 1 0 1 5 cy, bx, ay
0 1 1 0 6 cy, by, ax
0 1 1 1 7 cy, by, ay
1 * * * NONE NONE NONE
*Don’t Care condition.

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 CD4051BC • CD4052BC • CD4053BC
Logic Diagrams
CD4051BC

CD4052BC

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CD4051BC • CD4052BC • CD4053BC
Logic Diagrams (Continued)
CD4053BC

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 CD4051BC • CD4052BC • CD4053BC
Absolute Maximum Ratings(Note 1) Recommended Operating
DC Supply Voltage (VDD) −0.5 VDC to +18 VDC Conditions
Input Voltage (VIN) −0.5 VDC to VDD +0.5 VDC DC Supply Voltage (VDD) +5 VDC to +15 VDC
Storage Temperature Input Voltage (VIN) 0V to VDD VDC
Range (TS) −65°C to +150°C Operating Temperature Range (TA)
Power Dissipation (PD) CD4051BC/CD4052BC/CD4053BC −55°C to +125°C
Dual-In-Line 700 mW Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. Except for “Operating Tempera-
Small Outline 500 mW
ture Range” they are not meant to imply that the devices should be oper-
Lead Temperature (TL) ated at these limits. The Electrical Characteristics tables provide conditions
for actual device operation.
(soldering, 10 seconds) 260°C

DC Electrical Characteristics (Note 2)

−55°C +25° 125°C
Symbol Parameter Conditions Units
Min Max Min Typ Max Min Max
Control A, B, C and Inhibit
IIN Input Current VDD = 15V, VEE = 0V −0.1
−0.1 −10−5 −1.0
VIN = 0V
µA
VDD = 15V, VEE = 0V
0.1 10−5 0.1 1.0
VIN = 15V
IDD Quiescent Device Current VDD = 5V 5 5 150
VDD = 10V 10 10 300 µA
VDD = 15V 20 20 600
Signal Inputs (VIS) and Outputs (VOS)
RON “ON” Resistance (Peak RL = 10 kΩ VDD = 2.5V,
for VEE ≤ VIS ≤ VDD) (any channel VEE = −2.5V
800 270 1050 1300 Ω
selected) or VDD = 5V,
VEE = 0V
VDD = 5V,
VEE = −5V
310 120 400 550 Ω
or VDD = 10V,
VEE = 0V
VDD = 7.5V,
VEE = −7.5V
200 80 240 320 Ω
or VDD = 15V,
VEE = 0V
∆RON ∆ “ON” Resistance RL = 10 kΩ VDD = 2.5V,
Between Any Two (any channel VEE = −2.5V
10 Ω
Channels selected) or VDD = 5V,
VEE = 0V
VDD = 5V
VEE = −5V
10 Ω
or VDD = 10V,
VEE = 0V
VDD = 7.5V,
VEE = −7.5V
5 Ω
or VDD = 15V,
VEE = 0V
“OFF” Channel Leakage VDD=7.5V, VEE=−7.5V
Current, any channel “OFF” O/I=±7.5V, I/O=0V ±50 ±0.01 ±50 ±500 nA
“OFF” Channel Leakage Inhibit = 7.5V CD4051 ±200 ±0.08 ±200 ±2000
Current, all channels VDD = 7.5V,
“OFF” (Common VEE = −7.5V, D4052 ±200 ±0.04 ±200 ±2000 nA
OUT/IN) O/I = 0V
I/O = ±7.5V CD4053 ±200 ±0.02 ±200 ±2000

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CD4051BC • CD4052BC • CD4053BC
DC Electrical Characteristics (Continued)

−55°C +25° 125°C

Symbol Parameter Conditions Units
Min Max Min Typ Max Min Max
Control Inputs A, B, C and Inhibit
VIL LOW Level Input Voltage VEE = VSS RL = 1 kΩ to VSS
IIS<2 µA on all OFF Channels
VIS = VDD thru 1 kΩ
VDD = 5V 1.5 1.5 1.5
VDD = 10V 3.0 3.0 3.0 V
VDD = 15V 4.0 4.0 4.0
VIH HIGH Level Input Voltage VDD = 5 3.5 3.5 3.5
VDD = 10 7 7 7 V
VDD = 15 11 11 11
Note 2: All voltages measured with respect to VSS unless otherwise specified.

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 CD4051BC • CD4052BC • CD4053BC
AC Electrical Characteristics (Note 3)
TA = 25°C, tr = tf = 20 ns, unless otherwise specified.
Symbol Parameter Conditions VDD Min Typ Max Units
tPZH, Propagation Delay Time from VEE = VSS = 0V 5V 600 1200
tPZL Inhibit to Signal Output RL = 1 kΩ 10V 225 450 ns
(channel turning on) CL = 50 pF 15V 160 320
tPHZ, Propagation Delay Time from VEE = VSS = 0V 5V 210 420
tPLZ Inhibit to Signal Output RL = 1 kΩ 10V 100 200 ns
(channel turning off) CL = 50 pF 15V 75 150
CIN Input Capacitance
Control input 5 7.5 pF
Signal Input (IN/OUT) 10 15
COUT Output Capacitance
(common OUT/IN)
CD4051 10V 30
CD4052 VEE = VSS = 0V 10V 15 pF
CD4053 10V 8
CIOS Feedthrough Capacitance 0.2 pF
CPD Power Dissipation Capacitance
CD4051 110
CD4052 140 pF
CD4053 70
Signal Inputs (VIS) and Outputs (VOS)
Sine Wave Response RL = 10 kΩ
(Distortion) fIS = 1 kHz 10V 0.04 %
VIS = 5 Vp-p
VEE = VSI = 0V
Frequency Response, Channel RL = 1 kΩ, VEE = 0V, VIS = 5Vp-p, 10V 40 MHz
“ON” (Sine Wave Input) 20 log10 VOS/VIS = −3 dB
Feedthrough, Channel “OFF” RL = 1 kΩ, VEE = VSS = 0V, VIS = 5Vp-p, 10V 10 MHz
20 log10 VOS/VIS = −40 dB
Crosstalk Between Any Two RL = 1 kΩ, VEE = VSS = 0V, VIS(A) = 5Vp-p 10V 3 MHz
Channels (frequency at 40 dB) 20 log10 VOS(B)/VIS(A) = −40 dB (Note 4)
tPHL Propagation Delay Signal VEE = VSS = 0V 5V 25 55
tPLH Input to Signal Output CL = 50 pF 10V 15 35 ns
15V 10 25
Control Inputs, A, B, C and Inhibit
Control Input to Signal VEE = VSS = 0V, RL = 10 kΩ at both ends
Crosstalk of channel. 10V 65 mV (peak)
Input Square Wave Amplitude = 10V
tPHL, Propagation Delay Time from VEE = VSS = 0V 5V 500 1000
tPLH Address to Signal Output CL = 50 pF 10V 180 360 ns
(channels “ON” or “OFF”) 15V 120 240
Note 3: AC Parameters are guaranteed by DC correlated testing.
Note 4: A, B are two arbitrary channels with A turned “ON” and B “OFF”.

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CD4051BC • CD4052BC • CD4053BC
Special Considerations
In certain applications the external load-resistor current switch must not exceed 0.6V at TA ≤ 25°C, or 0.4V at
may include both VDD and signal-line components. To TA > 25°C (calculated from RON values shown). No VDD
avoid drawing VDD current when switch current flows into current will flow through RL if the switch current flows into
IN/OUT pin, the voltage drop across the bidirectional OUT/IN pin.

Typical Performance Characteristics

“ON” Resistance vs Signal “ON” Resistance as a
Voltage for TA = 25°C Function of Temperature for
VDD− VEE = 10V

“ON” Resistance as a “ON” Resistance as a

Function of Temperature for Function of Temperature for
VDD− VEE = 15V VDD − VEE = 5V

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 CD4051BC • CD4052BC • CD4053BC
Switching Time Waveforms

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CD4051BC • CD4052BC • CD4053BC
Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A

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 CD4051BC • CD4052BC • CD4053BC
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D

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CD4051BC • CD4052BC • CD4053BC
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16

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 Multiplexer/Demultiplexer • Triple 2-Channel Analog Multiplexer/Demultiplexer
CD4051BC • CD4052BC • CD4053BC Single 8-Channel Analog Multiplexer/Demultiplexer • Dual 4-Channel Analog
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N16E

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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