THE UNIVERSITY OF THE WEST INDIES
EXAMINATION OF MAY 2005
Code and Name of Course: EE37E ADVANCED DIGITAL ELECTRONICS
Paper:1/1
Date and Time:
Duration: 3 hours
INSTRUCTIONS TO CANDIDATES: This paper has 7 pages and 3 questions.
ANSWER ALL QUESTIONS
DOCUMENTS ARE NOT ALLOWED
NO CALCULATORS ALLOWED
Q1 A last-in/first-out (LIFO) memory or stack memory (see Fig. Q1) stores bit vectors in the
order in which they were written into the memory; however, in a read operation, the mostrecently entered vector (the top of the stack, last in) is transferred to the output and deleted
from the stack. No external address is needed because the access is always performed to the
top of the stack. Read and write operations are usually called pop and push, respectively. A
stack also provides empty and full conditions. A LIFO memory would be used, for example,
when a sequence of events is to be traced in an order that is the reverse of the order of
occurrence. We consider the design of a 32 x 4 bits LIFO.
6 marks
a) Complete the behavioral description of the LIFO (Answer Q1a).
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
2 marks
entity lifo_mod is
generic(n: natural := 16); -- lifo size
Port ( clk : in std_logic;
-- clk signal
reset : in std_logic;
-- reset signal
Wr : in std_logic;
-- write signal
Rd : in std_logic;
-- read signal
full : out std_logic;
-- full
empty : out std_logic;
-- empty
Datain : in std_logic_vector(3 downto 0); -- data in
Dataout : out std_logic_vector(3 downto 0)); -- data out
end lifo_mod;
The University of the West Indies
Course Code EE37E
2 marks
2 marks
3 marks
5 marks
December 2005
DO NOT WRITE ON THE BACK OF THIS SHEET: USE ONE SIDE ONLY
INSTRUCTIONS: Each page must be signed by the Examiners and where applicable, the University Examiner and/or the
External Examiner. Where the examination does not require a University examiner, he form must be signed by the First and
Second Examiners. Completed forms should be handed to the Assistant Registrar (Examinations). The EXTERNAL
EXAMINER is requested to sign the draft paper and return it with comments, if any, (on a separate sheet) to the Assistant
Registrar (Examinations).
First Examiner
University Examiner
Second Examiner
External Examiner
Date:
2005../.11../...
Date: 2005../.11../...
(where applicable)
page 2
architecture Behavioral of lifo_mod is
type store is array (0 to n-1) of std_logic_vector(3 downto 0);
signal lifo_st: store;
signal index: integer range -1 to n-1:=0;
begin
process(reset, clk)
begin
if(reset = '1') then
index <= -1;
Dataout<= "0000";
empty <= '1';
full <= '0';
elsif (clk'event and clk ='1') then
if (wr ='1') then
if (index = n-1) then
empty <= '0';
full <= '1';
else
lifo_st(index +1) <= Datain;
index <= index +1;
empty <= '0';
end if; -- if index =n-1
elsif (Rd = '1') then -- read operation
if (index = -1) then
empty <= '1';
full <= '0';
else
Dataout<= lifo_st(index);
index <= index -1;
full <= '0';
end if; -- if index =-1
else
Null;
end if; -- end if write
end if; -- reset if
end process;
end Behavioral;
The University of the West Indies
Course Code: EE37E
December 2005
DO NOT WRITE ON THE BACK OF THIS SHEET: USE ONE SIDE ONLY
INSTRUCTIONS: Each page must be signed by the Examiners and where applicable, the University Examiner and/or the
External Examiner. Where the examination does not require a University examiner, he form must be signed by the First and
Second Examiners. Completed forms should be handed to the Assistant Registrar (Examinations). The EXTERNAL
EXAMINER is requested to sign the draft paper and return it with comments, if any, (on a separate sheet) to the Assistant
Registrar (Examinations).
First Examiner
University Examiner
Second Examiner
External Examiner
Date:
2005../.11../...
Date: 2005../.11../...
(where applicable)
page 3
b) Draw the logic block diagram of the LIFO.
c) The data path is made of a register file (1-read and 1-write).
i.
Specify the data path input/output signals.
ii.
Draw the data path logic block diagram and identify all the control points.
d) Consider the design of the microprogrammed control unit.
i.
Define a microinstruction for this design. Use a horizontal format with the
appropriate sequencing method.
ii.
1. Initial state
Write the corresponding microprogram.
2. After PUSH b
empty
push
a
LIFO
pop
full
3. After PUSH c
Z
(data_out)
4. After POP c
(data_in)
(a)
a
(b)
Fig. Q1: LIFO. (a) Module. (b) Examples of read/write operations.
Q2
a) Functional units (data paths) can be classified in three groups. Name them, and 4 marks
briefly describe their specifications.
The University of the West Indies
Course Code: EE37E
December 2005
DO NOT WRITE ON THE BACK OF THIS SHEET: USE ONE SIDE ONLY
INSTRUCTIONS: Each page must be signed by the Examiners and where applicable, the University Examiner and/or the
External Examiner. Where the examination does not require a University examiner, he form must be signed by the First and
Second Examiners. Completed forms should be handed to the Assistant Registrar (Examinations). The EXTERNAL
EXAMINER is requested to sign the draft paper and return it with comments, if any, (on a separate sheet) to the Assistant
Registrar (Examinations).
First Examiner
University Examiner
Second Examiner
External Examiner
Date:
2005../.11../...
Date: 2005../.11../...
(where applicable)
page 4
2 marks
b) What are FPGA Fabrics?
c) Consider the following combinational logic circuit constructed from 6 modules. In
the diagram of Fig. Q2c, each combinational component is marked with its
propagation delay in seconds; contamination delays are zero for each component.
2 marks
i.
What is the latency and throughput of this combinational circuit?
ii.
Place the smallest number of ideal (zero delay, zero setup/hold time)
pipeline registers in the circuit above so as to maximize its throughput.
Remember to place a register on the output.
3 marks
iii.
What is the latency and throughput of your pipelined circuit?
2 marks
d) Complete the table of Fig.Q2d that summarizes some the key points of the various 4 marks
programming technologies.
e) Explain in few lines the primary functions of scheduling and allocation in high- 3 marks
level synthesis.
Fig. Q2c.
Q3 Consider the design of an accumulator-based CPU that supports a bare minimum of
registers. The Accu (also noted Akku) has a width of eight bits and is complemented by a
carry flag. The program counter (PC) has a width of six bits which allows to address 64
eight-bit words of memory. The memory is shared between program code and data. The
CPU is connected to the memory by using the data and address buses and two others
signals (oe = output enable, and we = write enable)
Each instruction is one word wide. A single instruction format is used. It is encoded with a
The University of the West Indies
Course Code: EE37E
December 2005
DO NOT WRITE ON THE BACK OF THIS SHEET: USE ONE SIDE ONLY
INSTRUCTIONS: Each page must be signed by the Examiners and where applicable, the University Examiner and/or the
External Examiner. Where the examination does not require a University examiner, he form must be signed by the First and
Second Examiners. Completed forms should be handed to the Assistant Registrar (Examinations). The EXTERNAL
EXAMINER is requested to sign the draft paper and return it with comments, if any, (on a separate sheet) to the Assistant
Registrar (Examinations).
First Examiner
University Examiner
Second Examiner
External Examiner
Date:
2005../.11../...
Date: 2005../.11../...
(where applicable)
page 5
two-bit opcode and a six bits address/immediate field.
Mnemonic
Opcode
Description
NOR
ADD
STA
JCC
Accu Acc NOR mem[AAAAAA]
Accu Accu + mem[AAAAAA], update carry
Mem[AAAAAA] Acc
Set PC to DDDDDDD when carry = 0, clear carry
00AAAAAA
01AAAAAA
10AAAAAA
11DDDDDD
Table 1: Instruction set listing
The four encoded instructions are listed in table 1. The instructions are used in the context
of an accumulator-based architecture. This made the additional STA instruction mandatory.
The benefits are a bigger code density (Instructions are just one word instead of two.) and
an even simpler cpu architecture.
One interesting aspect is the branch instruction JCC. Branches are always conditional.
However the JCC instruction clears the carry, so that succeeding branches are always taken.
This allows efficient unconditional, or two way branches.
One design goal was to minimize the amount of CLBs used purely for combinational logic,
to maximize the amount of usable registers. Due to this, structures like multiplexers
between registers and the address/data output have to be avoided at all costs. One
consequence was to divide the datapath into one path for the address and one for the data. In
contrast to other small cpus the adress generation is not done with the main ALU, therefore
a distinct incrementer is required for the PC.
The data path is controlled by a control unit that can be designed as a state machine.
2 marks
a) Write in VHDL the entity module of the CPU.
7 marks
b) Considering these specifications and the ISA of the small CPU, derive the digital
circuit of the data path. Show clearly all the control points.
2 marks
c) Derive the block diagram of the control.
7 marks
d) Draw the controllers state diagram.
2 marks
e) Propose a state encoding scheme that minimizes the required amount of CLBs.
The University of the West Indies
Course Code: EE37E
December 2005
DO NOT WRITE ON THE BACK OF THIS SHEET: USE ONE SIDE ONLY
INSTRUCTIONS: Each page must be signed by the Examiners and where applicable, the University Examiner and/or the
External Examiner. Where the examination does not require a University examiner, he form must be signed by the First and
Second Examiners. Completed forms should be handed to the Assistant Registrar (Examinations). The EXTERNAL
EXAMINER is requested to sign the draft paper and return it with comments, if any, (on a separate sheet) to the Assistant
Registrar (Examinations).
First Examiner
University Examiner
Second Examiner
External Examiner
Date:
2005../.11../...
Date: 2005../.11../...
(where applicable)
page 6
Detach this sheet for attachment to your answer script
(Answer Q1a)
Entity lifo is
Generic (n: natural:=16);
-- LIFO size
Port (X
: in bit_vector (n-1 downto 0); -- input bit-vector
Z
: out bit_vector (n-1 downto 0); -- output bit-vector
Rd, Wr
: in bit;
-- read, write control signals
Empty, Full
: out bit;
-- condition signals
Clk
: in bit);
End lifo;
Architecture behavioral of lifo is
-
- add your code here
The University of the West Indies
Course Code: EE37E
December 2005
DO NOT WRITE ON THE BACK OF THIS SHEET: USE ONE SIDE ONLY
INSTRUCTIONS: Each page must be signed by the Examiners and where applicable, the University Examiner and/or the
External Examiner. Where the examination does not require a University examiner, he form must be signed by the First and
Second Examiners. Completed forms should be handed to the Assistant Registrar (Examinations). The EXTERNAL
EXAMINER is requested to sign the draft paper and return it with comments, if any, (on a separate sheet) to the Assistant
Registrar (Examinations).
First Examiner
University Examiner
Second Examiner
External Examiner
Date:
2005../.11../...
Date: 2005../.11../...
(where applicable)
page 7
Detach this sheet for attachment to your answer script
(Answer Q1a)
-- add your code (continued)
end Process;
end behavioral;
The University of the West Indies
Course Code: EE37E
December 2005
DO NOT WRITE ON THE BACK OF THIS SHEET: USE ONE SIDE ONLY
INSTRUCTIONS: Each page must be signed by the Examiners and where applicable, the University Examiner and/or the
External Examiner. Where the examination does not require a University examiner, he form must be signed by the First and
Second Examiners. Completed forms should be handed to the Assistant Registrar (Examinations). The EXTERNAL
EXAMINER is requested to sign the draft paper and return it with comments, if any, (on a separate sheet) to the Assistant
Registrar (Examinations).
First Examiner
University Examiner
Second Examiner
External Examiner
Date:
2005../.11../...
Date: 2005../.11../...
(where applicable)
page 8
Detach this sheet for attachment to your answer script
Feature
SRAM
Anti-fuse
EEPROM/FLASH
Reprogrammable
IP Security
Rad Hard
Requires external configuration file
Good for prototyping
Fig. Q2d.
END OF QUESTION PAPER
The University of the West Indies
Course Code: EE37E
December 2005
DO NOT WRITE ON THE BACK OF THIS SHEET: USE ONE SIDE ONLY
INSTRUCTIONS: Each page must be signed by the Examiners and where applicable, the University Examiner and/or the
External Examiner. Where the examination does not require a University examiner, he form must be signed by the First and
Second Examiners. Completed forms should be handed to the Assistant Registrar (Examinations). The EXTERNAL
EXAMINER is requested to sign the draft paper and return it with comments, if any, (on a separate sheet) to the Assistant
Registrar (Examinations).
First Examiner
University Examiner
Second Examiner
External Examiner
Date:
2005../.11../...
Date: 2005../.11../...
(where applicable)
