Hardware Description Languages (HDLs)

Textural representation of a digital logic design

CSE372
Digital Systems Organization and Design
Lab
Prof. Milo Martin

Easier to edit and revise than schematics

However, you still need to think in terms of schematics (pictures)

HDLs are not programming languages

No, really. Even if they look like it, they are not.
One of the most difficult conceptual leaps of this course

Similar development chain

Compiler: source code ! assembly code ! binary machine code
Synthesis tool: HDL source ! gate-level specification ! hardware

Unit 1: Synthesizable Verilog

CSE 372 (Martin): Synthesizable Verilog

CSE 372 (Martin): Synthesizable Verilog

Hardware Description Languages (HDLs)

Verilog HDL

Write code to describe hardware

Verilog

Specify wires, gates, modules

Also hierarchical

One of two commonly-used HDLs

Verilog is a (surprisingly) big language
Lots of features for synthesis and simulation of hardware

Pro: easier to edit and create; Con: more abstract

module mux2to1(S, A, B, O);
input S, A, B;
output O;
wire S_, AnS_, BnS;
not (S_, S);
and (AnS_, A, S_);
and (BnS, B, S);
or (O, AnS_, BnS);
endmodule
CSE 372 (Martin): Synthesizable Verilog

Were going to learn a focused subset of Verilog

S
A

Focus on synthesizable constructs

Focus on avoiding subtle synthesis errors
Use as an educational tool
Initially restrict some features to build up primitives
Rule: if you havent seen it in lecture, you cant use it
Ask me if you have any questions

CSE 372 (Martin): Synthesizable Verilog

HDL History

Two Roles of HDL and Related Tools

1970s: First HDLs

Late 1970s: VHDL

#1: Specifying digital logic

Specify the logic that appears in final design
Either
Translated automatically (called synthesis) or
Optimized manually (automatically checked for equivalence)

VHDL = VHSIC HDL = Very High Speed Integrated Circuit HDL

VHDL inspired by programming languages of the day (Ada)

1980s:
Verilog first introduced
Verilog inspired by the C programming language
VHDL standardized

#2: Simulating and testing a design

High-speed simulation is crucial for large designs
Many HDL interpreters optimized for speed
Testbench: code to test design, but not part of final design

1990s:
Verilog standardized (Verilog-1995 standard)

2000s:
Continued evolution (Verilog-2001 standard)

Both VHDL and Verilog evolving, still in use today

CSE 372 (Martin): Synthesizable Verilog

CSE 372 (Martin): Synthesizable Verilog

Synthesis vs Simulation

Structural vs Behavioral HDL Constructs

HDLs have features for both synthesis and simulation

Structural constructs specify actual hardware structures

E.g., simulation-only operations for error messages, reading files

Obviously, these can be simulated, but not synthesized into circuits
Also has constructs such as for-loops, while-loops, etc.
These are either un-synthesizable or (worse) synthesize poorly

Low-level, direct correspondence to hardware

Primitive gates (e.g., and, or, not)
Hierarchical structures via modules
Analogous to programming software in assembly

Behavioral constructs specify an operation on bits

High-level, more abstract
Specified via equations, e.g., out = (a & b) | c
Statements, e.g., if-then-else
Analogous to programming software in C

Trends: a moving target

Good: better synthesis tools for higher-level constructs
Bad: harder than ever to know what is synthesizable or not

Not all behavioral constructs are synthesizable

Even higher-level, synthesize poorly or not at all (e.g., loops)
Perhaps analogous to programming in Perl, Python, Matlab, SQL
CSE 372 (Martin): Synthesizable Verilog

CSE 372 (Martin): Synthesizable Verilog

Verilog Structural vs Behavioral Example

Structural
module mux2to1(S, A, B, Out);
input S, A, B;
output Out;
A
wire S_, AnS_, BnS;
B
not (S_, S);
and (AnS_, A, S_);
and (BnS, B, S);
or (Out, AnS_, BnS);
endmodule
Behavioral
module mux2to1(S, A, B, Out);
input S, A, B;
output Out;
assign Out = (~S & A) | (S & B);
endmodule
CSE 372 (Martin): Synthesizable Verilog

Recall: Two Types of Digital Circuits

Combinational Logic

S
Out

Logic without state variables

Examples: adders, multiplexers, decoders, encoders
No clock involved

Sequential Logic

Logic with state variables

State variables: latches, flip-flops, registers, memories
Clocked
State machines, multi-cycle arithmetic, processors

Todays lecture: Verilog for specifying combinational logic

Sequential logic will be covered later
Focus on structural constructs with limited behavioral ones
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CSE 372 (Martin): Synthesizable Verilog

Verilog Structural Primitives

Three Module Components

Gate-level

Interface specification

One-output boolean operators: and, or, xor, nand, nor, xnor

E.g., C = A+B
or (C, A, B);
E.g., C= A+B+D
or (C, A, B, D);
One-input operators: not, buf
E.g., A = not Z
not (A, Z);
E.g., A = not Z, B = not Z
not (A, B, Z);
Buf just replicates signals (can increase drive strength)

Transistor-level primitives too

module mux2to1(S, A, B, O);

input S, A, B;
output O;
Can also have inout: bidirectional wire (we will not need)

Alternative: Verilog 2001 interface specification

module mux2to1(input S, A, B, output O);

Declarations
Internal wires, i.e., local variables
Wires also known as nets or signals
wire S_, AnS_, BnS;

Implementation: primitive and module instantiations

Will not use

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and (AnS_, A, S_);

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Verilog Module Example

module mux2to1(S, A, B, O);
input S, A, B;
output O;
wire S_, AnS_, BnS;
not (S_, S);
and (AnS_, A, S_);
and (BnS, B, S);
or (O, AnS_, BnS);
endmodule

Hierarchical Verilog Example

Build up more complex modules using simpler modules
Example: 4-bit wide mux from four 1-bit muxes
Again, just drawing boxes and wires
S
A

module mux2to1_4(Sel, A, B, O);

input [3:0] A;
input [3:0] B;
input Sel;
output [3:0] O;

CSE 372 (Martin): Synthesizable Verilog

mux2to1
mux2to1
mux2to1
mux2to1
endmodule
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mux0
mux1
mux2
mux3

A[0],
A[1],
A[2],
A[3],

B[0],
B[1],
B[2],
B[3],

O[0]);
O[1]);
O[2]);
O[3]);

CSE 372 (Martin): Synthesizable Verilog

Connections by Name

Vectors of Wires

Can (should) specify module connections by name

Wire vectors:

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wire [7:0] W1;

// 8 bits, w1[7] is MSB
wire [0:7] W2;
// 8 bits, w2[0] is MSB
Also called arrays or busses

Helps keep the bugs away

Example
mux2to1 mux0 (.S(Sel), .A(A[0]), .B(B[0]), .O(O[0]));

Also, order doesnt matter

Operations

mux2to1 mux1 (.A(A[1]), .B(B[1]), .O(O[1]), .S(Sel));

CSE 372 (Martin): Synthesizable Verilog

(Sel,
(Sel,
(Sel,
(Sel,

Bit select: W1[3]

Range select: W1[3:2]
Concatenate: {<expr>[,<expr>]*}
vec = {x, y, z};
{carry, sum} = vec[0:1];
e.g., swap high and low-order bytes of 16-bit vector
wire [15:0] w1, w2;
assign w2 = {w1[7:0], w1[15:8]}
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Wire and Vector Assignment

Operators

Wire assignment: continuous assignment

Operators similar to C or Java

On wires:

Connect combinational logic block or other wire to wire input

Order of statements not important, executed totally in parallel
When right-hand-side changes, it is re-evaluated and re-assigned
Designated by the keyword assign
wire c;
assign c = a | b;
wire c = a | b;
// same thing

& (and), | (or), ~ (not), ^ (xor)

On vectors:
&, |, ~, ^ (bit-wise operation on all wires in vector)
E.g., assign vec1 = vec2 & vec3;
&, |, ^ (reduction on the vector)
E.g., assign wire1 = | vec1;
Even ==, != (comparisons) +, -, * (arithmetic), <<, >> (shifts)
But you cant use these, yet. Can you guess why?
Note: use with care, assume unsigned numbers
Verilog 2001: signed vs unsigned vectors, >>> operator

Can be arbitrarily nested: (a & ~b) | c

CSE 372 (Martin): Synthesizable Verilog

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CSE 372 (Martin): Synthesizable Verilog

Conditional Operator

Miscellaneous

Verilog supports the ?: conditional operator

Operators and expressions can be used with modules

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!mux2to1 mux0 (cond1 & cond2, a, b, out);

Almost never useful in C (in my opinion)

Much more useful in Verilog

C/Java style comments

// comment until end of line
/* comment between markers */

Examples:
assign out = S ? B : A;

All variable names are case sensitive

assign out = sel
sel
sel
sel

==
==
==
==

2'b00
2'b01
2'b10
2'b11

?
?
?
?

a
b
c
d

:
:
:
: 1'b0;

Constants:

What do these do?

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assign x = 3b011
The 3 is the number of bits
The b means binary - h for hex, d for decimal
The 011 are the digits (in binary in this case)

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Arrays of Modules

Parameters

Verilog also supports arrays of module instances

Allow per-instantiation module parameters

Well, at least some Verilog tools

Support for this feature varies

Use parameter statement

modname #(10, 20, 30) instname(in1, out1);

Example:

module mux2to1_4(Sel, A, B, O);

input [3:0] A;
input [3:0] B;
input Sel;
output [3:0] O;

module mux2to1_N(Sel, A, B, O);

parameter N = 1
input [N-1:0] A;
input [N-1:0] B;
input Sel;
output [N-1:0] O;
mux2to1 mux0[N-1:0] (Sel, A, B, O);
endmodule

Mux2to1_N #(4) mux1 (S, in1, in2, out)

mux2to1 mux0[3:0] (Sel, A, B, O);

endmodule

CSE 372 (Martin): Synthesizable Verilog

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CSE 372 (Martin): Synthesizable Verilog

Last Multiplexer Example

Verilog Pre-Processor

Using conditional operator

Like the C pre-processor

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But uses ` (back-tick) instead of #

Constants: `define
No parameterized macros
Use ` before expanding constant macro
`define letter_A 8h41
wire w = `letter_A;

module mux2to1_N(Sel, A, B, Out);

parameter N = 1
input [N-1:0] A;
input [N-1:0] B;
input Sel;
output [N-1:0] Out;
assign Out = Sel ? B : A
endmodule

Conditional compilation: `ifdef, `endif

File inclusion: `include

Parameter vs `define
Parameter only for per instance constants
`define for global constants
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CSE 372 (Martin): Synthesizable Verilog

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Common Errors

Additional Verilog Resources

Tools are from a less gentle time

Elements of Logic Design Style by Shing Kong, 2001

More like C, less like Java

Assume that you mean what you say

Dos, do-nots, tips

http://www.cis.upenn.edu/~milom/elements-of-logic-design-style/

Common errors:

Verilog HDL Synthesis: A Practical Primer

Not assigning a wire a value

Assigning a wire a value more than once
Implicit wire declarations (default to type wire)
Disable by adding the following to the file:
`default_nettype none
Does not work with ModelSim

By J. Bhasker, 1998
To the point (<200 pages)

Advanced Digital Design with the Verilog HDL

By Michael D. Ciletti, 2003
Verilog plus lots of digital logic design (~1000 pages)

!Avoid names such as:

clock, clk, power, pwr, ground, gnd, vdd, vcc, init, reset, rst
Some of these are special and will silently cause errors
CSE 372 (Martin): Synthesizable Verilog

Verilog tutorial on CD from Computer Org. and Design

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CSE 372 (Martin): Synthesizable Verilog

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Lab 1 - ALU (Arithmetic/Logical Unit)

Task: design an ALU for a P37X CPU

CSE372
Digital Systems Organization and Design
Lab
Prof. Milo Martin

Ten operations:

Addition, subtraction
Multiplication
And, or, not, xor
Shift left, logical shift right, arithmetic shift right

The different adder implementations

Ripple-carry
Two carry-select adders

Unit 1: Synthesizable Verilog (continued)

Pay close attention in CSE371 lecture this week!

CSE 372 (Martin): Synthesizable Verilog

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CSE 372 (Martin): Synthesizable Verilog

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Aside: Honors Points

Aside: Due Dates and Late Days

Goals:

Normal due dates

Make the labs accessible to all

Challenge those that want more

Lab demos are on Fridays

Lab write-ups are due on Mondays (at start of class)

So, Im trying something different

Again, experimental

Ill give you two late credits for the semester

Labs will have two types of points

Used for emergencies, sickness, travel, etc.

Otherwise, no late assignments accepted

Normal - standard labs

Honors - above and beyond

Normal points

Impact of using a late credit

Get all the normal points -> A- in the class

Demo moved from Friday to Monday

Lab write-up moved from Monday to Wednesday (in TA lab hours)
No honors points for these late assignments

Honors points
Will distinguish the A- from A and A+
May bump others a third of a letter grade

Examples: fast adders (lab 1), advanced pipelines

CSE 372 (Martin): Synthesizable Verilog

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CSE 372 (Martin): Synthesizable Verilog

Repeated Signals

FYI: Non-binary Hardware Values

Last time we discussed vector concatenation

assign vec = {x, y, z};

A hardware signal can have four values

Can also repeat a signal n times

assign vec = {16{x}};

0, 1
X: dont know, dont care
Z: high-impedance (no current flowing)

// 16 copies of x

Example uses (what does this do?):

wire [7:0] out;
wire [3:0] A;
assign out = {{4{0}}, A[3:0]};

Uses for x
Tells synthesis tool you dont care
Synthesis tool makes the most convenient circuit (fast, small)
Use with care, leads to synthesis dependent operation

Uses for z
Tri-state devices drive a zero, one, or nothing (z)
Many tri-states drive the same wire, all but one must be z
Makes some circuits very fast
Example: multiplexer
Why Verilog allows multiple assignments to same wire.

What about this?

assign out = {{4{A[3]}}, A[3:0]};

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CSE 372 (Martin): Synthesizable Verilog

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Simulation

Levels of Simulation

Used to test and debug our designs

Graphical output via waveforms

Functional (or Behavioral) Simulation

Simulates Verilog abstractly
No timing information, cant detect timing bugs

Post-synthesis Timing Simulation

Simulating devices generated via synthesis
Gates, transistors, FPGA logical units (LUTs)
No interconnect delay
Not all internal signals may still exist
Synthesis might have optimized or changed the design
Slower

Layout Timing Simulation

After synthesis, the tool places and routes the logic blocks
Includes all sources of delay
Even slower
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CSE 372 (Martin): Synthesizable Verilog

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Sequential Logic in Verilog

Designing Sequential Logic

How do we specify state-holding constructs in Verilog?

CSE372 design rule: separate comb. logic from sequential

state elements
Not enforced by Verilog, but a very good idea
Possible exceptions: counters, shift registers

module dff (Clock, D, WE, Reset, Q);

input Clock, D, WE, Reset;
output Q;
reg Q;
always @(posedge Clock)
begin
if (Reset)
Q = 1'b0;
else if (WE)
Q = D;
end
endmodule
CSE 372 (Martin): Synthesizable Verilog

Well give you a 1-bit flip-flop module (see previous slide)

Edge-triggered, not a latch
Use it to build a n-bit register

Example use: state machine

Clock
State
Register

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CSE 372 (Martin): Synthesizable Verilog

Current
State

Combinational
Logic

Output
Next State
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Clocks Signals
Clocks signals are not normal signals
Travel on dedicated clock wires
Reach all parts of the chip
Special low-skew routing

Ramifications:
Never do logic operations on the clocks
If you want to add a write enable to a flip-flop:
Use a mux to route the old value back into it
Do not just and the write-enable signal with the clock!

Messing with the clock can cause a errors

Often can only be found using timing simulation
CSE 372 (Martin): Synthesizable Verilog

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