UVM Debug Presentation
Uwe Simm
Solution Architect
[email protected]
Agenda
Cadence Debug Overview
Testbench and UVM Debug Overview
Incisive Debug Analyzer
Summary
2013 Cadence Design Systems, Inc. All rights reserved.
Agenda
Cadence Debug Overview
Testbench and UVM Debug Overview
Incisive Debug Analyzer
Summary
2013 Cadence Design Systems, Inc. All rights reserved.
Debug Today: A Turning Point
Historically everyone was a hardware engineer:
Debug effort focused only on RTL
Testbench code written in HDL (by design engineers)
Debug Techniques:
Waveforms
Signal tracing
$display()/log files
Post process debug
Designs were smaller
Faster simulations
Print statements could suffice
Designs were less complex
No HW/SW Interaction
No need for OOP/AOP verification environments
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2013 Cadence Design Systems, Inc. All rights reserved.
Debug Today: A Turning Point
Today, there is a need for software
engineering skills in verification:
Large, complex designs require scalable, OO/
AO, re-usable testbenches
HVL languages (SystemVerilog/e) are required
to be efficient and competitive in the market
SW debug techniques are a must to be efficient:
Breakpoints
Single Stepping
Watch Windows
Interactive Debug
Transaction Debug
The need for SW debug techniques
in verification will only increase
moving forward
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2013 Cadence Design Systems, Inc. All rights reserved.
Agenda
Cadence Debug Overview
Testbench and UVM Debug Overview
Incisive Debug Analyzer
Summary
2013 Cadence Design Systems, Inc. All rights reserved.
SimVision
Core
Performance
and
Multi-language, mixed signal debug environment.
Supports all IEEE-std design/testbench languages:
Verilog, SystemVerilog, e, VHDL, and SystemC
Stability
Leverage SimVision debug from the Virtuoso, Incisive and Systems environments
Supports analog and mixed-level behavioral abstractions of wreal, SystemVerilog reals,
Verilog-AMS, and Verilog/VHDL
e/SystemVerilog class-based debug: SimVision offers interactive and/or post-process
debug that supports OOP/AOP class-based debug environments
UVM aware: Provide debugability of testbench through class inheritance and instance tree
Supports signal-level and transaction-based flows in interactive and post
process modes, and all assertion languages
SimVision adds a novel stripe chart view that allows visualization of the sequential order of
transactions across multiple streams
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2013 Cadence Design Systems, Inc. All rights reserved.
UVM Debug Challenges
Hardware Verification Languages (HVLs) are, necessarily, much more powerful
than HDL
Need to efficiently model the entire world around the DUT
Powerful features of HVLs bring added complexity:
Polymorphism
Object partitioning (header files)
Randomization/Generation
Coverage
Assertions
Automated Self Checking
UVM brings even more complexity to the picture
Base class library not written by the user
360+ macros utilized for various reasons
New methodology to learn
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2013 Cadence Design Systems, Inc. All rights reserved.
Heavy macro usage
UVM base class
inheritance
UVM register modeling
Phased execution
Factory overrides
Configuration Debug
Objections
Sequence Debug
UVM Debug
Challenges
UVM Debug
Hyperlinked UVM Messages - 1
SimVision supports clickable UVM Messages in the Console
Colourized based on severity
Take users directly to point of interest
Colourized
based on
message
type
Hovering over specific
message brings up menu
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2013 Cadence Design Systems, Inc. All rights reserved.
Users can then
perform a number of
actions on message
attributes
UVM Sequence Viewer
Rapid debug of sequence based stimulus
Double click of
any item opens
source in-scope
When items
selected,
sequencer is
bolded
Find box to easily search
within the hierarchy
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Can jump to the parent or
the root sequence
2013 Cadence Design Systems, Inc. All rights reserved.
Indicates whether item
is in flight or finished
Indicates the
sequencer that the
item belongs to
UVM Register Viewer (sv+e)
Register Hierarchy (maps/
blocks) for both SV and e
Registers
and
Fields
Register Values
Access Type
Values
currently
changing
Find
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2013 Cadence Design Systems, Inc. All rights reserved.
Filtering
Enhanced UVM Support - 2
UVM Toolbar additions configuration database printing
Several options in the drop down
Dump
Dumps configuration database
Trace ON/OFF
Print read/write information
Audit ON/OFF
Prints get/set information
All information printed to the
Simulator console
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2013 Cadence Design Systems, Inc. All rights reserved.
Enhanced UVM Support - 3
UVM Toolbar additions printing the UVM hierarchy
Prints the UVM hierarchy to the
simulator console
One level deep
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2013 Cadence Design Systems, Inc. All rights reserved.
Enhanced UVM Support - 4
UVM Toolbar additions transaction recording control
Enables transaction recording for
all UVM objects for later debug
Sequences and sequence items
Additional UVM transactions
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2013 Cadence Design Systems, Inc. All rights reserved.
Enhanced Macro Support - 1
Macros and generate statements
Macro is expanded inline
with background to
indicate expanded macro
code
Source annotations
Hover to see +
sign for expansion
Tool tip shows a sample of the
macro and the original Source
File
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2013 Cadence Design Systems, Inc. All rights reserved.
Agenda
Cadence Debug Overview
Testbench and UVM Debug Overview
Incisive Debug Analyzer
Summary
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2013 Cadence Design Systems, Inc. All rights reserved.
Incisive Debug Analyzer
Nominated as the Product of the Year
Recipient of multiple awards for product innovation:
2013 EETimes/EDN Ace Award Finalist
2012 Cadence Product Innovation Award
2012 Cadence Invention of the Year Award
Debug productivity enhancer
Only one debug simulation cycle required no need to rerun
Single-click stepping/jumping through time
Any source code line or variable change even backwards
Integrated, interactive log file analysis capabilities
Rapid debug handover among global teams
We were using print messages for debug, but using this method, we werent able to catch all of the
errors
and it was
taking a really long time. Using Incisive Debug Analyzer, we were able to learn the
Scheduled
Availability:
structure
of ourinthird
testbench
step by step, and built a reliable
Released
Dec.party-developed
2012: Production Release
for environment
HDL and e
environment for fixing bugs. Using Incisive Debug Analyzer, we saved two months in our overall
Dec. 2013: Production Release for IDA SV
debug cycle
S. Sayar, Sr. Verification Engineer, STxP70 Team, STMicroelectronics
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2013 Cadence Design Systems, Inc. All rights reserved.
Incisive Debug Analyzer
Advanced Verification debugger
The first and only Interactive Post Process solution in EDA
today
New capabilities included in Debug Analyzer:
Post process Playback Debugger
Advanced Cause Analysis
Advanced search and exploration capabilities
Dynamic and Abstract Log
Designed to make your debug easier
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2013 Cadence Design Systems, Inc. All rights reserved.
Debug Analyzer - GUI
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Smartlog
Playback Debugger
Exploration
Cause Analysis
2013 Cadence Design Systems, Inc. All rights reserved.
Playback Debugger Step Back in Time
Playback
Debugger
Smart Log
Debug
Analyzer
Exploration
Cause
Analysis
Step/jump through time to any source code line or variable change
even backwards
Only one debug cycle (no need to re-run)
Zero time navigation (No real simulation)
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2013 Cadence Design Systems, Inc. All rights reserved.
Playback Debugger
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Time Tables
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Variables Table
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Calls Stack
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SmartLog
Advanced filtering options
Debugger location
Select a message
Message Text
(Connected to the source)
Waveform marker
Go to message execution
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Searcher
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2013 Cadence Design Systems, Inc. All rights reserved.
Searcher
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2013 Cadence Design Systems, Inc. All rights reserved.
Agenda
Cadence Debug Overview
Testbench and UVM Debug Overview
Incisive Debug Analyzer
Summary
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2013 Cadence Design Systems, Inc. All rights reserved.
UVM Debug Summary
The debug landscape has changed
HVLs warrant the need for more SW oriented debug techniques
There are many advantages to Interactive debug
Most efficient debug technique for complex software systems
Least number of debug iterations required
Access to a much broader set of debug tools
Most powerful debug technique to tackle the toughest debug challenges
UVM Methodology brings several unique debug challenges
Cadence is heavily focused on UVM debug
Increased technical collateral, YouTube debug videos, workshops, lunch-n-learn sessions,
available for customer ramp-up
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2013 Cadence Design Systems, Inc. All rights reserved.
Debug Collateral Pages
SimVision YouTube Videos
Cadence Debug Landing Page
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2013 Cadence Design Systems, Inc. All rights reserved.
SimVision Unique Advantages
UVM Awareness
Walk Up
Connections
Post Process
e/SV Class Debug
Enhanced Transaction Analysis
Enhanced Macro Debug
Hierarchical, MultiLevel Schematic
Smart Source
Annotation
Callouts+stacking
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2013 Cadence Design Systems, Inc. All rights reserved.
SC/C/C++Debug
Mixed Signal
Post Process Class Based Debug
Hierarchy Navigation
Full access to the entire dynamic class based hierarchy
UVM hierarchy
Internal class variables (critical for debug)
Object values at current
cursor time
Expandable Class Based
hierarchy
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2013 Cadence Design Systems, Inc. All rights reserved.
Post Process Class Based Debug
Waveform representation
Hover to bring up detailed info
in tool tips
Dynamic Class
Internal fields
changing
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2013 Cadence Design Systems, Inc. All rights reserved.
Changing Class
Handles
Click + to create
new group for this
transaction
