ARMCortexM3:

Overview&ProgrammersModel
ECE331,Spring2013

OverviewofComputingSystems

RISC
ARMstandsforAdvancedRISCMachine
RISC=ReducedInstructionSetComputer

Earliestworkbeganinthelate60s/early70s

RISC/ARMgoals

Allinstructionsexecutedinsinglecycle
Allinstructionswerethesamesizeandhadfixedformat(32bitsinthiscase)
Simpletodecodeinstructions
Easiertovalidate
Load/Storearchitecture.Datainexternalmemoryaccessedwithexplicit
instructions.Allotheroperations(adds,subtracts,logic,etc)useonlyregisters
ontheprocessor.

Featurecreep
Althoughitisareduced instructionset,manyinstructionshavebeenkeeping
upwiththeneedformoredemandingalgorithms.
Forinstance,31instructionsinBerkeleyRISC1,46inthesecondARM
processor,uptoseveralhundrednow.

WidespreadUseOfARMToday
Morethan10billionARMprocessorsshipped
sofar.

DigitalCameras
Antilockdiscbrakes
Gameboy
Appledevices
Cellphones(Android)
Somanymore

CortexM3Architecture
Microcontroller

System bus
Arm CortexTM-M3
processor

Input
ports

PPB
Internal NVIC
peripherals
Instructions
Flash ROM
ICode bus

Output
ports
Data
RAM

DCode bus

HarvardArchitecture:Separatedataandinstructionbuses
CortexM3instructionsetcombineshighperformancetypicalof
32bitprocessorwithcodedensityof8and16bitcontrollers
Each8bitbytehasuniqueaddressmeaningtheprocessorcan
readorwrite8,16,or32bitdata

Features
Somefeaturesvisibleinthepreviousslide
32bitcore
32bitaddressspace
32bitregisters
32bitshifterandALU
32bitmemorytransfer

ProgrammersModel
Registers:Themostbasicstorageareaonthechip.Canbeusedfordata,
timer,counter,addresses,etc.

30generalpurposeregisters(forloadsandstores)
6statusregisters
Aprogramcounter
37totalregisters

Atonetime
15generalpurposeregisters(r0r14)
Oneortwostatusregisters
Programcounter(r15orPC)

Allregistersare32bitswide

Onethingmanyfailtounderstandisthattheseregistersthemselvesoccupymemoryon
thedevice

Forinstance,registersonARM7TDMIarebetween0x100000000x10000FFF

Registers

Whatisaregister?
Highspeedstorageinsidetheprocessor
R0R12aregeneralpurposeregisters,containeitherdataoraddresses
R13isstackpointer,pointstotopelementofstack
R14islinkregister,usedtostorereturnlocationforfunctions(subroutines)
R15isthePC,pointstothenextinstructionbeingfetchedfrommemory

General
purpose
registers

Stack pointer
Link register
Program counter

R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13 (MSP)
R14 (LR)
R15 (PC)

256k Flash
ROM
64k RAM

0x0000.0000
0x0003.FFFF
0x2000.0000
0x2000.FFFF

I/O ports

0x4000.0000
0x41FF.FFFF

Internal I/O
PPB

0xE000.0000
0xE004.0FFF

SpecialPurposeRegisters
R13,theStackPointer:
Holdstheaddressofthestackinmemory
Uniquestackpointerinallmodes(exceptsystem shareswithuser)

R14,theLinkRegister:
Subroutinereturnaddresslinkregister
Uniquelinkregisterinallmodes(exceptsystemshareswithuser)

R15,Programcounter(PC)
PCholdsaddressofinstructionbeingfetched.
Usuallyonlyusedforlongmemoryjumpsorexceptionrecovery

CurrentProgramStatusRegister(CPSR)
Stateofthemachine
Allowsprogramstorecoverfromexceptionsorbranchonresultsofan
operation

InstructionExecution
Singlethread,pipelinedarchitecture
Atanygiventime(clockcycle)
oneinstructionbeingfetched
anotherbeingdecoded
anotherbeingexecuted

PipeliningInstructions

Fetch:Instructionfetchedfrommemory
Decode:Decodingofregistersusedininstruction
Execute:RegistersreadfromRegisterBank,shiftandALU
operationoccur,writeregistersbacktoregisterbank
PCalwayscontainstheaddressoftheinstructioncurrently
beingfetched(2instructionspastwhatiscurrentlybeing
executed).Duringpipelining,thepcincrementstwice
beforeinstructiononeexecutes

ProgrammersModelPipeline
PC

PC4

PC8

PipeliningExample
code

pipeline

Fetch
LDRR1,=0x01
ADDR1,R1,#4
SUBEQR1,R1,#4
SUBR1,R1,#7
ADDMIR1,R1,#10
ADDSR1,R1,#2
ADDEQR1,R1,#3
BDN

Decode

LDRR1,=0x01
ADDR1,R1,#4
SUBEQR1,R1,#4
SUBR1,R1,#7
ADDMIR1,R1,#10
ADDSR1,R1,#2
ADDEQR1,R1,#3
BDN

Execute

LDRR1,=0x01
ADDR1,R1,#4
SUBEQR1,R1,#4
SUBR1,R1,#7
ADDMIR1,R1,#10
ADDSR1,R1,#2
ADDEQR1,R1,#3
BDN

NumberRepresentation
Hexrepresentedwithprefix0x
Ex.0x0FC1AB22

Binaryrepresentedwithsuffixy
Ex.11010010y

Decimalrequiresnoprefixorsuffix.

13

ClosedBrackets
Closedbrackets,[],treatwhattheycontain
asanaddress.
Ex.Accessdatastoredatmemory
LDRr1,=dataLoc

;loadthe32bitaddressinr1

LDRr2,[r1] ;r1containsanaddress,thisloadsr2withwhatisstoredattheaddress

14

ProgramStatusRegisterFormat
Formatoftheprogramstatusregisters

I/Fbit:
Activelowinterruptset

Tbit:
Setto1ifTHUMBmode(uses16bitinstructions)

ConditionalExecution
Mostinstructionsetsonlyallowbranches
tobetakenconditionally.
ALLARMinstructionshaveaconditionfield
thatdetermineswhetherornottheinstruction
wouldbeexecuted.
Instructionsthatarenotexecutedtakeuponly
1cycle couldbeanadvantageforlongcode.
Frequentlylessoverheadthantheusualbranch
orsubroutinejump.
Ex.ADDEQr0,r2,r5;ifZflag=1,r0=r2+r5
16

LoadandStoreInstructionFormat
31st bitrepresentsNflag,30th bitrepresentsZflag,29th bit
representsCflag,28th bitistheVflag
I,P,U,Wbitsdistinguishbetweendifferenttypesofaddressing
modes.Wontgettoospecificbutindicateswhetherimmediateor
nonimmediateuseofanoperand
L:distinguishesbetweenaload(L=1),orstore(L=0)
B:distinguishesbetweenanunsignedbyte(B=1)andaword(B=0)
Rn:specifiesthebaseregisterusedbyaddressing_mode (R0R15)
Rd:specifiestheregisterwhosecontentsaretobeloaded/stored

Operands

Operandsarethevariablespassedtotheinstruction.
Inmanyinstructions,suchasdataprocessing
instructions,instructionsperformaspecificoperationon
oneortwooperands.
Operand1isalwaysaregister.
Operand2issenttotheALUbybarrelshifter

SecondOperand
Shiftedregister
Amounttoshiftiscontainedin5bitinstructionfield
Nooverhead,shiftisdonefreeinonecycle

ShiftisstoredinbottombyteofanonregisterPC
TakesextracyclebecauseARMonlyhas2readports

BarrelShifter

BigVs.LittleEndian
BigEndian:Storesmostsignificantbyteofdataatlower
memoryaddress
LittleEndian:Storesmostsignificantbyteofdataat
highermemoryaddress
MostARMprocessorsarebiendian,canbeconfiguredto
handleboth
Ex:Store16bitnumber0x03E8atlocations0x2000.0850and
0x2000.0851
BigEndian

LittleEndian

Address

Data

Address

Data

0x2000.0850

0x03

0x2000.0850

0xE8

0x2000.0851

0xE8

0x2000.0851

0x03