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ContohVHDL PartI II Tugas

The document describes designing various digital logic circuits using VHDL such as basic logic gates, half adder, full adder, 4-bit adder, BCD adder, and mode control 4-bit adder/subtractor. The circuits are designed using both dataflow and structural modeling. Basic gates like AND, OR, NOT etc are designed. Half adder and full adder are designed using dataflow and structural modeling by using half adder as a component. A 4-bit adder is designed using full adder as a component. BCD adder adds two 4-bit BCD numbers. A mode control 4-bit adder/subtractor allows addition or subtraction based on a mode control

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46 views55 pages

ContohVHDL PartI II Tugas

The document describes designing various digital logic circuits using VHDL such as basic logic gates, half adder, full adder, 4-bit adder, BCD adder, and mode control 4-bit adder/subtractor. The circuits are designed using both dataflow and structural modeling. Basic gates like AND, OR, NOT etc are designed. Half adder and full adder are designed using dataflow and structural modeling by using half adder as a component. A 4-bit adder is designed using full adder as a component. BCD adder adds two 4-bit BCD numbers. A mode control 4-bit adder/subtractor allows addition or subtraction based on a mode control

Uploaded by

Luthfiyah13
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 55

Part - I

======
1. Design basic gates (AND,OR, NOT, XOR, XNOR, NAND, NOR) using VHDL.

AND

OR

NOT

NAND

NOR

XOR

XNOR

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity GATES is
Port ( G1 : in std_logic;
G2 : in std_logic;
N1 : out std_logic;
A1 : out std_logic;
O1 : out std_logic;
X1 : out std_logic;
NA1 : out std_logic;
NO1 : out std_logic;
XN1 : out std_logic);
end GATES;
architecture Behavioral of GATES is
begin
N1 <= NOT G1;
A1 <= G1 AND G2;
O1 <= G1 OR G2;
X1 <= G1 XOR G2;
NA1 <= G1 NAND G2;
NO1 <= G1 NOR G2;
XN1 <= G1 XNOR G2;
end Behavioral;

2. (a) Design a Half Adder using dataflow modeling with VHDL.

S= X Y
C= X.Y

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity HALF_ADDER is
Port ( HA1 : in std_logic;
HA2 : in std_logic;
HA_SUM : out std_logic;
HA_CAR : out std_logic);
end HALF_ADDER;
architecture Behavioral of HALF_ADDER is
begin
HA_SUM <= HA1 XOR HA2;
HA_CAR <= HA1 AND HA2;
end Behavioral;

2. (b) Design a Half Adder using structural modeling

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity HALF_ADDER_COMP is
Port(HA1 : in std_logic;
HA2 : in std_logic;
HA_SUM : out std_logic;
HA_CRY : out std_logic);
end HALF_ADDER_COMP;
architecture Behavioral of HALF_ADDER_COMP is
component XOR_TWO is
Port ( X : in std_logic;
Y : in std_logic;
Z : out std_logic);
end component XOR_TWO;
component AND_TWO is
Port( A : in std_logic;
B : in std_logic;
C : out std_logic);
end component AND_TWO;
begin
LB1 : XOR_TWO PORT MAP(HA1,HA2,HA_SUM);
LB2 : AND_TWO PORT MAP(HA1,HA2,HA_CRY);
end Behavioral;

3. (a) Design a Full adder using dataflow modeling.

D= X Y Z
C= X.Y+Z(X Y)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FULL_ADDER_DATA is
Port ( FA1 : in std_logic;
FA2 : in std_logic;
FA3 : in std_logic;
FA_SUM : out std_logic;
FA_CAR : out std_logic);
end FULL_ADDER_DATA;
architecture Behavioral of FULL_ADDER_DATA is
begin
FA_SUM <= FA1 XOR FA2 XOR FA3;
FA_CAR <= (FA1 AND FA2) OR (FA2 AND FA3) OR(FA1 AND FA3);
end Behavioral;

3. (b) Design a Full adder using the macro of Half adder.

10

X
C

HA
Y

HA
S

D= X Y Z
C= X.Y+Z(X Y)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FULL_ADDER_COMP is
Port ( FA1 : in std_logic;
FA2 : in std_logic;
FA3 : in std_logic;
FA_SUM : out std_logic;
FA_CAR : out std_logic);
end FULL_ADDER_COMP;

11

architecture Behavioral of FULL_ADDER_COMP is


component HALF_ADDER is
Port ( HA1 : in std_logic;
HA2 : in std_logic;
HA_SUM : out std_logic;
HA_CAR : out std_logic);
end component HALF_ADDER;
signal T1,T2,T3,SUM : std_logic;
begin
F1: HALF_ADDER port map(FA1,FA2,T1,T2);
F2:
HALF_ADDER port map(T1,FA3,SUM,T3);
FA_CAR <= (T2 OR T3);
FA_SUM <= SUM;
end Behavioral;

12

4. (a) Design a 4-bit adder circuit using the macro of Full adder.

13

Cout C3 C2 C1 Cin
A3 A2 A1 A0
B3 B2 B1 B0
S3

S2 S1 S0

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FULL_ADDER_4BIT is
Port(Ain : in std_logic_vector(3 downto 0);
Bin : in std_logic_vector(3 downto 0);
Cary_in : in std_logic;
Cout : out std_logic_vector(3 downto 0);
Cary_out : out std_logic);
end FULL_ADDER_4BIT;
architecture Behavioral of FULL_ADDER_4BIT is
component FULL_ADDER_COMP is
Port( FA1 : in std_logic;
FA2 : in std_logic;
FA3 : in std_logic;
FA_SUM : out std_logic;
FA_CAR : out std_logic);

14

end component FULL_ADDER_COMP;


signal T : std_logic_vector(4 downto 0);
begin
T(0) <= Cary_in;
FA4B_1: FULL_ADDER_COMP PORT MAP(Ain(0),Bin(0),T(0),Cout(0),T(1));
FA4B_2: FULL_ADDER_COMP PORT MAP(Ain(1),Bin(1),T(1),Cout(1),T(2));
FA4B_3: FULL_ADDER_COMP PORT MAP(Ain(2),Bin(2),T(2),Cout(2),T(3));
FA4B_4: FULL_ADDER_COMP PORT MAP(Ain(3),Bin(3),T(3),Cout(3),T(4));
Cary_out <= T(4);
end Behavioral;

15

4. (b) Design a 4-bit adder circuit using carry look-ahead adder circuit.

carry propagate: Pi = Ai XOR Bi


carry generate: Gi = AiBi
sum: Si = Pi XOR Ci
carry: Ci+1 = Gi+PiCi

16

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CARRY_LOOK_AHEAD_ADDER_4BIT is
port( CAin1 : in std_logic_vector(3 downto 0);
CAin2 : in std_logic_vector(3 downto 0);
CAcarryin : in std_logic;
CAsum : out std_logic_vector(3 downto 0);
CAcarry : out std_logic);
End entity CARRY_LOOK_AHEAD_ADDER_4BIT;
Architecture CLA_ADDER OF CARRY_LOOK_AHEAD_ADDER_4BIT is
Begin
process(CAin1,CAin2,CAcarryin)
variable P,G : std_logic_vector(4 downto 1);
variable C : std_logic_vector(4 downto 0);
begin
C(0) := CAcarryin;
for I in 1 to 4 loop
G(I) := (CAin1(I-1) AND CAin2(I-1));
P(I) := (CAin1(I-1) XOR CAin2(I-1));
C(I) := G(I) OR (P(I) AND C(I-1));
End loop;
for I in 0 to 3 loop
CAsum(I) <= P(I+1) xor C(I);
End loop;
CAcarry <= C(4);
end process;
End CLA_ADDER;

17

5. (a) Design a Half Subtractor using data flow modeling.

18

D= X Y
C= A.B

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity half_subtractor is
Port(HS1 : in std_logic;
HS2 : in std_logic;
HS_SUB : out std_logic;
HS_BOR : out std_logic);
end half_subtractor;

19

architecture Behavioral of half_subtractor is


begin
HS_SUB <= HS1 XOR HS2;
HS_BOR <= (NOT HS1) AND HS2;
end Behavioral;

20

5. (b)
Deisgn a full subtractor using a 3:8 Decoder circuit and OR gates.

21

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FULL_SUBTRACTOR_38DECODER is
Port(FS1 : in std_logic;
FS2 : in std_logic;
FS3 : in std_logic;
FS_SUB : out std_logic;
FS_BOR : out std_logic);
end FULL_SUBTRACTOR_38DECODER;
architecture Behavioral of FULL_SUBTRACTOR_38DECODER is
component DECODER_38 is
Port( S : in std_logic_vector(2 downto 0);
D : out std_logic_vector(7 downto 0);
en : in std_logic );
end component DECODER_38;
signal T : std_logic_vector(7 downto 0);
signal Temp : std_logic_vector(2 downto 0);
begin
Temp <= FS1 & FS2 & FS3;
DE1 : DECODER_38 PORT MAP(Temp,T,'1');
FS_SUB <= T(1) or T(2) or T(4) or T(7);
FS_BOR <= T(1) or T(2) or T(3) or T(7);
end Behavioral;

22

6. Design a BCD adder circuit using VHDL.

23

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BCD_ADDER is
Port( BCD1 : in std_logic_vector(3 downto 0);
BCD2 : in std_logic_vector(3 downto 0);
BCD_CIN : in std_logic;
BCD_SUM : out std_logic_vector(3 downto 0);
BCD_COUT : out std_logic);
end BCD_ADDER;
architecture Behavioral of BCD_ADDER is
component FULL_ADDER_COMP is
Port( FA1 : in std_logic;
FA2 : in std_logic;
FA3 : in std_logic;
FA_SUM : out std_logic;
FA_CAR : out std_logic);
end component FULL_ADDER_COMP;
signal TS : std_logic_vector(3 downto 1);
signal C : std_logic_vector(6 downto 0);
signal T : std_logic_vector(2 downto 0);
signal Cin : std_logic;
24

begin
C(0) <= BCD_CIN;
Cin <= '0';
B1: FULL_ADDER_COMP port map(BCD1(0), BCD2(0), C(0), BCD_SUM(0),
C(1));
B2: FULL_ADDER_COMP port map(BCD1(1), BCD2(1),C(1),TS(1),C(2));
B3: FULL_ADDER_COMP port map(BCD1(2), BCD2(2),C(2),TS(2),C(3));
B4: FULL_ADDER_COMP port map(BCD1(3), BCD2(3),C(3),TS(3),C(4));
T(0) <= TS(3) and TS(2);
T(1) <= TS(3) and TS(1);
T(2) <= C(4) or T(0) or T(1);
B5: FULL_ADDER_COMP port map(TS(1),T(2),Cin,BCD_SUM(1),C(5));
B6: FULL_ADDER_COMP port map(TS(2),T(2),C(5),BCD_SUM(2),C(6));
BCD_SUM(3) <= TS(3) xor C(6);
BCD_COUT <= T(2);
end Behavioral;

25

Part- II
=====
1. Design a 4-bit adder using generate statement.

Cout C3 C2 C1 Cin
A3 A2 A1 A0
B3 B2 B1 B0
S3

S 2 S1 S 0

26

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
menyediakan penambahan definisi
Jenis didefinisikan meliputi: std_ulogic_vector std_ulogic
std_logic_vector std_logic
use IEEE.STD_LOGIC_ARITH.ALL;
menyediakan komputasi numeric
use IEEE.STD_LOGIC_UNSIGNED.ALL;
memberikan perhitungan numerik unsigned
pada jenis std_logic_vector
entity FULLADDER_4BIT_GENERATE is
Port ( FAIN_A : in std_logic_vector(3 downto 0);
FAIN_B : in std_logic_vector(3 downto 0);
FAIN_C : in std_logic;
FA_SM : out std_logic_vector(3 downto 0);
FA_CY : out std_logic);
end FULLADDER_4BIT_GENERATE;
architecture Behavioral of FULLADDER_4BIT_GENERATE is
component FULL_ADDER_COMP is
Port ( FA1 : in std_logic;
FA2 : in std_logic;
FA3 : in std_logic;
FA_SUM : out std_logic;
FA_CAR : out std_logic);
end component FULL_ADDER_COMP;
signal C : std_logic_vector(4 downto 0);
begin
C(0) <= FAIN_C;
GK: for k in 3 downto 0 generate
U1: FULL_ADDER_COMP PORT MAP (FAIN_A(K), FAIN_B(K),
C(K), FA_SM(K), C(K+1));
end generate gk;
FA_CY <= C(4);
end Behavioral;

27

2. Design a mode-control 4-bit adder/subtractor circuit.

28

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
menyediakan penambahan definisi
Jenis didefinisikan meliputi: std_ulogic_vector std_ulogic
std_logic_vector std_logic
use IEEE.STD_LOGIC_ARITH.ALL;
menyediakan komputasi numeric
use IEEE.STD_LOGIC_UNSIGNED.ALL;
memberikan perhitungan numerik unsigned
pada jenis std_logic_vector
entity FULL_ADDER_4_MODE is
Port ( FAIN_A : in std_logic_vector(3 downto 0);
Ketika digunakan dalam array, downto . berarti bahwa. Jadi di L downto R, L
sesuai dengan Most Significant Bit (MSB) dan R ke Least Significant Bit (LSB).
untuk sesuai dengan big endian. Jadi dalam L untuk R, L adalah LSB dan R MSB.
FAIN_B : in std_logic_vector(3 downto 0);
FA_MODE : in std_logic;
FA_SUM : out std_logic_vector(3 downto 0);
FA_CAR : out std_logic;
FA_V : out std_logic);
end FULL_ADDER_4_MODE;
menjelaskan tentang port in dan port out yang digunakan pada full adder.
architecture Behavioral of FULL_ADDER_4_MODE is
component FULL_ADDER_COMP is
Port ( FA1 : in std_logic;
29

FA2 : in std_logic;
FA3 : in std_logic;
FA_SUM : out std_logic;
FA_CAR : out std_logic);
end component FULL_ADDER_COMP;
signal carry : std_logic_vector(4 downto 0);
signal ModeB : std_logic_vector(3 downto 0);
begin
ModeB(0) <=
ModeB(1) <=
ModeB(2) <=
ModeB(3) <=

FAIN_B(0) xor FA_MODE;


FAIN_B(1) xor FA_MODE;
FAIN_B(2) xor FA_MODE;
FAIN_B(3) xor FA_MODE;

carry(0) <= FA_MODE;


FA4M_1: FULL_ADDER_COMP PORT MAP(FAIN_A(0), ModeB(0), carry(0),
FA_SUM(0), carry(1));
FA4M_2: FULL_ADDER_COMP PORT MAP(FAIN_A(1), ModeB(1), carry(1),
FA_SUM(1), carry(2));
FA4M_3: FULL_ADDER_COMP PORT MAP(FAIN_A(2), ModeB(2), carry(2),
FA_SUM(2), carry(3));
FA4M_4: FULL_ADDER_COMP PORT MAP(FAIN_A(3), ModeB(3), carry(3),
FA_SUM(3),carry(4));
FA_V <= carry(4) xor carry(3);
FA_CAR <= carry(4);
end Behavioral;

30

3. (a) Design a 4:1 Multiplexer using if_else statement.

31

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity MUX4_1_IF_ELSE is
Port( MUXIN_0,MUXIN_1,MUXIN_2,MUXIN_3 : in std_logic;
MUXSEL : in std_logic_vector(1 downto 0);
MUXOUT : out std_logic);
end MUX4_1_IF_ELSE;
architecture Behavioral of MUX4_1_IF_ELSE is
begin
PROCESS(MUXSEL)
BEGIN
IF MUXSEL = "00" THEN
MUXOUT <= MUXIN_0;
ELSIF MUXSEL = "01" THEN
MUXOUT <= MUXIN_1;
ELSIF MUXSEL = "10" THEN
MUXOUT <= MUXIN_2;
ELSE
MUXOUT <= MUXIN_3;
END IF;
END PROCESS;
end Behavioral;

32

3. (b)
Design a 4:1 Multiplexer using case statement.

33

34

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity MUX4_1_CASE is
Port( MUXIN_0,MUXIN_1,MUXIN_2,MUXIN_3 : in std_logic;
MUXSEL : in std_logic_vector(1 downto 0);
MUXOUT : out std_logic);
end MUX4_1_CASE;
architecture Behavioral of MUX4_1_CASE is
begin
PROCESS(MUXSEL)
BEGIN
CASE MUXSEL IS
WHEN "00" => MUXOUT <= MUXIN_0;
WHEN "01" => MUXOUT <= MUXIN_1;
WHEN "10" => MUXOUT <= MUXIN_2;
WHEN OTHERS => MUXOUT <= MUXIN_3;
END CASE;
END PROCESS;
end Behavioral;

35

4. (a) Design a 2:4 Decoder using behavioral modeling.

36

37

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DECODER2_4 is
Port ( SE : in std_logic_vector(1 downto 0);
DE : out std_logic_vector(3 downto 0));
end DECODER2_4;
architecture Behavioral of DECODER2_4 is
signal TE : std_logic_vector(3 downto 0);
begin
TE <= "0001" when SE = "00" else
"0010" when SE = "01" else
"0100" when SE = "10" else
"1000" when SE = "11";
DE <= TE;
end Behavioral;

38

4. (b) Design a 3:8 Decoder using behavioral modeling.

39

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DECODER_38 is
Port(S : in std_logic_vector(2 downto 0);
D : out std_logic_vector(7 downto 0);
en : in std_logic );
end DECODER_38;
architecture Behavioral of DECODER_38 is
begin
------------------process 1--------------process(en,S)
begin
if en ='1' then
case s is
when "000" =>D<="00000001";
when "001" =>D<="00000010";
when "010" =>D<="00000100";
when "011" =>D<="00001000";
when "100" =>D<="00010000";
when "101" =>D<="00100000";
when "110" =>D<="01000000";
when "111" =>D<="10000000";
when others => null;
end case;
else
d<=(others =>'0');
end if;
end process;
--------------------------------------end Behavioral;

40

4. (c) Design a 5:32 decoder using the macro of above two design.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DECODER5_32_COMP2_4_3_8 is
port( SEL : in std_logic_vector(4 downto 0);
DEC : out std_logic_vector(31 downto 0));
end DECODER5_32_COMP2_4_3_8;
architecture Behavioral of DECODER5_32_COMP2_4_3_8 is
component DECODER2_4 is
Port( SE : in std_logic_vector(1 downto 0);
DE : out std_logic_vector(3 downto 0));
end component DECODER2_4;
component DECODER_38 is
Port( S : in std_logic_vector(2 downto 0);
D : out std_logic_vector(7 downto 0);
en : in std_logic );
end component DECODER_38;
signal EN_DE : std_logic_vector(3 downto 0);
signal T : std_logic_vector(31 downto 0);
begin
D1 : DECODER2_4 PORT MAP(SEL(4 downto 3),EN_DE);
D2 : DECODER_38 PORT MAP(SEL(2 downto 0),T(7 downto 0),
EN_DE(0));
D3 : DECODER_38 PORT MAP(SEL(2 downto 0),T(15 downto 8),
EN_DE(1));
D4 : DECODER_38 PORT MAP(SEL(2 downto 0),T(23 downto 16),
EN_DE(2));
D5 : DECODER_38 PORT MAP(SEL(2 downto 0),T(31 downto 24),
EN_DE(3));
DEC <= T;
end Behavioral;

41

5. Design 4:2 binary encoder using VHDL.


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ENCODER4_2 is
Port( ENin : in std_logic_vector(3 downto 0);
ENout : out std_logic_vector(1 downto 0));
end ENCODER4_2;
architecture Behavioral of ENCODER4_2 is
begin
process(ENin)
begin
case ENin is
when "0001" => ENout <= "00";
when "0010" => ENout <= "01";
when "0100" => ENout <= "10";
when "1000" => ENout <= "11";
when others => NULL;
end case;
end process;
end Behavioral;

42

43

6. Design a Even-parity generator and cheker circuit.

44

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity PARITY_CHECKER_GENERATOR_8BIT is
Port(
Pin : in std_logic_vector(7 downto 0);
Pcheck : out std_logic;
Pgenerate : out std_logic);
end PARITY_CHECKER_GENERATOR_8BIT;
architecture Behavioral of PARITY_CHECKER_GENERATOR_8BIT is
signal T : std_logic_vector(7 downto 0);
begin
T(0) <= Pin(0) XOR Pin(1);
T(1) <= Pin(2) XOR Pin(3);
T(2) <= Pin(4) XOR Pin(5);
T(3) <= Pin(6) XOR Pin(7);
T(4) <= T(0) XOR T(1);
T(5) <= T(2) XOR T(3);
T(6) <= T(4) XOR T(5);
T(7) <= NOT T(6);
Pcheck <= T(7);
Pgenerate <= T(6);
end Behavioral;

45

7. Design a 4-bit by 3-bit binary multiplier circuit using the macro of 4-bit adder
and AND gates.

46

library
IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Mutiplier4_3 is
port( B : in std_logic_vector(3 downto 0);
A : in std_logic_vector(2 downto 0);
O : out std_logic_vector(6 downto 0));
end Mutiplier4_3;
architecture Behavioral of Mutiplier4_3 is
component FULL_ADDER_4BIT is
Port( Ain : in std_logic_vector(3 downto 0);
Bin : in std_logic_vector(3 downto 0);
Cary_in : in std_logic;
Cout : out std_logic_vector(3 downto 0);
Cary_out : out std_logic);
end component FULL_ADDER_4BIT;
signal C : std_logic;
signal T : std_logic_vector(11 downto 0);
signal A1,B1,C1,D1,E1 : std_logic_vector(3 downto 0);

47

begin
T(0) <= A(0) and B(0);
T(1) <= A(0) and B(1);
T(2) <= A(0) and B(2);
T(3) <= A(0) and B(3);
T(4) <= A(1) and B(0);
T(5) <= A(1) and B(1);
T(6) <= A(1) and B(2);
T(7) <= A(1) and B(3);
T(8) <= A(2) and B(0);
T(9) <= A(2) and B(1);
T(10) <= A(2) and B(2);
T(11) <= A(2) and B(3);
A1 <= '0' & T(3) & T(2) & T(1);
B1 <= T(7) & T(6) & T(5) & T(4);
C1 <= T(11) & T(10) & T(9) & T(8);
O(0) <= T(0);
FA4_1 : FULL_ADDER_4BIT PORT MAP(A1,B1,'0',D1,C);
O(1) <= D1(0);
E1 <= C & D1(3 downto 1);
FA4_2 : FULL_ADDER_4BIT PORT MAP(E1,C1,'0',O(5 downto
2),O(6));
end Behavioral;

48

8. Design a single bit comparator cirucit using VHDL.


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity COMPARATOR_1BIT is
Port ( A, B : in std_logic;
X : out std_logic; -- A > B
Y : out std_logic; -- A < B
Z : out std_logic; -- A = B
EN : in std_logic);
end COMPARATOR_1BIT;
architecture Behavioral of COMPARATOR_1BIT is
begin
PROCESS(A,B,EN)
BEGIN
If (EN = '1') then
If (A > B) then
X <= '1'; Y <= '0'; Z <= '0';
elsif(A < B) then
X <= '0'; Y <= '1'; Z <= '0';
else
X <= '0'; Y <= '0'; Z <= '1';
end if;
else
X <= '0'; Y <= '0'; Z <= '0';
end if;
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END PROCESS;
end Behavioral;

50

9. (a) Design a 4-bit comparator using the macro of single bit comparator.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity COMPARATOR_4BIT_COMP is
Port ( P, Q : in std_logic_vector(3 downto 0);
M : out std_logic; -- P > Q
N : out std_logic; -- P < Q
O : out std_logic; -- P = Q
EN : in std_logic);
end COMPARATOR_4BIT_COMP;
architecture Behavioral of COMPARATOR_4BIT_COMP is
component COMPARATOR_1BIT is
Port ( A, B : in std_logic;
X : out std_logic; -- A > B
Y : out std_logic; -- A < B
Z : out std_logic; -- A = B
EN : in std_logic);
end component COMPARATOR_1BIT;
signal T : std_logic_vector(11 downto 0);
constant enable : std_logic := '1';
begin
c1: COMPARATOR_1BIT port map(P(3),Q(3),T(0),T(1),T(2),enable);
c2: COMPARATOR_1BIT port map(P(2),Q(2),T(3),T(4),T(5),T(2));
c3: COMPARATOR_1BIT port map(P(1),Q(1),T(6),T(7),T(8),T(5));
c4: COMPARATOR_1BIT port map(P(0),Q(0),T(9),T(10),T(11),T(8));
M <= T(0) OR T(3) OR T(6) OR T(9);
N <= T(1) OR T(4) OR T(7) OR T(10);
O <= T(11);

51

end Behavioral;

52

9. (b) Design a 4-bit comparator using the boolean function.


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity COMPARATOR_4BIT_BOOLEAN is
Port ( P, Q : in std_logic_vector(3 downto 0);
M : out std_logic; -- P > Q
N : out std_logic; -- P < Q
O : out std_logic; -- P = Q
EN : in std_logic);
end COMPARATOR_4BIT_BOOLEAN;
architecture Behavioral of COMPARATOR_4BIT_BOOLEAN is
begin
process(P,Q,EN)
begin
if(EN = '1')then
if(P > Q) then
M <= '1';
N <= '0';
O <= '0';
elsif(P < Q) then
M <= '0';
N <= '1';
O <= '0';
else
M <= '0';
N <= '0';
O <= '1';
end if;
else
M <= '0';
N <= '0';
O <= '0';
end if;
end process;
end Behavioral;

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