10/12/2016
DesignForTest:DFTQ&Apart1
0
More NextBlog
CreateBlog SignIn
DesignForTest
Wednesday,September11,2013
SearchThisBlog
DFTQ&Apart1
Search
1.WhatissequentialDepthInDFT?Howdoesitimprovecoverage?
Ans:FastScanperformsclocksequentialtestgenerationifyouspecifyanonzerosequential
depth.
Clocksequentialidentificationselectsscannablecellsbycuttingsequentialloopsandlimiting
sequentialdepthbasedontheDepthswitch.Typically,thismethodisusedtocreatestructured
partialscandesignsthatcanusetheFastScanclocksequentialATPGalgorithm.
SettingtheSequentialswitchtoeither0(thedefault)or1resultsinpatternswitha
Labels
DFTQ&A(29)
+5 Recommend this on Google
PopularPosts
DFTQ&APart19
maximumsequentialdepthofone,butFastScancreatesclocksequentialpatternsonlyifthe
settingis1orhigher.
Themaximumallowablesequentialdepthis255(atypicaldepthwouldrangefrom
2to5).
DFTQ&Apart1
CoverageImprovement:
DFTQ&APart2
TestablefaultsbecomeATPG_untestablefaultsbecauseofconstraints,orlimitations,
placedontheATPGtool(suchasapinconstraintoraninsufficientsequentialdepth).
Thesefaultsmaybepossibledetectable,ordetectable,ifyouremovesomeconstraint,orchange
somelimitation,onthetestgenerator(suchasremovingapinconstraintorchangingthe
sequentialdepth).
Also,(whileusingnamedcaptureprocedure)graduallyaddmorecaptureprocedureswithhigher
sequentialdepthuntilthetestcoveragegoalisachievedorthepatterncountlimitisreached.
2.Whatisthedifferencebetweenflopsandscanflops?
DFTQ&APart26
DFTQ&APart25
FollowbyEmail
Emailaddress...
Submit
Archives
2010(6)
2013(53)
Ans:Differencebetweenscanflopandsimpleflopsbecomesmoreeasytounderstandwhenwe
knowwhydoweneedscanflop!!
Needofscanflop:
Thegoalofscandesignistomakeadifficulttotestsequentialcircuitbehave(duringthetesting
process)likeaneasiertotestcombinationalcircuit.Achievingthisgoalinvolvesreplacing
sequentialelementswithscannablesequentialelements(scancells/scanflops)andthenstitching
thescancellstogetherintoscanregisters,orscanchains.Youcanthenusetheseserially
connectedscancellstoshiftdatainandoutwhenthedesignisinscanmode.
September(29)
DFTQ&Apart1
DFTQ&APart2
DFTQ&APart3
DFTQ&APart4
DFTQ&APart5
DFTQ&APart6
DFTQ&APart7
DFTQ&APart8
BeforeScandesignisdifficulttoinitializetoaknownstate,makingitdifficulttobothcontrolthe
internalcircuitryandobserveitsbehaviorusingtheprimaryinputsandoutputsofthedesign.Ina
"Scandesign"scanmemoryelements(scanflops)replacetheoriginalmemoryelements(normal
flops)impartingcontrollabilityandobservabilitytothedesign(primerequirementforthedesign
beingtestable),whenshiftingisenabled.
3.Whatisrobust/non_robusttestforpathdelayfaults?
Ans:NonRobusttests:
DFTQ&APart9
DFTQ&APart10
DFTQ&APart11
DFTQ&APart12
DFTQ&APart13
DFTQ&APart14
DFTQ&APart15
DFTQ&APart16
Apairofatspeedvectorsthattestapathdelayfaultfaultdetectionisnotguaranteed,becauseit
dependsonotherdelaysinthecircuit.
DFTQ&APart17
RobustTests:
DFTQ&APart19
Apairofatspeedvectorsthattestapathdelayfaultindependentofotherdelaysordelayfaultsin
http://vlsidoubts.blogspot.in/2013/09/dftqpart1.html#gsc.tab=0
DFTQ&APart18
DFTQ&APart20
1/3
10/12/2016
DesignForTest:DFTQ&Apart1
thecircuit.
DFTQ&APart21
4.Whatarethetechniquesusedtoreducepatterncountwithoutlosingcoverage?
DFTQ&APart22
DFTQ&APart23
Ans:Thenumberoftestpatternsthatyouneedtoachievefullcoveragedependsonthedesign
size.DifferentATPGtoolsofferdifferentcompressionandpatternorderingtechniquestohelp
reducepatterncount.
DFTQ&APart24
faultmodelsbeyondstuckattypicallyrequirepatterncountsthataremuchlargerthanthosefor
stuckatonly.
DFTQ&APart27
ForPatternreduction,firststepisthechainbalancingduringStitchingorscaninsertion.Ifyour
chainsarebalanced,Toolneedstoinsertlessdummypatternsforreachingtillrequiredflop.
DFTQ&APart25
DFTQ&APart26
DFTQ&APart28
DFTQ&APart29
October(2)
December(22)
Alsowecanincludecompressiononthechainswherewehaveconstraintsonthepinsof
device.Thismeansifwearehavingthecompressionfactorof2thenyour1scanchainwillget
dividedinto2insidethedevicereducingyourchainlength(flopsperscanchain).
5.Arethefaultsontheresetsoftheflopsaredetected?ifsohowaretheydetected?
Followers
Followers(56)Next
Ans:Yesthefaultsonresetofthefloparedetectable.Itisdetectedinthefollowingway
1)Definetheresetpinasclockinthetdl
2)Letusassumethattheresetoftheflopisactivelow.Keeptheresetas'high'andscanin'1'in
totheflop(duringthisscanenableis'high')
3)Aswehavescanin'1'theQoftheflopwillhave'1'
Follow
4)Makethescanenable'low'andtogglethereset(i.e.makeitlow).Thisisallowedbecausewe
havedeclaredtheresetasclock.
TotalPageviews
5)Asresetis'low'theflopneedtogetresetandwhateverthevalueintheflopwillbecome'0'
1 6 5 2 2 7
6)Thenstrobefor'0',whileshiftingoutthecontentsfromtheflop.
7)Iftheoutputwhileshiftingoutis'0',itmeanstheresetpinoftheflopisnotstuckat1.
Otherwiseitisstuckat'1'.
vlsi
doubts.blogspot.in
Search
byYakkalaSrikanth
Search
Note:
1.Intestmodealltheflopsshouldhaveaasynchronousreset.
JavaAssist
2.TheresetpinsofallflopsshouldbecontrollablefromTop(Chip)level.
Ifyourdesigncontainsalotofsynchronousresetflops.ThensinceduringAC(transdly)testing
theseresetlinefaultsarenottargetedforAC,Constrainingtheresettooffstateisthebestway.
MethodCallduringPolymorphism
Passinganarraytoamethod
instanceof
HashMapVsHashtable
PostedbySreeatWednesday,September11,2013
<! Place this tag in your head or just before your close body tag > (1)
Reactions:
Recommend this on Google
Linkstothispost
CreateaLink
NewerPost
Home
OlderPost
Didyoufindthisposthelpful
Yes
0(0%)
No
0(0%)
Canbebetter
0(0%)
Votessofar:0
Pollclosed
Simpletemplate.PoweredbyBlogger.
http://vlsidoubts.blogspot.in/2013/09/dftqpart1.html#gsc.tab=0
2/3
10/12/2016
http://vlsidoubts.blogspot.in/2013/09/dftqpart1.html#gsc.tab=0
DesignForTest:DFTQ&Apart1
3/3
