Chapter 10
Boundary Scan and
Core-Based Testing
VLSIEE141
Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 1
Outline
Introduction
Digital
Boundary Scan (1149.1)
Boundary Scan for Advanced Networks
(1149.6)
Embedded Core Test Standard (1500)
Comparison between 1149.1 and 1500
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 2
Boundary Scan
Original
objective: board-level digital testing
Now also apply to:
MCM and FPGA
Analog circuits and high-speed networks
Verification, debugging, clock control, power
management, chip reconfiguration, etc.
History:
Mid-1980: JETAG
1988: JTAG
1990: First boundary scan standard 1149.1
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 3
Boundary Scan Family
No.
Main target
1149.1 Digital chips and interconnects
among chips
1149.2 Extended digital serial interface
Status
Std. 1149.1-2001
Discontinue
1149.3 Direct access testability interface Discontinue
1149.4 Mixed-signal test bus
Std. 1149.4-1999
1149.5 Standard module test and
maintenance (MTM) bus
Std. 1149.5-1995
(not endorsed by
IEEE since 2003)
Std. 1149.6-2003
1149.6 High-speed network interface
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 4
Core-Based SOC Design
ADC
RAM
RAM
ROM
GLUE LOGIC
PLL
DAC
BUS &
INTERCONNECT
DSP
CPU
IP 1
ASIC 1
IP 2
ASIC
2
RAM
DSP
ALU
ASIC
ROM
ASIC
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 5
Digital Boundary Scan 1149.1
Basic
concepts
Overall test architecture & operations
Hardware components
Instruction register & instruction set
Boundary scan description language
On-chip test support
Board/system-level control architectures
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 6
Basic Idea of Boundary Scan
Boundary-scan cell
Internal
Logic
VLSIEE141
Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 7
A Board Containing 4 ICs with
Boundary Scan
Boundary-scan cell
Boundary-scan chain
Serial
Data in
Serial
Data out
Internal
Logic
Internal
Logic
Internal
Logic
Internal
Logic
System interconnect
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 8
1149.1 Boundary-Scan Architecture
Internal
Logic
Boundary-Scan Register
(consists of boundary
Scan cells)
1
Internal Registers
Test Data In (TDI)
Bypass Register
Test Data Out (TDO)
Miscellaneous Register
1
Test Mode Select (TMS)
Test Clock (TCK)
Instruction Register
TAP
Controller
1
Test Reset (TRST*) (optional)
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 9
Hardware Components of 1149.1
A test access port (TAP) consisting of :
4 mandatory pins: Test data in (TDI), Test data out (TDO),
Test mode select (TMS), Test clock (TCK), and
1 optional pin: Test reset (TRST)
A test access port controller (TAPC)
An instruction register (IR)
Several test data registers
A boundary scan register (BSR) consisting of boundary
scan cells (BSCs)
A bypass register (BR)
Some optional registers (Device-ID register, designspecified registers such as scan registers, LFSRs for BIST,
etc.)
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 10
Basic Operations
1. Instruction sent (serially) through TDI into
instruction register.
2. Selected test circuitry configured to respond to
the instruction.
3. Test pattern shifted into selected data register
and applied to logic to be tested
4. Test response captured into some data register
5. Captured response shifted out; new test pattern
shifted in simultaneously
6. Steps 3-5 repeated until all test patterns are
applied.
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 11
Boundary-Scan Circuitry in A Chip
Data Register
Design-Spec. Reg.
Device-ID Reg.
TDO
TDI
TRST*
TMS
TCK
Boundary Scan Reg.
T
A
P
M
U
X
0M
U 1D
1 X
EN
Bypass Reg. (1-bit)
T
A
P
C
3
ClockDR, ShiftDR, UpdateDR
Reset*
ClockIR, ShiftIR, UpdateIR
IR decode
Instruction Register
Select
TCK
Enable
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 12
Data registers
Boundary scan register: consists of boundary
scan cells
Bypass register: a one-bit register used to pass
test signal from a chip when it is not involved in
current test operation
Device-ID register: for the loading of product
information (manufacturer, part number, version
number, etc.)
Other user-specified data registers (scan chains,
LFSR for BIST, etc.)
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 13
A Typical Boundary-Scan Cell (BSC)
Operation modes
Normal: IN OUT (Mode = 0)
Shift: TDI ... IN OUT ... TDO (ShiftDR = 1, ClockDR)
Capture: IN R1, OUT driven by IN or R2 (ShiftDR = 0, ClcokDR)
Update: R1 OUT (Mode_Control = 1, UpdateDR)
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 14
TAP Controller
A
finite state machine with 16 states
Input: TCK, TMS
Output: 9 or 10 signals included ClockDR,
UpdateDR, ShiftDR, ClockIR, UpdateIR,
ShiftIR, Select, Enable, TCK and TRST*
(optional).
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 15
State Diagram of TAP Controller
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 16
Main functions of TAP controller
Providing
control signals to
Reset BS circuitry
Load instructions into instruction register
Perform test capture operation
Perform test update operation
Shift test data in and out
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 17
States of TAP Controller
Test-Logic-Reset: normal mode
Run-Test/Idle: wait for internal test such as BIST
Select-DR-Scan: initiate a data-scan sequence
Capture-DR: load test data in parallel
Shift-DR: load test data in series
Exit1-DR: finish phase-1 shifting of data
Pause-DR: temporarily hold the scan operation (e.g.,
allow the bus master to reload data)
Exit2-DR: finish phase-2 shifting of data
Update-DR: parallel load from associated shift registers
Note: Controls for IR are similar to those for DR.
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 18
Instruction Set
BYPASS
Bypass data through a chip
SAMPLE
Sample (capture) test data into BSR
PRELOAD
Shift-in test data and update BSR
EXTEST
Test interconnection between chips of board
Optional
INTEST, RUNBIST, CLAMP, IDCODE, USERCODE,
HIGH-Z, etc.
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Test Principles and Architectures
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Ch. 10 - Boundary Scan and Core-Based Testing - P. 19
Execution of BYPASS Instruction
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 20
Execution of SAMPLE Instruction
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 21
Execution of PRELOAD Instruction
Input
M
U
X
PRELOAD
R1
R2
TDI
M Output
U
X
Internal
Logic
R1
R2
TDO
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 22
Execution of EXTEST Instruction (1/3)
Shift-DR
(Chip1)
Internal
Logic
TDI
Registers
TAP controller
Internal
Logic
TDO TDI
Registers
TDO
TAP controller
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 23
Execution of EXTEST Instruction (2/3)
Update-DR
(Chip1)
Capture-DR (Chip2)
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 24
Execution of EXTEST Instruction (3/3)
Shift-DR
(Chip2)
Internal
Logic
TDI
Registers
TAP controller
Internal
Logic
TDO TDI
Registers
TDO
TAP controller
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 25
Execution of INTEST Instruction (1/4)
Shift-DR
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 26
Execution of INTEST Instruction (2/4)
Update-DR
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 27
Execution of INTEST Instruction (3/4)
Capture-DR
Internal
Logic
TDI
Registers
TDO
TAP controller
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 28
Execution of INTEST Instruction (4/4)
Shift-DR
Internal
Logic
TDI
Registers
TDO
TAP controller
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 29
Boundary Scan Description
Language (BSDL)
Now
a part of IEEE 1149.1-2001
Purposes:
Provide standard description language for BS devices.
Simplify design work for BS automated synthesis is possible.
Promote consistency throughout ASIC designers, device
manufacturers, foundries, test developers and ATE
manufacturers.
Make it easy to incorporation BS into software tools for test
generation, analysis and failure diagnosis.
Reduce possibility of human error when employing boundary
scan in a design.
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Ch. 10 - Boundary Scan and Core-Based Testing - P. 30
Features of BSDL
Describes
the testability features of BS
devices that are compatible with 1149.1.
S subset of VHDL.
System-logic and the 1149.1 elements that
are absolutely mandatory need not be
specified.
Examples: BYPASS register, TAP controller, etc.
Commercial
tools to synthesize BSDL exist.
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Ch. 10 - Boundary Scan and Core-Based Testing - P. 31
Scan and BIST Support with
Boundary Scan
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 32
Bus Master for Chips with
Boundary Scan (1/5)
Ring
architecture with shared TMS
Application chips
Bus master
TDI
TDO
TMS
TCK
VLSIEE141
Test Principles and Architectures
TDI
TCK
TMS
TDO
#1
TDI
TCK
TMS
TDO
#2
TDI
TCK
TMS
TDO
#N
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Ch. 10 - Boundary Scan and Core-Based Testing - P. 33
Bus Master for Chips with
Boundary Scan (2/5)
Ring
architecture with separate TMS
Application chips
Bus master
TDI
TDO
TMS1
TMS2
TDI
TCK
TMS
TDO
#1
TDI
TCK
TMS
TDO
#2
TDI
TCK
TMS
TDO
#N
TMSN
TCK
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Test Principles and Architectures
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Ch. 10 - Boundary Scan and Core-Based Testing - P. 34
Bus Master for Chips with
Boundary Scan (3/5)
Star
architecture
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 35
Bus Master for Chips with
Boundary Scan (4/5)
Multi-drop
architecture
Multi-Drop
Device
Multi-Drop
Device
Multi-Drop
Device
Bus master
TDI
TMS
TCK
TDO
Test Bus
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 36
Bus Master for Chips with
Boundary Scan (5/5)
Hierarchical
architecture
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 37
Boundary scan for advanced networks
1149.6
Rationale
Analog
test receiver
Digital driver logic
Digital receiver logic
Test access port for 1149.6
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 38
Rationale
Advanced
signaling techniques are required
for multiple-mega-per-second I/O.
Differential or AC-coupling networks
Coupling
capacitor in AC-coupled networks
blocks DC signals.
DC-level applied during EXTEST may
decay to undefined logic level.
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 39
Capturing AC-Coupled Signal with 1149.1
C
TX
RX
VT
Update-DR
VH
TX
VL
VH
RX
VL
Capture-DR
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Test Principles and Architectures
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Ch. 10 - Boundary Scan and Core-Based Testing - P. 40
1149.1 Configuration for Differential
Signaling
TX
RX
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 41
Analog Test Receiver Response to AC
and DC-Coupled Signals
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 42
Digital Driver Logic
Mission
0
Shift out
Data
0
1
1
Mode
AC Test Signal
Insertion, per driver
AC Mode
Shift in
ShiftDR
UpdateDR
ClockDR
Train/Pulse
D Q
RTI State
TCK
AC Test Signal
(distributed to all AC
drivers)
Mode
AC Mode Train/Pulse
1149.1 Bypass
1149.1 Extest
Extest_Pulse
Extest_Train
AC Test Signal Generator
(near TAP Controller)
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 43
Digital Receiver Logic
Optional, Required for Observe-and-Control Capabilty on Single-Ended Inputs Only
0
1
Shift Out
Shift In
Boundary
Register
Cell
TCK
1
0
ShiftDR
EXTEST_PULSE
or
EXTEST_TRAIN
Selected
Pad
RF
Capture
FF
ClockDR
Update
FF
UpdateDR
TAP State
Capture-DR
Shift_DR
Init_Memory
Clock_DR
EXTEST_PULSE, EXTEST_TRAIN:
TCK
TAP State
TMS
VHyst
Exit*-DR
Update_DR
Latch Q
Init_Memory
AC
Set
D Hyst
DC
Test
Receiver
EXTEST:
CF
Mem
Clear
May be located near
TAP controller
Capture-DR
EXTEST
VT
VHyst
Init_Memory
(common to all
test receivers)
QQ
SET
CLR
D
D
LG
EXTEST_TRAIN
EXTEST_PULSE
TMS
Exit1-DR
Exit2-DR
TCK
NOTE: The generated clock (Init_Memory) shown is suitable for rising edge-sensitive behavior only.
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Test Principles and Architectures
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Ch. 10 - Boundary Scan and Core-Based Testing - P. 44
Example of Modification on 1149.1 TAP
Driver Behavior During EXTEST_PULSE
Pulse Width
TCK
(TAP State)
Test-Logic Reset
Update-xR
Run-Test/Idle
Select-DR Capture-DR
AC Test Signal
Update Point
AC Pin Driver
Capture Point
Data
Inverted Data
Data
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 45
Embedded Core Test Standard - 1500
SOC
test problems
Overall architecture
Wrapper components and functions
Instruction set
Core test language
Core test supporting and system test
configurations
Hierarchical test control and plug & play
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 46
SOC Test Problems/Requirements (1/2)
Mixing technologies: logic, processor, memory, analog
Need various DFT/BIST/other techniques
Deeply embedded cores
Need Test Access Mechanism
Hierarchical core reuse
Need hierarchical test management
Different core providers and SOC test developers
Need standard for test integration
IP protection/test reuse
Need core test standard/documentation
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 47
SOC Test Problems/Requirements (2/2)
Higher-performance core pins than SOC pins
Need on-chip, at-speed testing
External ATE inefficiency
Need on-chip ATE
Long test application time
Need parallel testing or test scheduling
Test power must be considered
Need lower power design or test scheduling
Testable design automation
Need new testable design tools and flow
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Ch. 10 - Boundary Scan and Core-Based Testing - P. 48
A System Overview of IEEE 1500
Standard
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 49
Test Interface of A Core Wrapper
W rapper
Parallel Control
Optional W rapper
Parallel Port (W PP)
W PC
W rapper
Parallel Input
W rapper
Parallel Output
W PI
W PO
Core
W SI
W rapper
Serial Input
Required W rapper
Serial Port (W SP)
W rapper
W SO
W rapper
Serial Output
W SC
W rapper
Serial Control
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Ch. 10 - Boundary Scan and Core-Based Testing - P. 50
Serial Test Circuitry of 1500 for a Core
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Ch. 10 - Boundary Scan and Core-Based Testing - P. 51
Wrapper Components
Wrapper series port (WSP)
Wrapper series input (WSI), Wrapper series output
(WSO), Wrapper series control (WSC)
Wrapper parallel port (WPP) (optional)
Wrapper parallel input (WPI), Wrapper parallel output
(WPO), wrapper parallel control (WPC)
Wrapper instruction register (WIR)
Wrapper bypass regiester (WBY)
Wrapper data register (WBR)
Consists of wrapper boundary cells (WBCs)
Core data register (CDR) (optional)
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Ch. 10 - Boundary Scan and Core-Based Testing - P. 52
Wrapper Series Control (WSC) signals
WRCK:
wrapper clock terminal
AUXCKn: Optional auxiliary clocks, where n is
the number of the clocks.
WRSTN: wrapper reset
SelectWIR: determine whether WIR is selected
CaptureWR: enable Capture operation
ShiftWR: enable Shift operation
UpdateWR: enable Update operation
TransferDR: enable Transfer operation
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Ch. 10 - Boundary Scan and Core-Based Testing - P. 53
Wrapper Instruction Register
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Wrapper Boundary Register (WBR)
Consists
of Wrapper boundary cells (WBCs)
WBC
Terminals: Cell functional input (CFI), cell
functional output (CFO), cell test input (CTI), cell
test output (CTO)
Functional modes: Normal, inward facing, outward
facing, nonhazardous (safe).
Operation events: Shift, capture, update, transfer,
apply.
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 55
Events of WBR (WBC)
Shift: data advance one-bit forward on WBRs
shift path
Capture: data on CFI or CFO are captured and
stored in WBC
Update: data stored in WBCs shift path storage
are loaded into an off-shift-path storage of the
WBC
Transfer: move data to the storage closest to CTI
or one bit closer to CTO
Apply: a derivative event inferred from other
events to apply data to functional inputs of cores
or functional outputs of WBR
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 56
Four Symbols Used in Bubble Diagrams for
WBCs
Storage
element
Data
path
Decision
point
Data paths
from a source
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 57
Some Typical WBCs Represented by
Bubble Diagrams
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Ch. 10 - Boundary Scan and Core-Based Testing - P. 58
Example 10.1 - WIR Interface of WBY,
WBR WDR(s) and CDR(s)
SelectWIR
WIR_WSO
WBR
WIR Circuitry
{SelectWIR,
WRCK,
WRSTN,
CaptureWR,
ShiftWR,
UpdateWR}
Core_Cntrl
WDR_Cntrl
CDR_Cntrl
DR_Select[n:0]
WBR_Cntrl
WBY_Cntrl
WSO
CDR k
DR_Select[n:0]
WDR k
DR_WSO
WSI
WBY
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Test Principles and Architectures
Ch. 10 - Boundary Scan and Core-Based Testing - P. 59
Example 10.2 - Schematic Diagram of
WBC WC_SD2_CIO
CTI
SHIFT
WRCK
D1
XFER
MODE
CFI
CAPT
CFO
CTO
D2
IO_FACE
WRCK
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Ch. 10 - Boundary Scan and Core-Based Testing - P. 60
WS_BYPASS Instruction
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Ch. 10 - Boundary Scan and Core-Based Testing - P. 61
WS_EXTEST Instruction
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Ch. 10 - Boundary Scan and Core-Based Testing - P. 62
WP_EXTEXT Instruction
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Ch. 10 - Boundary Scan and Core-Based Testing - P. 63
WS_SAFE Instruction
Disabled
FI
Safe
States
W
B
R
Core FO
FI
FO
W
B
R
Safe
States
Bypass
WSI
WSO
WIR
WSC
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Ch. 10 - Boundary Scan and Core-Based Testing - P. 64
WS_PRELOAD Instruction
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Ch. 10 - Boundary Scan and Core-Based Testing - P. 65
WP_PRELOAD Instruction
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Ch. 10 - Boundary Scan and Core-Based Testing - P. 66
WS_CLAMP Instruction
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Ch. 10 - Boundary Scan and Core-Based Testing - P. 67
WS_INTEST Instruction
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Ch. 10 - Boundary Scan and Core-Based Testing - P. 68
WS_INTEST_SCAN Instruction
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Ch. 10 - Boundary Scan and Core-Based Testing - P. 69
General Parallel TAM Structure
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Multiplexed TAM Architectures
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Ch. 10 - Boundary Scan and Core-Based Testing - P. 71
Daisy chained TAM Architecture
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Direct Access TAM Architectures
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Local Controller TAM Architectures
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Core Access Switch (CAS) Architecture
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Different Functional Modes of CAS
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Various Types of Test Supporting
Using CAS Structure
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A Hierarchical Test Architecture
Supporting Plug & Play Feature
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Detailed I/O and CTC of The
Hierarchical Test Architecture
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Ch. 10 - Boundary Scan and Core-Based Testing - P. 79
A Hierarchical Test Architecture with I/Os
Compatible to 1149.1
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Ch. 10 - Boundary Scan and Core-Based Testing - P. 80
Comparison between 1149.1 and 1500
1149.1
Purpose
Parallel Mode
Extra Data/Control
I/Os
FSM
Transfer Mode
Latency between
operations
Mandatory
Instructions
1500
Board-level
Core-based
No
Yes
Mandatory: TDI, TDO, Mandatory: WSI, WSO, 6 WSC
TMS, TCK
Optional: TransferDR, WPP,
AUXCKn(s)
Optional: TRST
Yes
No
No
Yes
Yes
No
EXTEST, BYPASS, WS_EXTEST, WS_BYPASS,
SAMPLE, PRELOAD one Wx_INTEST,
WS_PRELOAD (cond. required)
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