DATA SHEET
MOS INTEGRATED CIRCUIT
PD42S4260, 424260
4 M-BIT DYNAMIC RAM
256 K-WORD BY 16-BIT, FAST PAGE MODE, BYTE READ/WRITE MODE
Description
The PD42S4260, 424260 are 262,144 words by 16 bits dynamic CMOS RAMs. The fast page mode and byte
read/write mode capability realize high speed access and low power consumption.
Main Menu
Besides, the PD42S4260 can execute CAS before RAS self refresh.
These are packaged in 44-pin plastic TSOP (II) and 40-pin plastic SOJ.
Features
262,144 words by 16 bits organization
Single +5.0 V 10 % power supply
Power consumption
Part number
Active (MAX.)
Access time
R/W cycle time
Fast page mode
(MAX.)
(MIN.)
cycle time (MIN.)
PD42S4260-60, 424260-60
880.0 mW
60 ns
110 ns
40 ns
PD42S4260-70, 424260-70
880.0 mW
70 ns
130 ns
45 ns
PD42S4260-80, 424260-80
797.5 mW
80 ns
150 ns
50 ns
The PD42S4260 can execute CAS before RAS self refresh
Refresh
Power consumption at standby
(MAX.)
Part number
Refresh cycle
PD42S4260
512 cycles / 128 ms
CAS before RAS self refresh,
CAS before RAS refresh,
RAS only refresh, Hidden refresh
0.825 mW
(CMOS level input)
PD424260
512 cycles / 8 ms
CAS before RAS refresh,
RAS only refresh,
Hidden refresh
5.5 mW
(CMOS level input)
Line Up
Multiplexed address inputs ... Row address: A0 to A8, Column address: A0 to A8
The information in this document is subject to change without notice.
Document No. M11089EJ5V0DS00 (5th edition)
(Previous No. IC-2932)
Date Published February 1996 P
Printed in Japan
The mark
Fast Page DRAM
Fast access and cycle time
shows major revised points.
1991, 1993, 1995
1994
PD42S4260, 424260
Ordering Information
PD42S4260G5-60-7JF
60 ns
PD42S4260G5-70-7JF
70 ns
PD42S4260G5-80-7JF
80 ns
PD42S4260LE-60
60 ns
PD42S4260LE-70
70 ns
PD42S4260LE-80
80 ns
PD424260G5-60-7JF
60 ns
PD424260G5-70-7JF
70 ns
PD424260G5-80-7JF
80 ns
PD424260LE-60
60 ns
PD424260LE-70
70 ns
PD424260LE-80
80 ns
Package
44-pin Plastic TSOP (II)
(400 mil)
Refresh
CAS before RAS self refresh
CAS before RAS refresh
RAS only refresh
Hidden refresh
Main Menu
Access time (MAX.)
40-pin Plastic SOJ
(400 mil)
44-pin Plastic TSOP (II)
(400 mil)
CAS before RAS refresh
RAS only refresh
Hidden refresh
40-pin Plastic SOJ
(400 mil)
Fast Page DRAM
Part number
Line Up
PD42S4260, 424260
(400 mil)
(400 mil)
44
GND
VCC
40
GND
43
I/O16
I/O1
39
I/O16
I/O2
42
I/O15
I/O2
38
I/O15
I/O3
41
I/O14
I/O3
37
I/O14
I/O4
40
I/O13
I/O4
36
I/O13
VCC
39
GND
VCC
35
GND
I/O5
38
I/O12
I/O5
34
I/O12
I/O6
37
I/O11
I/O6
33
I/O11
36
I/O10
I/O7
32
I/O10
35
I/O9
I/O8
10
31
I/O9
NC
11
30
NC
NC
12
29
LCAS
WE
13
28
UCAS
RAS
14
27
OE
NC
15
26
A8
A0
16
25
A7
I/O7
I/O8
10
NC
13
NC
14
32
NC
31
LCAS
WE
15
30
UCAS
RAS
16
29
OE
NC
17
28
A8
A0
18
27
A7
A1
19
26
A6
A2
20
25
A5
A3
21
24
A4
VCC
22
23
GND
A0 to A8
PD42S4260LE
PD424260LE
PD42S4260G5-7JF
PD424260G5-7JF
VCC
I/O1
A1
17
24
A6
A2
18
23
A5
A3
19
22
A4
VCC
20
21
GND
Fast Page DRAM
40-pin Plastic SOJ
Line Up
44-pin Plastic TSOP (II)
Main Menu
Pin Configurations (Marking Side)
: Address Inputs
I/O1 to I/O16 : Data Inputs/Outputs
RAS
: Row Address Strobe
UCAS
: Column Address Strobe (upper)
LCAS
: Column Address Strobe (lower)
WE
: Write Enable
OE
: Output Enable
V CC
: Power Supply
GND
: Ground
NC
: No Connection
PD42S4260, 424260
Lower
Byte
Control
OE
Data
Output
Buffer
Upper
Byte
Control
VCC
A0
to
A8
CAS before
RAS Counter
Row
Address
Buffer
Column
Address
Buffer
X0 to X8
512
Data
Input
Buffer
Row Decoder
GND
I/O1
to
I/O8
(Lower Byte)
Memory
Cell
Array
512 512 16
Data
Output
Buffer
512 16
Y0 to Y8
Sense Amplifier
512
Column Decoder
Fast Page DRAM
Clock Generator
I/O9
to
I/O16
(Upper Byte)
16
Data
Input
Buffer
Line Up
RAS
LCAS
UCAS
WE
Main Menu
Block Diagram
PD42S4260, 424260
Input/Output Pin Functions
The PD42S4260, 424260 have input pins RAS, CAS Note, WE, OE, A0 to A8 and input/output pins I/O1 to
Input/
Output
RAS
(Row address
strobe)
Input
RAS activates the sense amplifier by latching a row address (A0 to A8) and selecting a
corresponding word line.
It refreshes memory cell array of one line selected by the row address (A0 to A8).
It also selects the following function.
CAS before RAS refresh
CAS
(Column address
strobe)
Input
CAS activates data input/output circuit by latching column address (A0 to A8) and selecting a digit line connected with the sense amplifier.
A0 to A8
(Address input)
Input
9-bit address bus.
Input total 18-bit of address signal, upper 9-bit and lower 9-bit in sequence (address
multiplex method).
Therefore, one word (16-bit) is selected from 262,144-word by 16-bit memory cell array.
In actual operation, latch row address by specifying row address and activating RAS.
Then, switch the address bus to column address and activate CAS.
Each address is taken into the device when RAS and CAS are activated.
Therefore, the address input setup time (tASR, tASC) and hold time (tRAH, tCAH) are specified
for the activation of RAS and CAS.
WE
(Write enable)
Input
Write control signal.
Write operation is executed by activating RAS, CAS and WE.
OE
(Output enable)
Input
Read control signal.
Read operation can be executed by activating RAS, CAS and OE.
If WE is activated during read operation, OE is to be ineffective in the device.
Therefore, read operation cannot be executed.
I/O1 to I/O16
(Data input/
output)
Input/
Output
16-bit data bus.
I/O1 to I/O16 are used to input/output data.
Fast Page DRAM
Function
Line Up
Pin name
Main Menu
I/O16.
Note CAS means UCAS and LCAS.
PD42S4260, 424260
Electrical Specifications
After power up (VCC VCC (MIN.)), wait more than 100 s (RAS, CAS inactive) and then, execute eight CAS before
RAS or RAS only refresh cycles as dummy cycles to initialize internal circuit.
Absolute Maximum Ratings
Parameter
Symbol
Condition
Rating
Unit
Voltage on any pin relative to GND
VT
1.0 to +7.0
Supply voltage
VCC
1.0 to +7.0
Output current
IO
50
mA
Power dissipation
PD
Operating ambient temperature
TA
0 to +70
Storage temperature
Tstg
55 to +125
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
5.0
5.5
Supply voltage
VCC
4.5
High level input voltage
VIH
2.4
VCC +1.0
Low level input voltage
VIL
1.0
+0.8
Operating ambient temperature
TA
70
MAX.
Unit
Line Up
Recommended Operating Conditions
Capacitance (TA = 25 C, f = 1 MHz)
Parameter
Input capacitance
Data input/output capacitance
Symbol
Test condition
MIN.
TYP.
C I1
Address
pF
C I2
RAS, CAS, WE, OE
pF
C I/O
I/O
pF
Fast Page DRAM
All voltages are referenced to GND.
Main Menu
CAS means UCAS and LCAS.
PD42S4260, 424260
Operating current
Standby
current
PD42S4260
ICC1
ICC2
RAS, CAS cycling
tRC = tRC (MIN.), IO = 0 mA
MIN.
MAX.
Unit
Notes
tRAC = 60 ns
160
mA
1, 2, 3
tRAC = 70 ns
160
tRAC = 80 ns
145
RAS, CAS VIH (MIN.), IO = 0 mA
RAS only refresh current
Operating current
(Fast page mode)
CAS before RAS
refresh current
CAS before RAS
ICC3
ICC4
ICC5
ICC6
long refresh current
(512 cycles / 128 ms,
only for the PD42S4260)
TYP.
RAS, CAS VCC 0.2 V, IO = 0 mA
PD424260
Test condition
0.15
RAS, CAS VIH (MIN.), IO = 0 mA
RAS, CAS VCC 0.2 V, IO = 0 mA
RAS cycling, CAS VIH (MIN.)
tRC = tRC (MIN.), IO = 0 mA
tRAC = 60 ns
160
tRAC = 70 ns
160
tRAC = 80 ns
145
tRAC = 60 ns
140
tRAC = 70 ns
140
tRAC = 80 ns
130
tRAC = 60 ns
160
tRAC = 70 ns
160
tRAC = 80 ns
145
CAS before RAS refresh:
tRC = 250.0 s
RAS, CAS:
VCC 0.2 V VIH VIH(MAX.)
0 V VIL 0.2 V
tRAS 200 ns
Standby:
RAS, CAS VCC 0.2 V
Address: VIH or VIL
WE, OE: VIH
IO = 0 mA
tRAS 1 s
RAS VIL (MAX.), CAS cycling
tPC = t PC (MIN.), IO = 0 mA
RAS cycling
tRC = tRC (MIN.), IO = 0 mA
mA
mA
1, 2, 3, 4
mA
1, 2, 5
mA
1, 2
200
1, 2
300
1, 2
150
Self refresh current
(CAS before RAS self
refresh, only for the
PD42S4260)
ICC7
RAS, CAS:
tRASS = 5 ms
VCC 0.2 V VIH VIH (MAX.)
0 V VIL 0.2 V
IO = 0 mA
Input leakage current
II(L)
VI = 0 to 5.5 V
All other pins not under test = 0 V
10
+10
Output leakage current
IO(L)
VO = 0 to 5.5 V
Output is disabled (Hi-Z)
10
+10
High level output voltage
VOH
IO = 2.5 mA
2.4
Low level output voltage
VOL
IO = +2.1 mA
V
0.4
Main Menu
Symbol
Fast Page DRAM
Parameter
(Recommended Operating Conditions unless otherwise noted)
Line Up
DC Characteristics
Notes 1. ICC1, ICC3, ICC4, ICC5 and ICC6 depend on cycle rates (tRC and tPC).
2. Specified values are obtained with outputs unloaded.
3. ICC1 and ICC3 are measured assuming that address can be changed once or less during RAS
VIL (MAX.) and CAS VIH (MIN.).
4. ICC3 is measured assuming that all column address inputs are held at either high or low.
5. ICC4 is measured assuming that all column address inputs are switched only once during each fast page
cycle.
PD42S4260, 424260
AC Characteristics
(Recommended Operating Conditions unless otherwise noted)
(1) Input timing specification
VIH
(2) Output timing specification
= 2.4 V
VOH (MIN.) = 2.4 V
VIL (MAX.) = 0.8 V
VOL (MAX.) = 0.4 V
(MIN.)
Main Menu
AC Characteristics Test Conditions
tT = 5 ns
tT = 5 ns
(3) Output load condition
Fast Page DRAM
VCC
1,660
I/O
100 pF
590
CL
Common to Read, Write, Read Modify Write Cycle
Parameter
Symbol
tRAC = 60 ns
tRAC = 70 ns
tRAC = 80 ns
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Unit
Notes
Read/Write cycle time
tRC
110
130
150
ns
RAS precharge time
tRP
40
50
60
ns
CAS precharge time
tCPN
10
10
10
ns
RAS pulse width
tRAS
60
10,000
70
10,000
80
10,000
ns
CAS pulse width
tCAS
15
10,000
20
10,000
20
10,000
ns
RAS hold time
tRSH
15
20
20
ns
CAS hold time
tCSH
60
70
80
ns
RAS to CAS delay time
tRCD
20
45
20
50
20
60
ns
RAS to column address delay time
tRAD
15
30
15
35
15
40
ns
CAS to RAS precharge time
tCRP
10
10
10
ns
Row address setup time
tASR
ns
Row address hold time
tRAH
10
10
10
ns
Column address setup time
tASC
ns
Column address hold time
tCAH
15
15
15
ns
OE lead time referenced to RAS
tOES
ns
CAS to data setup time
tCLZ
ns
OE to data setup time
tOLZ
ns
OE to data delay time
tOED
15
15
20
ns
Masked byte write hold time referenced to RAS
tMRH
ns
tT
50
50
50
ns
tREF
128
128
128
ms
ms
Transition time (rise and fall)
Refresh time
PD42S4260
PD424260
Line Up
PD42S4260, 424260
Notes 1. In CAS before RAS refresh cycles, tRAS (MAX.) is 100 s.
If 10 s < tRAS < 100 s, RAS precharge time for CAS before RAS self refresh (tRPS) is applied.
Input conditions
Access time
Access time from RAS
tRAD tRAD (MAX.) and tRCD tRCD (MAX.)
tRAC (MAX.)
tRAC (MAX.)
tRAD >tRAD (MAX.) and tRCD tRCD (MAX.)
tAA (MAX.)
tRAD + tAA (MAX.)
tRCD > tRCD (MAX.)
tCAC (MAX.)
tRCD + tCAC (MAX.)
tRAD (MAX.) and tRCD (MAX.) are specified as reference points only; they are not restrictive operating parameters.
Main Menu
2. For read cycles, access time is defined as follows:
They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD tRAD (MAX.) and tRCD tRCD (MAX.) will not cause
any operation problems.
3. tCRP (MIN.) requirement is applied to RAS, CAS cycles.
Fast Page DRAM
4. This specification is applied only to the PD42S4260.
Parameter
Symbol
tRAC = 60 ns
tRAC = 70 ns
tRAC = 80 ns
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Unit
Notes
Access time from RAS
tRAC
60
70
80
ns
Access time from CAS
tCAC
15
20
20
ns
Access time from column address
tAA
30
35
40
ns
Access time from OE
tOEA
15
20
20
ns
Column address lead time referenced to RAS
tRAL
30
35
40
ns
Read command setup time
tRCS
ns
Read command hold time referenced to RAS
tRRH
ns
Read command hold time referenced to CAS
tRCH
ns
Output buffer turn-off delay time from OE
tOEZ
15
15
20
ns
Output buffer turn-off delay time from CAS
tOFF
15
15
20
ns
Line Up
Read Cycle
Notes 1. For read cycles, access time is defined as follows:
Input conditions
Access time
Access time from RAS
tRAD tRAD (MAX.) and tRCD tRCD (MAX.)
tRAC (MAX.)
tRAC (MAX.)
tRAD >tRAD (MAX.) and tRCD tRCD (MAX.)
tAA (MAX.)
tRAD + tAA (MAX.)
tRCD > tRCD (MAX.)
tCAC (MAX.)
tRCD + tCAC (MAX.)
tRAD (MAX.) and tRCD (MAX.) are specified as reference points only; they are not restrictive operating parameters.
They are used to determine which access time (tRAC, tAA or tCAC) is to be used for finding out when output
data will be available. Therefore, the input conditions tRAD tRAD (MAX.) and tRCD tRCD (MAX.) will not cause
any operation problems.
2. Either tRCH (MIN.) or tRRH (MIN.) should be met in read cycles.
3. tOFF (MAX.) and tOEZ (MAX.) define the time when the output achieves the condition of Hi-Z and is not referenced
to VOH or VOL.
PD42S4260, 424260
Write Cycle
tRAC = 70 ns
tRAC = 80 ns
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Unit
Notes
WE hold time referenced to CAS
tWCH
15
15
15
ns
WE pulse width
tWP
10
15
15
ns
WE lead time referenced to RAS
tRWL
15
20
20
ns
WE lead time referenced to CAS
tCWL
15
15
20
ns
WE setup time
tWCS
ns
OE hold time
tOEH
ns
Data-in setup time
tDS
ns
Data-in hold time
tDH
15
15
20
ns
Main Menu
tRAC = 60 ns
Notes 1. tWP (MIN.) is applied to late write cycles or read modify write cycles. In early write cycles, tWCH (MIN.) should
be met.
2. If tWCS tWCS (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire
cycle.
3. tDS (MIN.) and tDH (MIN.) are referenced to the CAS falling edge in early write cycles. In late write cycles and
read modify write cycles, they are referenced to the WE falling edge.
Read Modify Write Cycle
Parameter
Symbol
tRAC = 60 ns
tRAC = 70 ns
tRAC = 80 ns
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Unit
Fast Page DRAM
Symbol
Note
Read modify write cycle time
tRWC
150
175
200
ns
RAS to WE delay time
tRWD
80
90
105
ns
CAS to WE delay time
tCWD
35
40
45
ns
Column address to WE delay time
tAWD
50
55
65
ns
Note 1. If tWCS tWCS (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
If tRWD tRWD (MIN.), tCWD tCWD (MIN.), tAWD tAWD (MIN.) and tCPWD tCPWD (MIN.), the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met, the state of the data out is indeterminate.
10
Line Up
Parameter
PD42S4260, 424260
Fast Page Mode
tRAC = 60 ns
tRAC = 70 ns
tRAC = 80 ns
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Unit
Symbol
Fast page mode cycle time
tPC
40
45
50
ns
Access time from CAS precharge
tACP
35
40
45
ns
RAS pulse width
tRASP
60
125,000
70
125,000
80
125,000
ns
tCP
10
10
10
ns
RAS hold time from CAS precharge
tRHCP
35
40
45
ns
Read modify write cycle time
tPRWC
80
85
100
ns
CAS precharge to WE delay time
tCPWD
55
60
70
ns
CAS precharge time
Note
Main Menu
Parameter
If tRWD tRWD (MIN.), tCWD tCWD (MIN.), tAWD tAWD (MIN.) and tCPWD tCPWD (MIN.), the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met, the state of the data out is indeterminate.
Refresh Cycle
Parameter
tRAC = 60 ns
tRAC = 70 ns
tRAC = 80 ns
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Symbol
Unit
Note
CAS setup time
tCSR
10
10
10
ns
CAS hold time (CAS before RAS refresh)
tCHR
10
15
15
ns
RAS precharge CAS hold time
tRPC
10
10
10
ns
RAS pulse width
tRASS
100
100
100
RAS precharge time
(CAS before RAS self refresh cycle)
tRPS
110
130
150
ns
CAS hold time
(CAS before RAS self refresh cycle)
tCHS
50
50
50
ns
WE hold time (hidden refresh cycle)
tWHR
10
15
15
ns
Fast Page DRAM
Note 1. If tWCS tWCS (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
Line Up
(CAS before RAS self refresh cycle)
Note 1. This specification is applied only to the PD42S4260.
11
PD42S4260, 424260
Read Cycle
RAS
Main Menu
tRC
tRAS
tRP
VIH
VIL
tCSH
tCRP
UCAS
LCAS
tRCD
tRSH
tCAS
VIH
VIL
tRAD
tASR
Address
tCPN
VIH
VIL
tRAH
tRAL
tCAH
tASC
Row
Col.
WE
Fast Page DRAM
tRCH
tRCS
tRRH
VIH
VIL
tOES
tOEA
OE
VIH
VIL
tRAC
tAA
tCAC
tOFF
tOEZ
tOLZ
tCLZ
VOH
VOL
Hi - Z
Data out
Hi - Z
Line Up
U I/O
L I/O
12
PD42S4260, 424260
Upper Byte Read Cycle
RAS
Main Menu
tRC
tRAS
tRP
VIH
VIL
tCSH
tCRP
tRSH
tCAS
tCPN
VIH
VIL
tCRP
LCAS
tMRH
VIH
VIL
tRAD
tASR
Address
VIH
VIL
tRAH
tRAL
tCAH
tASC
Row
Fast Page DRAM
UCAS
tRCD
Col.
tRCH
tRCS
WE
tRRH
VIH
VIL
tOES
tOEA
OE
VIH
VIL
tRAC
tAA
tCAC
tOFF
tOEZ
Line Up
tOLZ
tCLZ
U I/O
VOH
VOL
Hi - Z
Data out
Hi - Z
Remark L I/O: Hi-Z
13
PD42S4260, 424260
Lower Byte Read Cycle
RAS
tRP
VIH
VIL
tCRP
UCAS
Main Menu
tRC
tRAS
tMRH
VIH
VIL
tCSH
tCRP
tRSH
tCAS
VIH
VIL
tRAD
tASR
Address
tCPN
VIH
VIL
tRAH
tRAL
tASC
Row
Fast Page DRAM
LCAS
tRCD
tCAH
Col.
tRCH
tRCS
WE
tRRH
VIH
VIL
tOES
tOEA
OE
VIH
VIL
tRAC
tAA
tCAC
tOFF
tOEZ
Line Up
tOLZ
tCLZ
L I/O
VOH
VOL
Hi - Z
Data out
Hi - Z
Remark U I/O: Hi-Z
14
PD42S4260, 424260
Early Write Cycle
RAS
Main Menu
tRC
tRAS
tRP
VIH
VIL
tCSH
tRCD
tCRP
UCAS
LCAS
tRSH
tCAS
tCPN
VIH
VIL
tRAD
Address
VIH
VIL
WE
VIH
VIL
U I/O
L I/O
VIH
VIL
tRAH
tASC
Row
tCAH
Col.
tWCS
tWCH
tDS
tDH
Fast Page DRAM
tASR
Data in
Line Up
Remark OE: Dont care
15
PD42S4260, 424260
Upper Byte Early Write Cycle
RAS
Main Menu
tRC
tRAS
tRP
VIH
VIL
tCSH
tRCD
tCRP
VIH
VIL
tCRP
VIH
VIL
tASR
Address
VIH
VIL
WE
VIH
VIL
tRAD
tRAH
tASC
Row
tCAH
Col.
tWCS
tWCH
tDS
U I/O
VIH
VIL
Fast Page DRAM
LCAS
tMRH
tDH
Data in
Line Up
UCAS
tCPN
tRSH
tCAS
Remark OE, L I/O: Dont care
16
PD42S4260, 424260
Lower Byte Early Write Cycle
RAS
tRP
VIH
VIL
tCRP
UCAS
Main Menu
tRC
tRAS
tMRH
VIH
VIL
tCSH
tCRP
LCAS
tRCD
tRSH
tCPN
tCAS
VIH
VIL
Address
VIH
VIL
WE
VIH
VIL
tRAH
tASC
Row
tCAH
Col.
tWCS
tWCH
tDS
L I/O
VIH
VIL
Fast Page DRAM
tRAD
tASR
tDH
Data in
Line Up
Remark OE, U I/O: Dont care
17
PD42S4260, 424260
Late Write Cycle
RAS
Main Menu
tRC
tRAS
tRP
VIH
VIL
tCSH
tRCD
tCRP
UCAS
LCAS
tCPN
VIH
VIL
tASR
Address
tRSH
tCAS
VIH
VIL
tRAD
tRAH
tASC
Row
tCAH
Col.
tRCS
WE
Fast Page DRAM
tCWL
tRWL
tWP
VIH
VIL
tOEH
VIH
VIL
tOED
U I/O
L I/O
VIH
VIL
Hi - Z
tDS
tDH
Data in
Line Up
OE
18
PD42S4260, 424260
Upper Byte Late Write Cycle
RAS
Main Menu
tRC
tRAS
tRP
VIH
VIL
tCSH
tCRP
tRSH
tCAS
VIH
VIL
tCRP
LCAS
tMRH
VIH
VIL
tRAD
tRAH
tASR
Address
tCPN
VIH
VIL
tASC
Row
Fast Page DRAM
UCAS
tRCD
tCAH
Col.
tCWL
tRWL
tRCS
WE
tWP
VIH
VIL
tOEH
VIH
VIL
tOED
U I/O
VIH
VIL
tDS
tDH
Line Up
OE
Hi - Z
Data in
Remark L I/O: Dont care
19
PD42S4260, 424260
Lower Byte Late Write Cycle
RAS
tRP
VIH
VIL
tCRP
UCAS
Main Menu
tRC
tRAS
tMRH
VIH
VIL
tCSH
tCRP
VIH
VIL
tCPN
tCAS
VIH
VIL
tRAD
tRAH
tASR
Address
tRSH
tASC
Row
Fast Page DRAM
LCAS
tRCD
tCAH
Col.
tCWL
tRWL
tRCS
WE
tWP
VIH
VIL
tOEH
VIH
VIL
tOED
L I/O
VIH
VIL
Hi - Z
tDS
tDH
Line Up
OE
Data in
Remark U I/O: Dont care
20
PD42S4260, 424260
Read Modify Write Cycle
RAS
Main Menu
tRWC
tRAS
tRP
VIH
VIL
tCSH
tCRP
UCAS
LCAS
tRCD
tCPN
tRSH
tCAS
VIH
VIL
tRAD
Address
VIH
VIL
tRAH
tASC
Row
tCAH
Col.
tRWD
tAWD
tCWD
tRCS
WE
tCWL
tRWL
tWP
VIH
VIL
tOEA
OE
tOEH
VIH
VIL
tRAC
tAA
tCAC
U I/O
L I/O
Fast Page DRAM
tASR
tOED
tDS
VIH
VIL
tDH
Data in
tOLZ
U I/O
L I/O
VOH
VOL
Hi - Z
tOEZ
Data out
Hi - Z
Line Up
tCLZ
21
PD42S4260, 424260
Upper Byte Read Modify Write Cycle
RAS
Main Menu
tRWC
tRAS
tRP
VIH
VIL
tCSH
tCRP
UCAS
tRCD
tCPN
tRSH
tCAS
VIH
VIL
tCRP
LCAS
tMRH
VIH
VIL
VIH
VIL
tASC
Row
tCAH
Col.
tRWD
tAWD
tCWD
tRCS
WE
tCWL
tRWL
tWP
VIH
VIL
tOEA
OE
VIH
VIL
tRAC
tAA
tCAC
U I/O
tOEH
tOED tDS
VIH
VIL
tDH
Line Up
Address
tRAH
Fast Page DRAM
tRAD
tASR
Data in
tOLZ
tCLZ
U I/O
VOH
VOL
Hi - Z
tOEZ
Data out
Hi - Z
Remark In this cycle, the input data to Lower I/O is ineffective. The data out of that remains Hi-Z.
22
PD42S4260, 424260
Lower Byte Read Modify Write Cycle
RAS
tRP
VIH
VIL
tCRP
UCAS
Main Menu
tRWC
tRAS
tMRH
VIH
VIL
tCSH
tCRP
tRCD
tCPN
tRSH
tCAS
LCAS
VIH
VIL
VIH
VIL
tASC
Row
tCAH
Col.
tRWD
tAWD
tCWD
tRCS
WE
tCWL
tRWL
tWP
VIH
VIL
tOEA
OE
VIH
VIL
tRAC
tAA
tCAC
L I/O
tOEH
tOED tDS
VIH
VIL
tDH
Line Up
Address
tRAH
Fast Page DRAM
tRAD
tASR
Data in
tOLZ
tCLZ
L I/O
VOH
VOL
Hi - Z
tOEZ
Data out
Hi - Z
Remark In this cycle, the input data to Upper I/O is ineffective. The data out of that remains Hi-Z.
23
PD42S4260, 424260
Fast Page Mode Read Cycle
tRASP
VIH
VIL
tCSH
tCRP
UCAS
LCAS
tRCD
tRSH
tCAS
tPC
tCAS
tCP
tCAS
tCP
tCPN
VIH
VIL
tASR
Address
Main Menu
RAS
tRP
tRHCP
VIH
VIL
tRAD
tRAH tASC
Row
tCAH
tASC
Col.
tRAL
tCAH
tASC
tCAH
Col.
Col.
tRCS
tRCH
tRCS
tRRH
VIH
VIL
tOES
tACP
OE
tOEA
tOLZ
tOEA
tOLZ
VIH
VIL
tOEZ
tRAC
tAA
tCAC
tCLZ
U I/O
L I/O
VOH
VOL
Hi - Z
tACP
tOFF
Data out
tOEA
tOLZ
tOEZ
tAA
tCAC
tCLZ
Hi - Z
tOFF
Data out
tAA
tCAC
tCLZ
Hi - Z
tOFF
tOEZ
Data out
Hi - Z
Remark In the fast page mode, read, write and read modify write cycles are available for each of the consecutive
CAS cycles within the same RAS cycle.
24
Line Up
WE
tRCH
Fast Page DRAM
tRCH
tRCS
PD42S4260, 424260
Fast Page Mode Byte Read Cycle
tRHCP
VIH
VIL
tPC
tCSH
tCRP
UCAS
tRCD
tCP
tRAD
tRAH tASC
VIH
VIL
Row
tCAH
tASC
Col.
tCP
tCAH
tMRH
tRCH
tRAL
tCAH
tASC
Col.
tRCS
WE
tCAS
VIH
VIL
tASR
Address
tCPN
VIH
VIL
tCRP
LCAS
tRSH
tCAS
tCAS
Fast Page DRAM
RAS
Main Menu
tRP
tRASP
Col.
tRCS
tRCH
tRCH
tRCS
tRRH
VIH
VIL
tOES
tACP
tOEA
tOLZ
VIH
VIL
tRAC
tAA
tCAC
tCLZ
U I/O
VOH
VOL
tOEA
tOLZ
tOEZ
tAA
tCAC
tCLZ
tOFF
Hi - Z
VOH
VOL
tOFF
tOEZ
Hi - Z
Hi - Z
Data out
Data out
tAA
tCAC
tCLZ
L I/O
tOEA
tOLZ
Line Up
OE
tACP
tOEZ
tOFF
Hi - Z
Hi - Z
Data out
Remarks 1. In the fast page mode, read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.
2. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control UCAS
or LCAS simultaneously, or at random.
25
PD42S4260, 424260
Fast Page Mode Early Write Cycle
tRASP
Main Menu
tRP
tRHCP
VIH
RAS VIL
tPC
tCSH
tCRP
tRCD
tCAS
tCAS
tCP
tRSH
tCAS
tCP
tCPN
UCAS VIH
LCAS VIL
Address VIH
VIL
tRAD
tRAH
tASC
Row
tCAH
tASC
Col.
tCAH
tASC
Col.
tWCS
tWCH
tWCS
tDS
tDH
tDS
tRAL
tCAH
Col.
tWCH
tWCS
tWCH
tDH
tDS
tDH
Fast Page DRAM
tASR
WE VIH
VIL
U I/O VIH
L I/O VIL
Data in
Data in
Data in
Remarks 1. OE: Dont care
2. In the fast page mode, read, write and read modify write cycles are available for each of the
Line Up
consecutive CAS cycles within the same RAS cycle.
26
PD42S4260, 424260
Fast Page Mode Byte Early Write Cycle
tRHCP
VIH
VIL
tCSH
tCRP
UCAS
tPC
tRCD
tCP
tCAS
tCP
tMRH
VIH
VIL
tASR
Address
tCPN
VIH
VIL
tCRP
LCAS
tRSH
tCAS
tCAS
VIH
VIL
tRAD
tRAH
tASC
Row
tCAH
tASC
Col.
tCAH
tASC
Col.
tWCS
tWCH
tDS
tDH
tWCS
tWCH
Fast Page DRAM
RAS
Main Menu
tRP
tRASP
tRAL
tCAH
Col.
tWCS
tWCH
VIH
WE
VIL
VIH
VIL
Data in
Data in
tDS
L I/O
VIH
VIL
tDH
tDH
Line Up
U I/O
tDS
Data in
Remarks 1. OE: Dont care
2. In the fast page mode, read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.
3. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control UCAS
or LCAS simultaneously, or at random.
27
PD42S4260, 424260
Fast Page Mode Late Write Cycle
tRASP
Main Menu
tRP
tRHCP
VIH
VIL
tPC
tCSH
tCRP
tRCD
tCAS
tCP
tCAS
tRSH
tCAS
tCP
tCPN
UCAS VIH
LCAS VIL
tRAD
Address
VIH
VIL
tRAH
tASC
Row
tCAH
tASC
Col.
tCAH
Col.
tCWL
tRCS
tWP
tRAL
tCAH
tASC
Col.
tCWL
tRWL
tWP
tCWL
tRCS
tWP
Fast Page DRAM
tASR
tRCS
WE VIH
VIL
tOEH
OE
tOEH
tOEH
VIH
VIL
tOED
U I/O VIH
L I/O VIL
Hi - Z
tDS
tDH
Data in
tOED
Hi - Z
tDS
tDH
Data in
tOED
Hi - Z
tDS
tDH
Data in
Remark In the fast page mode, read, write and read modify write cycles are available for each of the consecutive
CAS cycles within the same RAS cycle.
28
Line Up
RAS
PD42S4260, 424260
Fast Page Mode Byte Late Write Cycle
Main Menu
tRP
tRASP
tRHCP
VIH
VIL
tRCD
tCP
tCAS
tCP
tMRH
VIH
VIL
tRAD
tASR
Address
VIH
VIL
tRAH
tASC
Row
tASC
tCAH
Col.
tCAH
tRCS
tWP
tRCS
tWP
tRCS
tWP
tOEH
tOEH
VIH
VIL
VIH
VIL
Hi - Z
VIH
VIL
Hi - Z
tDS
tDH
Data in
tOED
L I/O
tCWL
tRWL
VIH
VIL
tOED
U I/O
Col.
tCWL
tOEH
OE
tRAL
tCAH
tASC
Col.
tCWL
WE
tCPN
VIH
VIL
tCRP
LCAS
tRSH
tCAS
tCAS
Fast Page DRAM
UCAS
tPC
tCSH
tCRP
tOED
tOED
Hi - Z
tOED
Hi - Z
tDS
Hi - Z
tDH
Data in
tDS
Line Up
RAS
tDH
Data in
tOED
Hi - Z
Remarks 1. In the fast page mode, read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.
2. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control UCAS
or LCAS simultaneously, or at random.
29
PD42S4260, 424260
Fast Page Mode Read Modify Write Cycle
tRP
Main Menu
tRASP
RAS VIH
VIL
tCRP
tCAS
tCP
tCAS
tCPN
VIH
VIL
tRAL
tRAD
tASR tRAH
tASC
Address
tCP
VIH
VIL
Row
tCAH
tASC
Col.
Col.
Col.
tACP
tRWD
tAWD
tCWD
tRCS
tASC tCAH
tCAH
tCWL
tWP
tACP
tCPWD
tAWD
tCWD
tRCS
tCWL
tWP
tRCS
tCPWD
tAWD
tCWD
tCWL
tRWL
tWP
Fast Page DRAM
UCAS
LCAS
tPRWC
tCAS
tRCD
VIH
WE
VIL
tRAC
tAA
tOEH
tCAC
tOEA
OE VIH
VIL
tCLZ
tOLZ
U I/O VOH
L I/O VOL
Hi - Z
tOED
tCLZ
tOEZ
tOLZ
Hi - Z
out
tDH
in
tOEH
tCAC
tOEA
tDS
U I/O VIH
L I/O VIL
tAA
tOEH
tCAC
tOEA
tOED
tCLZ
tOEZ
tOLZ
Hi - Z
out
tDS
tDH
in
tOED
tOEZ
Hi - Z
out
tDS tDH
Line Up
tAA
in
Remark In the fast page mode, read, write and read modify write cycles are available for each of the consecutive
CAS cycles within the same RAS cycle.
30
PD42S4260, 424260
Fast Page Mode Byte Read Modify Write Cycle
VIH
VIL
tCRP
VIH
VIL
tCRP
LCAS
tCAS
tCP
tCP
tMRH
VIH
VIL
tRAD
tRAL
tCAH
tASR tRAH tASC
Address
VIH
VIL
Row
tASC
Col.
tCAH
tASC
Col.
tCAH
Col.
tACP
tRWD
tAWD
tCWD
tRCS
WE
tWP
tACP
tCPWD
tAWD
tCWD
tCWL
tRCS
tCWL
tWP
tRCS
tCPWD
tAWD
tCWD
tCWL
tRWL
tWP
VIH
VIL
tRAC
tAA
VIH
VIL
tOEA
tCLZ
tOLZ
U I/O
VOH
VOL
Hi - Z
L I/O
VOH
VOL
Hi - Z
tOEH
tCAC
tCAC
tOED
tCLZ
tOEZ
tOLZ
tCLZ
tOED
tOLZ
tOEZ
Hi - Z
out
tOEH
tOEA
tOEA
tOED
tOEZ
Hi - Z
out
Hi - Z
out
tDS
VIH
U I/O VIL
tAA
tAA
tOEH
tCAC
OE
tCPN
tCAS
Fast Page DRAM
UCAS
tPRWC
tCAS
tRCD
Line Up
RAS
Main Menu
tRP
tRASP
tDS tDH
tDH
in
in
tDS
VIH
L I/O
VIL
tDH
in
Remarks 1. In the fast page mode, read, write and read modify write cycles are available for each of the
consecutive CAS cycles within the same RAS cycle.
2. This cycle can be used to control either UCAS or LCAS only. Or, it can be used to control UCAS
or LCAS simultaneously, or at random.
31
PD42S4260, 424260
CAS Before RAS Self Refresh Cycle (Only for the mPD42S4260)
tRASS
VIH
VIL
Main Menu
RAS
tRPS
tCRP
tRPC
tCHS
UCAS
LCAS
VIH
VIL
tCPN
t CSR
Remark Address, WE, OE: Don't care
L I/O, U I/O: Hi-Z
CAS before RAS self refresh can be used independently when used in combination with distributed CAS
before RAS long refresh; However, when used in combination with burst CAS before RAS long refresh or with
long RAS only refresh (both distributed and burst), the following cautions must be observed.
(1) Normal Combined Use of CAS Before RAS Self Refresh and Burst CAS Before RAS Long Refresh
When CAS before RAS self refresh and burst CAS before RAS long refresh are used in combination, please
perform CAS before RAS refresh 512 times within an 8 ms interval just before and after setting CAS before RAS
self refresh.
Fast Page DRAM
Cautions on Use of CAS Before RAS Self Refresh
(2) Normal Combined Use of CAS Before RAS Self Refresh and Long RAS Only Refresh
When CAS before RAS self refresh and RAS only refresh are used in combination, please perform RAS only
(3) If tRASS (MIN.) is not satisfied at the beginning of CAS before RAS self refresh cycles (tRAS < 100 s), CAS before
RAS refresh cycles will be executed one time.
If 10 s < tRAS < 100 s, RAS precharge time for CAS before RAS self refresh (tRPS) is applied.
And refresh cycles (512/128 ms) should be met.
For details, please refer to How to use DRAM Users Manual.
32
Line Up
refresh 512 times within an 8 ms interval just before and after setting CAS before RAS self refresh.
PD42S4260, 424260
CAS Before RAS Refresh Cycle
tRC
RAS
tRP
tRAS
Main Menu
tRC
tRAS
tRP
VIH
VIL
tCRP
tCSR
tCHR
tRPC
tCSR
tCHR
tRPC
tCPN
UCAS VIH
LCAS VIL
L I/O, U I/O: Hi-Z
Fast Page DRAM
Remark Address, WE, OE: Dont care
RAS Only Refresh Cycle
tRC
tRAS
RAS
tRC
tRP
tRAS
tRP
VIH
VIL
tCRP
tCRP
VIH
VIL
tASR
Address
tCPN
VIH
VIL
tRAH
Row
Remark WE, OE: Dont care
tASR
tRAH
Line Up
UCAS
LCAS
tRPC
Row
L I/O, U I/O: Hi-Z
33
PD42S4260, 424260
Hidden Refresh Cycle (Read)
tRC
tRSH
tRCD
tCHR
tASR
VIH
VIL
tRAH
tRAL
tASC
Row
tCAH
Col.
tRCS
WE
tCPN
VIH
VIL
tRAD
Address
tRP
VIH
VIL
tCRP
UCAS
LCAS
tRAS
Fast Page DRAM
RAS
tRP
Main Menu
tRC
tRAS
tWHR
VIH
VIL
tOES
tOEA
VIH
VIL
tRAC
tAA
tCAC
tOLZ
tCLZ
U I/O
L I/O
VOH
VOL
Hi - Z
tOFF
tOEZ
Data Out
Hi - Z
Line Up
OE
34
PD42S4260, 424260
Hidden Refresh Cycle (Write)
tRC
RAS
tRP
VIH
VIL
tCRP
UCAS
LCAS
tRAS
tRP
Main Menu
tRC
tRAS
tRSH
tRCD
tCHR
tCPN
VIH
VIL
tRAD
VIH
VIL
tCAH
tASC
Row
Col.
tWCS
WE
tWCH
VIH
VIL
tDS
U I/O
L I/O
VIH
VIL
Remark OE:
tDH
Data in
Dont care
Line Up
Address
tRAH
Fast Page DRAM
tASR
35
PD42S4260, 424260
Package Drawings
44
Main Menu
44 PIN PLASTIC TSOP(II) (400 mil)
23
Fast Page DRAM
detail of lead end
22
A
H
I
K
C
M
NOTE
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
INCHES
18.63 MAX.
0.734 MAX.
0.93 MAX.
0.037 MAX.
0.8 (T.P.)
0.031 (T.P.)
0.32 +0.08
0.07
0.0130.003
0.10.05
0.0040.002
1.2 MAX.
0.048 MAX.
0.97
0.038
11.760.2
0.4630.008
10.160.1
0.4000.004
0.80.2
0.031 +0.009
0.008
0.145 +0.025
0.015
0.0060.001
0.50.1
0.020 +0.004
0.005
0.13
0.005
0.10
0.004
3 +7
3
3 +7
3
Line Up
S44G5-80-7JF4
36
PD42S4260, 424260
40 PIN PLASTIC SOJ (400 mil)
20
J
I
K
M
NOTE
Each lead centerline is located within 0.12 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
INCHES
26.29 +0.2
0.35
1.035+0.008
0.014
10.16
0.400
11.180.2
0.4400.008
1.080.15
0.043 +0.006
0.007
0.7
0.028
3.50.2
0.1380.008
2.40.2
0.094+0.009
0.008
0.8 MIN.
0.031 MIN.
2.6
0.102
1.27(T.P.)
0.050(T.P.)
0.400.10
0.016 +0.004
0.005
0.12
0.005
9.400.20
0.3700.008
Q
T
0.15
R0.85
0.006
R0.033
0.20 +0.10
0.05
0.008 +0.004
0.002
Line Up
T
Q
Fast Page DRAM
21
40
Main Menu
P40LE-400A-2
37
PD42S4260, 424260
Recommended Soldering Conditions
424260.
For more details, refer to our document SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL
(IEI-1207).
Please consult with our sales offices in case other soldering process is used, or in case the soldering is done
under different conditions.
Main Menu
The following conditions (see tables below and next page) must be met when soldering PD42S4260,
Types of Surface Mount Device
PD42S4260G5-7JF, 424260G5-7JF: 44-pin plastic TSOP (II) (400 mil)
Soldering conditions
Peak temperature of package surface: 235 C or lower,
Reflow time: 30 seconds or less (210 C or higher),
Number of reflow processes: MAX. 2
Exposure limit: 7 daysNote
Infrared ray
reflow
Symbol
Fast Page DRAM
Soldering
process
IR35-107-2
(10 hours pre-baking is required at 125 C afterwards)
Cautions
1. After the first reflow process, cool the package down to room temperature, then start the second reflow process.
2. After the first reflow process, do not use water to remove residual flux
(water can be used in the second process).
VP15-107-2
Line Up
Peak temperature of package: 215 C or lower,
Reflow time: 40 seconds or less (200 C or higher),
Number of reflow processes: MAX. 2
Exposure limit: 7 daysNote
(10 hours pre-baking is required at 125 C afterwards)
VPS
Cautions
1. After the first reflow process, cool the package down to room temperature, then start the second reflow process.
2. After the first reflow process, do not use water to remove residual flux
(water can be used in the second process).
Partial heating
method
Note
Terminal temperature: 300 C or lower,
Time: 3 seconds or less (Per side of the package).
Exposure limit before soldering after dry-pack package is opened.
Storage conditions: 25 C and relative humidity at 65 % or less.
Caution
Do not apply more than one soldering method at any one time, except for Partial heating
method.
38
PD42S4260, 424260
PD42S4260LE, 424260LE: 40-pin plastic SOJ (400 mil)
Soldering conditions
Peak temperature of package surface: 235 C or lower,
Reflow time: 30 seconds or less (210 C or higher),
Number of reflow processes: MAX. 2
Exposure limit: 7 daysNote
(20 hours pre-baking is required at 125 C afterwards)
Infrared ray
reflow
Symbol
Main Menu
Soldering
process
IR35-207-2
Cautions
1. After the first reflow process, cool the package down to room temperature, then start the second reflow process.
2. After the first reflow process, do not use water to remove residual flux
(water can be used in the second process).
VP15-207-2
Fast Page DRAM
Peak temperature of package: 215 C or lower,
Reflow time: 40 seconds or less (200 C or higher),
Number of reflow processes: MAX. 2
Exposure limit: 7 daysNote
(20 hours pre-baking is required at 125 C afterwards)
VPS
Cautions
1. After the first reflow process, cool the package down to room temperature, then start the second reflow process.
2. After the first reflow process, do not use water to remove residual flux
(water can be used in the second process).
Partial heating
method
Note
Terminal temperature: 300 C or lower,
Time: 3 seconds or less (Per side of the package).
Exposure limit before soldering after dry-pack package is opened.
Caution
Do not apply more than one soldering method at any one time, except for Partial heating
method.
39
Line Up
Storage conditions: 25 C and relative humidity at 65 % or less.
