Programmable ASIC logic cells
Xilinx LCA
Xilinx LCA
Xilinx LCA (a trademark, denoting logic cell array)
basic logic cells, configurable logic blocks or
CLBs , are bigger and more complex than the Actel
or QuickLogic cells.
The Xilinx CLBs contain both combinational logic
and flip-flops.
Coarse-grain architecture
Xilinx Mature Products: XC3000, XC4000,
XC5200
Logic Lookup Table
LUT is used instead of basic
gates or MUXs
Specify logic functions to be
implemented as a simple truth
table
n-input LUT can handle function
of 2n inputs
A LUT is actually a small (1-bit)
RAM
FPGA LUTs can be used as RAM
A Two Input Look up table
LUTs can be implemented using MUXs
We do not normally care about the implementation,
just the functioning
x1
x1
0/1
0/1
0/1
0/1
x2
x1 x2
f1
0
0
1
1
1
0
0
1
0
1
0
1
(b) f 1 = x1 x2 + x1 x2
(a) Circuit for a two-input LUT
f1
0
1
x2
(c) Storage cell contents in the LUT
A Three-Input LUT
A simple
extension of the
two-input LUT
leads to the
figure at right
Again, at this
point we are
interested in
function and not
form
x1
x2
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
x3
Inclusion of a Flip-Flop with a LUT
A Flip-Flop can be selected for inclusion or not
Latches the LUT output
Select
Out
Flip-flop
In 1
In 2
LUT
In 3
Clock
can program to
bypass the FF
Xilinx XC3000 CLB
The block diagram for
an XC3000 family CLB
illustrates all of these
features
To simplify the
diagram, programmable
MUX select lines are
not shown
Combinational function
is a LUT
LUT
Xilinx Configurable Logic Block (CLB)
Figure 5.6 The Xilinx XC3000 CLB (configurable logic block).
Xilinx XC3000 CLB
A 32-bit look-up table ( LUT )
CLB propagation delay is fixed (the LUT access
time) and independent of the logic function
7 inputs to the XC3000 CLB:
5 CLB inputs (AE), and
2 flip-flop outputs (QX and QY)
2 outputs from the LUT (F and G).
Since a 32-bit LUT requires only five variables to
form a unique address (32 = 25), there are multiple
ways to use the LUT
Xilinx XC3000 CLB
Use 5 of the 7 possible inputs (AE, QX, QY) with the entire
32-bit LUT [F mode]
the CLB outputs (F and G) are then identical
We can realize functions ranging in complexity from a simple AND
gate (F=G=ABCDE) to a parity function (F=G=A xor B xor C xor D
xor E)
Split the 32-bit LUT in half to implement 2 functions of 4
variables each [FG mode]
choose 4 input variables from the 7 inputs (AE, QX, QY).
you have to choose 2 of the inputs from the 5 CLB inputs (AE); then
one function output connects to F and the other output connects to G
Xilinx XC3000 CLB
Use 5 of the 7 possible inputs (AE, QX, QY) with the entire
32-bit LUT [F mode]
the CLB outputs (F and G) are then identical
Split the 32-bit LUT in half to implement 2 functions of 4
variables each [FG mode]
choose 4 input variables from the 7 inputs (AE, QX, QY).
you have to choose 2 of the inputs from the 5 CLB inputs (AE); then
one function output connects to F and the other output connects to G
You can split the 32-bit LUT in half, using one of the 7 input
variables as a select input to a 2:1 MUX that switches between
F and G [FGM mode]
to implement some functions of 6 and 7 variables
Xilinx XC3000 CLB
Xilinx XC3000 CLB
Xilinx XC3000 CLB: Example 1
Parallel Adder-Subtracter Logic Cell:
Xilinx XC3000 CLB: Example 1(cont..)
Example 2 to realize using Xilinx XC3000 CLB
One input one-output sequence detector that produces an
output value 1 every time the sequence 0101 is detected
and an output value 0 at all other times. For example, if
the input sequence is 010101 then the corresponding
output sequence is 000101.
Alternative Approach
Realizing Y1, Y2
Realizing Z
Altera MAX - Logic cells
Programmable Logic Array
Programmable AND array
feeding into an OR array
can implement a sum-ofproducts form of an
expression
n-channel EPROM
transistors wired to a pullup resistor can implement
a wired-AND function of
the inputs
Output is high only when
all the inputs are high
The inputs must be
inverted
Figure 5.11 Logic Arrays. (a) Two-level logic.
(b) Organized sum of products.
(c) A programmable-AND plane.
(d) EPROM logic array. (e) Wired
logic.
Registered PAL
Figure 5.12 A registered PAL with I inputs, j product terms, and k macrocells.
Logic Expander
A logic expander is an output line of the AND array that feeds back
as an input to the array itself
Logic expanders can help implement functions that require more
product terms than are available in a simple PAL
Consider implementing this function in a three-wide OR array:
F = A C D + B C D + A B + B C
This can be rewritten as a sum of (products of products):
F = (A + B) C D + (A + C) B
F = (A B) (C D) + (A C) B
Logic Expander
Logic expanders can be used to form the expander
terms
(A B) and (A C)
Logic expanders require an extra pass through the
AND array, increasing delay
Logic Expander Implementation
Figure 5.13 Expander logic and programmable inversion.
Simplifying Logic with Programmed
Inversion
Figure 5.14 Use of programmed inversion to simplify logic. (a) The function F = AB+ AC+ AD+ ACD requires four product
terms to implement while (b) the complement F = ABCD+ AD+ AC requires only three product terms.
Altera MAX Architecture
Macrocell features:
Wide, programmable
AND array
Narrow, fixed OR array
Logic Expanders
Programmable inversion
Figure 5.15 The Altera MAX architecture. (a)
Organization of logic and
interconnect. (b) A MAX family LAB
(Logic Array Block). (c) A MAX
family macrocell.
Altera MAX architecture
Macro cell for Altera MAX
Altera MAX
Two types of logic expanders
Shareable expanders
Parallel expanders
One of the product term in each macro cell can be used as a
shareable expander
An AND-OR logic expression with more than five terms can often
be factored to utilize shareable expanders from other macro cells.
Altera MAX Shareable expanders
Altera MAX Parallel expanders
References
Chapter-5
from Application Specific ICs
M.J.S.Smith(1997), Addison Wesley, Pearson education.
[1]
[2]. Chapter-6 from Digital Systems Design using VHDL by
Charles H Roth, Jr., PWS.
by
