Microprocessor 8088:

Intel 8088 microprocessor was released in 1979, or one year after the Intel 8086
CPU. Both processors have the same architecture, and the only difference of the
8088 CPU from the 8086 is the external data bus width - it was reduced from 16 bits
to 8 bits. The 8088 microprocessor has 16-bit registers, 16-bit internal data bus and
20-bit address bus, which allows the processor address up to 1 MB of memory.

Pins and their Functions:

V CC, GND and CLK :

there are two pins for ground (GND) p g ( )
one for Vcc
8088 operates on a single, positive supply of 5 V 10%
supply current is 340 mA at room temperature.
The CLK input requires a digital waveform with a 33% duty cycle.
The minimum clock period is 200 ns, corresponding to a frequency of 5 MHz.

AD0 AD7, A8 A19:

These signals constitute the 8088s 20-bit address bus and 8bit data bus.

 AD0 - AD7 are the processor's multiplexed address/data bus.

ALE (address latch enable):

is an output signal used to demultiplex the 8088s address/data bus.
The processor uses ALE to indicate when AD0 through AD7 contain address
information

DT/R, WR, RD, and IO/M:

DT/R (data transmit/receive) is an output used in a minmode ( ) p system to
control the direction of data flow in the bidirectional buffer used on the data bus.
When DT/R is low data should flow into the 8088.
When DT/R is high, the 8088 is outputting data.
WR (write) is an active low output used to indicate when the processor is
writing to a memory or l/O
RD (read) is an active low output used to indicate when the processor is reading
a memory or I/O

processor is reading a memory or I/O.

IO/M is an output that indicates whether the current bus cycle is a memory
access or an I/O access.

NMI, INTR, and INTA:

These three signals control the activity of external hardware interrupts.
NMI and INTR are inputs and function identically in either processor mode.
INTA is an output available only in minmode.

HOLD, HLDA , READY:

_The execution of the processor is suspended as long as HOLD is high
_Acknowledges that the processor is suspended
_Informs the processor that the selected memory or I/O device is ready for a
data transfer

MN/MX, RESET:
High Minimum mode
Low Maximum mode

_Reset 8088

 TEST, DEN:
_It is examined by processor testing instructions
_Disconnects data bus connection

Microprocessor 8085:
It was introduced in 1977. It is 8-bit microprocessor. Its actual name is 8085 A.
It is single NMOS device. It contains 6200 transistors approx.

Pins and their functions:

X1 & X2:
_These are also called Crystal Input Pins.
_8085 can generate clock signals internally.
_To generate clock signals internally, 8085 requires external inputs from X1 and
X2.

RESET IN and RESET OUT:

_RESET IN

_It is used to reset the microprocessor.

_ It is active low signal.
_RESET OUT:
_ It is used to reset the peripheral devices and other ICs on the circuit.
_It is an output signal.
_ It is an active high signal.

SID and SOD:

_SID (Serial Input Data):
_It takes 1 bit input from serial port of 8085.
_ Stores the bit at the 8th position (MSB) of the Accumulator.
_ RIM (Read Interrupt Mask) instruction is used to transfer the bit.
_SOD (Serial Output Data):
_ It takes 1 bit from Accumulator to serial port of 8085.
_ Takes the bit from the 8th position (MSB) of the Accumulator.
_SIM (Set Interrupt Mask) instruction is used to transfer the bit.

TRAP:
_It is an non-maskable interrupt.
_It has the highest priority.
_It cannot be disabled.
_It is both edge and level triggered.
_ It means TRAP signal must go from low to high.
_ TRAP is usually used for power failure and emergency shutoff.

RST 7.5:
_It is a maskable interrupt.
_ It has the second highest priority.
_ It is positive edge triggered only.
_ The internal flip-flop is triggered by the rising edge.
_ The flip-flop remains high until it is cleared by RESET IN.

RST 6.5:
_It is a maskable interrupt.
_ It has the third highest priority.

_ It is level triggered only.

_ The pin has to be held high for a specific period of time.

RST 5.5:
_It is a maskable interrupt.
_It has the fourth highest priority.
_ It is also level triggered.
_ The pin has to be held high for a specific period of time.

INTR:
_ It is a maskable interrupt.
_ It has the lowest priority.
_ It is also level triggered.
_ It is a general purpose interrupt.

INTA:
_ It stands for interrupt acknowledge.
_ It is an outgoing signal.
_ It is an active low signal.

AD0 AD7:
_ These pins serve the dual purpose of transmitting lower order address and
data byte.
_ During 1st clock cycle, these pins act as lower half of address.
_ In remaining clock cycles, these pins act as data bus.
_The separation of lower order address and data is done by address latch.

A8 A15:
_These pins carry the higher order of address bus.
_The address is sent from microprocessor to memory.
_ These 8 pins are switched to high impedance state during HOLD and RESET
mode.

ALE:
_ It is used to enable Address Latch.
_ It indicates whether bus functions as address bus or data bus.

_ If ALE = 1 then Bus functions as address bus.

_ If ALE = 0 then Bus functions as data bus.

S0 and S1:
_S0 and S1 are called Status Pins.
_They tell the current operation which is in progress in 8085.

IO/M:
_This pin tells whether I/O or memory operation is being performed.
_ If IO/M = 1 then I/O operation is being performed.
_ If IO/M = 0 then Memory operation is being performed.

RD:
_RD stands for Read.
_ It is an active low signal.
_ It is a control signal used for Read operation either from memory or from Input
device.
_ A low signal indicates that data on the data bus must be placed either from
selected memory location or from input device.

WR:
_WR stands for Write.
_It is also active low signal.
_It is a control signal used for Write operation either into memory or into output
device.
_ A low signal indicates that data on the data bus must be written into selected
memory location or into output device.

READY:
_This pin is used to synchronize slower peripheral devices with fast
microprocessor.
_A low value causes the microprocessor to enter into wait state.
_The microprocessor remains in wait state until the input at this pin goes high.

HOLD:

_HOLD pin is used to request the microprocessor for DMA transfer.

_A high signal on this pin is a request to microprocessor to relinquish the hold on
buses.
_This request is sent by DMA controller.
_Intel 8257 and Intel 8237 are two DMA controllers.

HLDA:
_HLDA stands for Hold Acknowledge.
_The microprocessor uses this pin to acknowledge the receipt of HOLD signal.
_When HLDA signal goes high, address bus, data bus, RD, WR, IO/M pins are tristated.
_This means they are cut-off from external environment.
_The control of these buses goes to DMA Controller.
_Control remains at DMA Controller until HOLD is held high.
_When HOLD goes low, HLDA also goes low and the microprocessor takes
control of the buses.

VSS and VCC:

_+5V power supply is connected to VCC.
_Ground signal is connected to VSS.

Microprocessor Pentium (80586):

80586 (Pentium) Microprocessor. Pentium (80586) Microprocessor was
introduced in 1993. Data bus is of 64-bit & address bus is of 32 bits. Superscalar
performance: can execute 2 instructions per clock cycle. Introductory versions
operated with a clocking frequency of 60 MHz & 66 MHz. Can address up to 4G bytes
of memory. Contains total 237 pins. Memory access time near about 18 ns. Contains
near about 3.1 millions of transistors. High-level system functions such as power
management and security. Allows 4MByte memory pages instead of the 4KByte
pages. The numeric coprocessor operates at about five times faster than the 80486
numeric coprocessor. A dual-integer processor often allows two instructions per
clock. Super pipelined architecture. Having speed of 110 MIPs.

Pins and their Functions:

Data bus (D0 D 63):

_64-bit data bus

Address bus (A3 A31):

_Only 29 lines
No A0-A2 (due to 8-byte wide data bus)

Byte enable (BE0# -BE7#):

_ Identifies the set of bytes to read or write
BE0# : least significant byte (D0 D7)
BE1# : next byte (D8 D15)

BE7# : most significant byte (D56 D63)

_Any combination of bytes can be specified

 Data parity (DP0 DP7):

_Even parity for 8 bytes of data
DP0 : D0 D7
DP1 : D8 D15

DP7 : D56 D63

Parity check (PCHK#):

_Indicates the parity check result on data read
_ Parity is checked only for valid bytes
Indicated by BE# signals

Parity enable (PEN#):

_Determines whether parity check should be used

Address parity (AP):

_Bad address parity during inquire cycles

Memory/IO (M/IO#):
_Defines bus cycle: memory or I/O

Write/Read (W/R#):
_Distinguishes between write and read cycles

Data/Code (D/C#):
_Distinguishes between data and code

Cache ability (CACHE#):

_Read cycle: indicates internal cacheability
_Write cycle: burst write-back

Bus locks (LOCK#) :

_Used in read-modify-write cycle
_Useful in implementing semaphores

 Interrupt (INTR):
_External interrupt signal

Nonmaskable interrupt (NMI):

_External NMI signal

Clock (CLK):
_System clock signal

Bus ready (BRDY#):

_Used to extend the bus cycle
Introduces wait states

Bus request (BREQ):

_Used in bus arbitration

Backoff (BOFF#):
_Aborts all pending bus cycles and floats the bus
_ Useful to resolve deadlock between two bus masters

Bus hold (HOLD):

_Completes outstanding bus cycles and floats bus
_Asserts HLDA to give control of bus to another master

Bus hold acknowledge (HLDA):

_Indicates the Pentium has given control to another local master
_Pentium continues execution from its internal caches

Cache enable (KEN#):

_If asserted, the current cycle is transformed into cache line fill

Write-back/Write-through (WB/WT#):
_Determines the cache write policy to be used

 Reset (RESET):
_Resets the processor
_Starts execution at FFFFFFF0H
_Invalidates all internal caches

Initialization (INIT):
_Similar to RESET but internal caches and FP registers are not flushed
_After power up, use RESET (not INIT)

Differences among 8085, 8088, 80586:

8085:
_8085 is an 8 bit microprocessor chip designed by Intel.
_Maximum memory 64K bytes.

8088:
_Maximum memory 64K bytes.
_8088 has a 20 bit address bus, so it can address 1mb of memory.

80586:
_Data bus is of 64-bit & address bus is of 32 bits.
_Superscalar performance: can execute 2 instructions per clock cycle.
_Introductory versions operated with a clocking frequency of 60 MHz & 66 MHz.