VLSI Design,
Verification & Test
Arnab Sarkar
Dept. of CSE
IIT Guwahati
26-Jul-16 VLSI Design, Verification and Test 1
Unit #1
26-Jul-16 VLSI Design, Verification and Test 2
Introduction
There exists a set of sophisticated computer aided design,
verification and testing tools
Takes the design from a very initial and abstract idea of its
functionality or behavior, to the correct structural
implementation in the form of a packaged chip, in a
streamlined step-by-step manner.
The objective of this course is to explain the fundamental
algorithms and data structures that empowers these tools
Disclaimer: Design being a creative activity can perhaps
never be fully mechanized; hence, human ingenuity will
always remain an essential component of design
26-Jul-16 VLSI Design, Verification and Test 3
Why Computer Aided Design?
Modern designs are too complex to be developed manually
Increasing levels of integration of devices on a substrate
Multi-million gate chips VLSI
Diminishing cost per transistor
Near impossibility to repair integrated circuits
Larger efforts towards zero-defect designs
Efforts towards the consolidation of a larger number of
functionalities on a single substrate - SoCs
Reduces number of components
Enhances performance faster circuits
Reduces design cost in packaging and interconnection
Improves reliability
CAD provides a systematic step-by-step design procedure
From initial functional design to final packaging stage
26-Jul-16 VLSI Design, Verification and Test 4
Why CAD?
Higher integration has led to huge power dissipation
Handling hot-spots
Focus towards low power design at each stage
Paradigm shift towards fault-tolerant designs
safety-critical embedded devices wearable healthcare devices
Manufacturing chips with specified levels of reliability
Increasingly stringent design metrics
Huge design space
Consider a pacemaker
performance sensitive, small size, low power, fault-tolerant, verifiable,
testable, low cost
Efficient algorithms are required at each design stage
To find an optimal solution from an enormous set of feasible
implementation choices
26-Jul-16 VLSI Design, Verification and Test 5
Design Flow: From Concept to Chip
26-Jul-16 VLSI Design, Verification and Test 6
A Toy Example
Suppose you want to design a 1-bit full adder
You first have an initial idea of what it should do
Behavior
26-Jul-16 VLSI Design, Verification and Test 7
A Toy Example continued
Then, you progressively realize its precise ultimate
structure and obtain a packaged chip
26-Jul-16 VLSI Design, Verification and Test 8
Circuit Models
At each stage of design
The circuit is represented through a corresponding model
Shows relevant features without associated details
Models are classified based on:
Levels of abstraction
architectural, logic and
geometrical
Views
behavioral, structural and
physical
26-Jul-16 VLSI Design, Verification and Test 9
Levels of Abstraction
Architectural Level
Modeled as a set of data computation and data transfer
operations and realizes the overall architecture in terms
of say, ALUs, buses, control units etc.
Logic Level
The circuit evaluates a set of logic operations and
realizes a digital circuit
Geometric Level
Modeled as a netlist of connected geometrical entities
(which represent different components) and realizes the
final floor plan or layout
26-Jul-16 VLSI Design, Verification and Test 10
Model Views
Behavioral View
Describe the function of
the circuit regardless of
its implementation
Structural View
Describe the structure
of the circuit as an
interconnection of
components
Physical View
Relates to the physical
objects (e.g.
transistors) of a design
26-Jul-16 VLSI Design, Verification and Test 11
The Design Flow
Synthesis progresses from
one abstraction level to next.
The process of generating a
circuit model, starting from a
less detailed one
Each layer is defined through
a specification model
The reverse is denoted as extraction.
Reverse Engineering get more precise info. from a lower
level and make refinements accordingly.
Eg. At technology mapping, we come to know about a glitch.
The logic level design may be modified accordingly.
26-Jul-16 VLSI Design, Verification and Test 12
Architectural Synthesis
Also called high level synthesis
The input behavioral model can be abstracted as:
Threaded, concurrent, communicating process modules
Representing a set of operations and their dependencies
Process modules have interfaces to other blocks and
outside world.
26-Jul-16 VLSI Design, Verification and Test 13
Architectural Synthesis
At the architectural Level
Specification languages include:
Hardware Description Languages (HDLs) like System
Verilog, system C etc.
Architecture Description Languages (ADLs) like LISA,
EXPRESSION, MIMOLA etc.
At this stage, we have two types of designs
Synchronous (clocked) we will consider them here
Asynchronous (unclocked)
26-Jul-16 VLSI Design, Verification and Test 14
Architectural Synthesis
Synthesis
Identifying hardware resources that can implement the
operations
Scheduling the execution time of the operations
Binding operations to the resources
Synthesis defines
The structural model of a data path
as an interconnection of resources
Logic level model of a control unit
Issues control signals to the data path according to the
schedule
26-Jul-16 VLSI Design, Verification and Test 15
Architectural Synthesis
The output block structure will be represented as:
Data Path
A register bank
A functional unit (FU) bank
A interconnection network
A clocked controller (FSM)
26-Jul-16 CSE 526: CAD for VLSI 16
Architectural Synthesis
Registers connected to functional units via MUXs
Functional Units connected to registers via DMUXs
MUXs / DMUXs controlled by an FSM (controller)
Design broken up into clocked steps
At each step some registers and functional units are
activated; these activations define the RTL assignments
Timing and other constraints are specified on the system.
Temporal logic based assertions
26-Jul-16 VLSI Design, Verification and Test 17
Architectural Synthesis - Example
26-Jul-16 VLSI Design, Verification and Test 18
Logic Synthesis
Logic Level
Specified in terms of a functional representation
Boolean logic and FSMs
We obtain a structural realization through gates and flip-
flops the gate-level netlist.
The following are done:
State encoding
State assignment
Formation of boolean equations
Logic minimization
These stages are referred to as front-end
26-Jul-16 VLSI Design, Verification and Test 19
Logic Synthesis - Example
26-Jul-16 VLSI Design, Verification and Test 20
Logic Synthesis
Back-end of Logic Synthesis
The task of transferring a logic model to an interconnection of
library cells
Library binding or Technology mapping
Microelectronic design styles:
Custom Design
Functional and physical design are hand-crafted
Objective is to optimize every detailed feature of the circuit
Huge design effort and cost
Semi-custom Design
Restrict possible circuit primitives
Reduces possibility of fine-tuning all parts
Opportunity of using pre-designed well-characterized primitives
Examples: Standard-cell based design, Array based Design etc.
26-Jul-16 VLSI Design, Verification and Test 21
Geometrical Synthesis
Traditionally known as Physical Design
The circuit blocks with their real-estate requirements
and interconnections are specified
using graph-like structures
We obtain a geometric layout of the circuit elements and
interconnections
Fabrication
Physical Layout fabricated on wafers
Packaging
Wafers packaged into chips
26-Jul-16 VLSI Design, Verification and Test 22
Physical Design - Example
26-Jul-16 VLSI Design, Verification and Test 23
Verification Issues
Mainly two types:
Intent Verification:
Checking the equivalence between MLi and BSi at each level.
Implementation Verification / Equivalence Checking:
Checking the equivalence between MLi and MLj or BSi and BSj
between levels i and j.
26-Jul-16 VLSI Design, Verification and Test 24
Testing Issues
Prototype testing for design errors
Manufacturing test to check whether packaged chip
produced exactly what was designed
Select fault models (eg. Stuck-at fault model) and drive test
vectors to sensitize faults.
What are the minimum set of test vectors required to
uncover a set of faults?
Design for testability
Add hardware to enhance testability
Built-In Self-Test
26-Jul-16 VLSI Design, Verification and Test 25
The Design Flow
Synthesis progresses from
one abstraction level to next.
The process of generating a
circuit model, starting from a
less detailed one
Each layer is defined through
a specification model
The reverse is denoted as extraction.
Reverse Engineering get more precise info. from a lower
level and make refinements accordingly.
Eg. At technology mapping, we come to know about a glitch.
The logic level design may be modified accordingly.
26-Jul-16 VLSI Design, Verification and Test 26
High Level Synthesis
Architecture Level Design
Register Transfer Level Design
26-Jul-16 VLSI Design, Verification and Test 27
High Level Synthesis
Also called high level synthesis
The input behavioral model can be abstracted as:
Threaded, concurrent, communicating process modules
Representing a set of operations and their dependencies
Process modules have interfaces to other blocks and
outside world.
26-Jul-16 VLSI Design, Verification and Test 28
High Level Synthesis
The output block structure will be represented as:
Data Path
A register bank
A functional unit (FU) bank
A interconnection network
A clocked controller (FSM)
26-Jul-16 VLSI Design, Verification and Test 29
High Level Synthesis
Registers connected to functional units via MUXs
Functional Units connected to registers via DMUXs
MUXs / DMUXs controlled by an FSM (controller)
Design broken up into clocked steps
At each step some registers and functional units are
activated; these activations define the RTL assignments
Timing and other constraints are specified on the system.
Temporal logic based assertions
26-Jul-16 VLSI Design, Verification and Test 30
High Level Synthesis - Example
26-Jul-16 VLSI Design, Verification and Test 31
High Level Synthesis - Example
26-Jul-16 VLSI Design, Verification and Test 32
Overall HLS Steps
Step #1: Decomposition into basic blocks and
generation of master controller
Each module is parsed and its flow chart is extracted
A control flow graph (CFG) is generated from the flow chart
Each node of the CFG is a basic block (BB)
BB is a piece of sequential or straight line code
Single entry and exit points
Generate Master Controller from CFG
States BBs
Transitions Same as CFG
26-Jul-16 VLSI Design, Verification and Test 33
From Code to CFG
26-Jul-16 VLSI Design, Verification and Test 34
Overall HLS Steps
Step #2: Scheduling operations within each BB
All operations in a BB may in principle be performed in a
single clock cycle
Problems Unacceptable hardware cost and delays
Solution: Execute a BB using several clock cycles
Chaining: Multiple operations may be executed in the time
step if: Overall propagation delay < Cycle-time
Scheduling
Assign start time to each operation in a BB
Generate controller to direct operations in each time step
within the BB
26-Jul-16 VLSI Design, Verification and Test 35
Scheduling Process: Steps
Given a BB, obtain Data Flow
Graph [DFG]
Nodes denote operations
edges denote data
dependencies
Acyclic Provides an partial
order among operations [DAG]
Basic Block
X + Y * Z < (W + T)
26-Jul-16 VLSI Design, Verification and Test 36
Scheduling Process: Steps
Generate Operation Constraint Graph (OCG)
Shows only the precedence constraints among operations
Add a source and sink node
OCG
DFG
26-Jul-16 VLSI Design, Verification and Test 37
Scheduling Process: Steps
Assign a time step to each operation in the OCG
Given: area and execution delays of each functional resource type
Multiple options for assigning time steps to operations
26-Jul-16 VLSI Design, Verification and Test 38
Overall HLS Steps
Step #3: Resource Allocation and binding
Allocation:
There may be more than one resource type that can execute
and operation
E.g. ripple-carry and carry-look-ahead adder for addition
Select appropriate resource type
Binding: Map operations to functional resources.
Allocation and binding can be looked as a global optimization
problem considering multiple basic blocks.
Step #4: FSM controller for a BB is inserted into Master
FSM controller replacing the state for the BB
26-Jul-16 VLSI Design, Verification and Test 39
