Qualcomm Technologies, Inc.

Qualcomm® Snapdragon™ 410 Processor APQ8016

Device Specification
LM80-P0436-7 Rev. B
August 2015

© 2015 Qualcomm Technologies, Inc. All rights reserved.

Qualcomm Snapdragon, Fluence, and Qualcomm Adreno are products of Qualcomm Technologies, Inc. Other Qualcomm products
referenced herein are products of Qualcomm Technologies, Inc. or its other subsidiaries.

DragonBoard, Snapdragon, Adreno, Fluence, and Qualcomm are trademarks of Qualcomm Incorporated, registered in the United States and
other countries. All Qualcomm Incorporated trademarks are used with permission. Other product and brand names may be trademarks or
registered trademarks of their respective owners.

This technical data may be subject to U.S. and international export, re-export, or transfer (“export”) laws. Diversion contrary to U.S. and
international law is strictly prohibited.

Use of this document is subject to the license set forth In Exhibit 1.

Qualcomm Technologies, Inc.

5775 Morehouse Drive
San Diego, CA 92121
U.S.A.

LM80-P0436-7 Rev. B
 Revision history
Revision Date Description
A May 29, 2015 Initial release
B August 7, 2015 Added recent changes from source document:
 Section 1.3.1 New features integrated into APQ8016 and Table 3-7
Dhrystone and rock bottom power specifications: Updated the
frequency information
 Table 2-4 Pin descriptions – connectivity functions: Renamed MI2S_1
to Speaker and MI2S_2 to MI2S
 Table 2-10 Pin descriptions – general-purpose input/output ports:
Updated the type of USB_HS_ID for gpio_110
 Table 3-3 Operating conditions Updated the VDD_PLL2 minimum
voltage to 1.72
 Section 3.5 Power sequencing: Corrected the VDD_USBPHY and
PLL2 sequence
 Section 3.10.5 Serial peripheral interface: Corrected spi frequency to
50Mhz

LM80-P0436-7 Rev. B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 2
 Contents

1 Introduction ........................................................................................................................... 7
1.1 Documentation overview............................................................................................................................7
1.2 APQ8016 introduction ................................................................................................................................9
1.2.1 Device variants ....................................................................................................................... 11
1.3 APQ8016 features ................................................................................................................................... 11
1.3.1 New features integrated into APQ8016 .................................................................................. 12
1.3.2 Summary of APQ8016 features .............................................................................................. 12
1.4 Terms and acronyms ............................................................................................................................... 15
1.5 Special marks .......................................................................................................................................... 17

2 Pin Definitions ......................................................................................................................18

2.1 BAM-enabled low-speed peripheral (BLSP) ............................................................................................ 20
2.2 I/O parameter definitions.......................................................................................................................... 22

2.2.1 Pin descriptions ...................................................................................................................... 23

3 Electrical Specifications ......................................................................................................51

3.1 Absolute maximum ratings....................................................................................................................... 51
3.2 Operating conditions ................................................................................................................................ 52
3.2.1 Core voltage minimization (retention mode) ........................................................................... 54
3.3 Power delivery network specification ....................................................................................................... 54
3.3.1 PDN system specification (PCB + baseband IC) .................................................................... 55
3.3.2 PDN specification (PCB-only) ................................................................................................. 55
3.4 DC power characteristics ......................................................................................................................... 56
3.4.1 Dhrystone and rock bottom maximum power ......................................................................... 56
3.5 Power sequencing ................................................................................................................................... 56
3.6 Digital logic characteristics....................................................................................................................... 57
3.7 Timing characteristics .............................................................................................................................. 62
3.7.1 Timing-diagram conventions................................................................................................... 62
3.7.2 Rise and fall time specifications.............................................................................................. 63
3.7.3 Pad design.............................................................................................................................. 63
3.8 Memory support ....................................................................................................................................... 64
3.8.1 EBI0 memory support ............................................................................................................. 64
3.8.2 eMMC on SDC1 ..................................................................................................................... 72
3.9 Multimedia ............................................................................................................................................... 72
3.9.1 Camera interfaces .................................................................................................................. 72
3.9.2 Audio support ......................................................................................................................... 73
3.9.3 Display support ....................................................................................................................... 73
3.10 Connectivity ........................................................................................................................................... 73
3.10.1 Secure digital interfaces ....................................................................................................... 74
3.10.2 USB interfaces...................................................................................................................... 76
3.10.3 I2S interface .......................................................................................................................... 77
3.10.4 Digital microphone PDM interface ........................................................................................ 79
3.10.5 I2C interface .......................................................................................................................... 81
3.10.6 Serial peripheral interface ..................................................................................................... 81

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Contents

3.11 Internal functions.................................................................................................................................... 82

3.11.1 Clocks ................................................................................................................................... 82
3.11.2 Modes and resets ................................................................................................................. 83
3.11.3 JTAG .................................................................................................................................... 84
3.12 RF and power management interfaces .................................................................................................. 84
3.12.1 RF front-end (RFFE) ............................................................................................................. 85
3.12.2 System power management interface (SPMI) ...................................................................... 86

4 Mechanical Information .......................................................................................................87

4.1 Device physical dimensions ..................................................................................................................... 87
4.2 Part marking ............................................................................................................................................ 88
4.2.1 Specification-compliant devices.............................................................................................. 88
4.3 Device ordering information ..................................................................................................................... 89
4.3.1 Specification-compliant devices.............................................................................................. 89
4.4 Device moisture-sensitivity level .............................................................................................................. 90
4.5 Thermal characteristics ............................................................................................................................ 90

5 Carrier, Storage, & Handling Information ...........................................................................91

5.1 Carrier ...................................................................................................................................................... 91
5.1.1 Tape and reel information ....................................................................................................... 91
5.2 Storage .................................................................................................................................................... 92
5.2.1 Bagged storage conditions ..................................................................................................... 92
5.2.2 Out-of-bag duration ................................................................................................................ 92
5.3 Handling................................................................................................................................................... 92
5.3.1 Baking..................................................................................................................................... 92
5.3.2 Electrostatic discharge............................................................................................................ 92

6 PCB Mounting Guidelines ...................................................................................................94

6.1 RoHS compliance .................................................................................................................................... 94

6.2 SMT parameters ...................................................................................................................................... 94
6.2.1 Land pad and stencil design ................................................................................................... 94
6.2.2 Reflow profile .......................................................................................................................... 95
6.2.3 SMT peak package-body temperature ................................................................................... 96
6.2.4 SMT process verification ........................................................................................................ 97
6.3 Board-level reliability ................................................................................................................................ 97

7 Part Reliability ......................................................................................................................98

7.1 Reliability evaluation summary ................................................................................................................ 98
7.1.1 APQ8016 reliability evaluation report for device from GF-F8.................................................. 98
7.1.2 APQ8016 reliability evaluation report for device from TSMC-F15 ........................................ 100
7.1.3 APQ8016 reliability evaluation report for device from Samsung ........................................... 103
7.2 Qualification sample description ............................................................................................................ 105

8 EXHIBIT 1 ............................................................................................................................106

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Contents

Figures
Figure 1-1 APQ8016 functional block diagram and example application ..................................................................... 10
Figure 2-1 APQ8016 pin assignments – legend ........................................................................................................... 18
Figure 2-2 High-level view of APQ8016 pin assignments (top view) ............................................................................ 19
Figure 3-1 IV curve for VOL and VOH (valid for all VDD_Px).............................................................................................. 61
Figure 3-2 Timing-diagram conventions ....................................................................................................................... 62
Figure 3-3 Rise and fall times under different load conditions ...................................................................................... 63
Figure 3-4 Digital input signal switch points ................................................................................................................. 63
Figure 3-5 Output-pad equivalent circuit ...................................................................................................................... 64
Figure 3-6 DDR SDRAM DCLK and DCLKB................................................................................................................ 65
Figure 3-7 DDR SDRAM DQS_x and DQSB_x ............................................................................................................ 66
Figure 3-8 LPDDR2 SDRAM read timing diagram ....................................................................................................... 67
Figure 3-9 LPDDR2 SDRAM write timing diagram ....................................................................................................... 68
Figure 3-10 LPDDR3 SDRAM read timing diagram ..................................................................................................... 70
Figure 3-11 LPDDR3 SDRAM write timing diagram ..................................................................................................... 71
Figure 3-12 Secure digital interface timing diagram ..................................................................................................... 74
Figure 3-13 I2S timing diagram..................................................................................................................................... 78
Figure 3-14 APQ8016 digital mic PDM interface timing ............................................................................................... 79
Figure 3-15 SPI master timing diagram........................................................................................................................ 81
Figure 3-16 XO timing parameters ............................................................................................................................... 82
Figure 3-17 Sleep-clock timing diagram ....................................................................................................................... 83
Figure 3-18 JTAG-interface timing diagram ................................................................................................................. 84
Figure 4-1 760 NSP (14.0 × 12.0 × 0.96 mm) outline drawing ..................................................................................... 87
Figure 4-2 APQ8016 device marking (top view, not to scale) ...................................................................................... 88
Figure 4-3 APQ8016 device identification code ........................................................................................................... 89
Figure 5-1 Carrier tape drawing with part orientation ................................................................................................... 91
Figure 5-2 Tape handling ............................................................................................................................................. 92
Figure 6-1 Area ratio (AR) ............................................................................................................................................ 95
Figure 6-2 Typical SMT reflow profile........................................................................................................................... 96

Tables
Table 1-1 Primary APQ8016 documentation ..................................................................................................................8
Table 1-2 Summary of APQ8016 features ................................................................................................................... 12
Table 1-3 Terms and acronyms ................................................................................................................................... 15
Table 1-4 Special marks .............................................................................................................................................. 17
Table 2-1 BLSP alternate function configurations ........................................................................................................ 20
Table 2-2 BLSP internal pin mapping........................................................................................................................... 21
Table 2-3 I/O description (pad type) parameters .......................................................................................................... 22
Table 2-4 Pin descriptions – memory support functions............................................................................................... 23
Table 2-5 Pin descriptions – multimedia functions ....................................................................................................... 26
Table 2-6 Pin descriptions – connectivity functions ...................................................................................................... 28
Table 2-7 Pin descriptions – internal functions ............................................................................................................. 34
Table 2-8 APQ8016 wakeup pins for modem power management (MPM) .................................................................. 36
Table 2-9 Pin descriptions – chipset interface functions .............................................................................................. 38
Table 2-10 Pin descriptions – general-purpose input/output ports ............................................................................... 40
Table 2-11 Pin descriptions – No connection, do not connect, and reserved pins ....................................................... 48
Table 2-12 Pin descriptions – power supply pins ......................................................................................................... 48
Table 2-13 Pin descriptions – ground pins ................................................................................................................... 50
Table 3-1 Absolute maximum ratings ........................................................................................................................... 51

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Contents

Table 3-2 Operating conditions for APC and CORE rails 1 ........................................................................................... 52
Table 3-3 Operating conditions .................................................................................................................................... 53
Table 3-4 Core voltage in retention mode .................................................................................................................... 54
Table 3-5 PCB + baseband IC PDN impedance vs. frequency .................................................................................... 55
Table 3-6 PCB-only PDN impedance vs. frequency..................................................................................................... 55
Table 3-7 Dhrystone and rock bottom power specifications ......................................................................................... 56
Table 3-8 Digital I/Os specified in this section .............................................................................................................. 57
Table 3-9 1.2 V digital I/O characteristics ..................................................................................................................... 57
Table 3-10 1.8 V digital I/O characteristics ................................................................................................................... 58
Table 3-11 Dual-voltage 1.8 V/2.95 V digital I/O characteristics .................................................................................. 59
Table 3-12 Dual-voltage 1.2 V/1.8 V digital I/O characteristics .................................................................................... 61
Table 3-13 DDR SDRAM clock-timing parameters ...................................................................................................... 65
Table 3-14 DDR SDRAM strobe timing parameters ..................................................................................................... 66
Table 3-15 LPDDR2 SDRAM read timing specifications .............................................................................................. 67
Table 3-16 LPDDR2 SDRAM write timing specifications ............................................................................................. 69
Table 3-17 LPDDR3 SDRAM read timing specifications .............................................................................................. 70
Table 3-18 LPDDR3 SDRAM write timing specifications ............................................................................................. 71
Table 3-19 Supported MIPI_CSI standards and exceptions ........................................................................................ 72
Table 3-20 Supported MIPI_DSI standards and exceptions ........................................................................................ 73
Table 3-21 Supported SD standards and exceptions ................................................................................................... 74
Table 3-22 Secure digital interface timing specifications.............................................................................................. 75
Table 3-23 Supported USB standards and exceptions ................................................................................................ 76
Table 3-24 Device-specific USBPHY specifications ..................................................................................................... 76
Table 3-25 Supported I2S standards and exceptions ................................................................................................... 77
Table 3-26 I2S interface timing ..................................................................................................................................... 78
Table 3-27 Digital microphone timing ........................................................................................................................... 80
Table 3-28 Digital microphone input path performance for sampling rates of 8 kHz, 16 kHz, 32 kHz, and 48 kHz ...... 80
Table 3-29 Supported I2C standards and exceptions ................................................................................................... 81
Table 3-30 SPI master timing characteristics at 50 MHz .............................................................................................. 81
Table 3-31 XO timing parameters ................................................................................................................................ 82
Table 3-32 Sleep-clock timing parameters ................................................................................................................... 83
Table 3-33 JTAG-interface timing characteristics......................................................................................................... 84
Table 3-34 Supported RFFE standards and exceptions .............................................................................................. 85
Table 3-35 RFFE data.................................................................................................................................................. 85
Table 3-36 Rx/Tx data .................................................................................................................................................. 86
Table 3-37 SPMI standards and exceptions ................................................................................................................ 86
Table 3-38 Supported SPMI standards ........................................................................................................................ 86
Table 4-1 APQ8016 device marking line definitions ..................................................................................................... 88
Table 4-2 Device identification code/ordering information details ................................................................................ 89
Table 4-3 Source configuration code ........................................................................................................................... 89
Table 4-4 MSL ratings summary .................................................................................................................................. 90
Table 6-1 Typical SMT reflow profile conditions (for reference only)............................................................................ 95
Table 7-1 GF-F8 silicon reliability results ..................................................................................................................... 98
Table 7-2 GF-F8 package reliability results .................................................................................................................. 99
Table 7-3 TSMC-F15 silicon reliability results ............................................................................................................ 100
Table 7-4 TSMC-F15 package reliability results......................................................................................................... 101
Table 7-5 Samsung silicon reliability results .............................................................................................................. 103
Table 7-6 Samsung package reliability results ........................................................................................................... 103
Table 7-7 Device characteristics ................................................................................................................................ 105

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 1 Introduction

This document describes features and functionality of the Qualcomm® Snapdragon™ 410
processor (model APQ8016) for embedded computing.
Qualcomm processors for embedded computing are dedicated to support embedded device OEMs
in several ways:
 Longevity beyond lifecycle of mobile chipsets through 2020
 Detailed documentation for developers
 Availability of development kits/community board for early access
 Multiple OS support including mainline Linux support
 Availability of several computing module partners for customization for your individual
projects/products
Snapdragon 410 processors deliver high-performance computing, low power consumption and a
rich multimedia experience for embedded devices.
It is an ideal solution for any application requiring computing horsepower and integrated
WiFi/Bluetooth connectivity: Smart Home; Industrial Appliances, Digital Media and TV dongles,
Smart Surveillance and Robotics.
Snapdragon supports a clear deployment path for embedded device OEMs and developers –
starting with single-board computers and development kits and scaling up to customer solutions,
integration services and production-ready, customizable computing modules.

1.1 Documentation overview

Technical information for the APQ8016 device is primarily covered by the documents listed in
Table 1-1. All documents should be studied for a thorough understanding of the device and its
applications.

NOTE: This current version is an early release to support initial product developers. The content is
subject to change without advance notice.

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Introduction

Table 1-1 Primary APQ8016 documentation

Document
Title and description
number

LM80-P0436-7 Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification

(this document) Provides all APQ8016 electrical specifications and mechanical information. Additional
material includes pin assignments; shipping, storage, and handling instructions; PCB
mounting guidelines; and part reliability. This document can be used by company
purchasing departments to facilitate procurement.

LM80-P0436-6 Qualcomm® Snapdragon™ 410 Processor APQ8016 GPIO Pin Assignments

A Microsoft Excel spreadsheet listing all APQ8016 GPIOs (in numeric order), pad
numbers, pad voltages, pull states, and available configurations. This can be used to help
designers define their products’ GPIO assignments.

This document is organized as follows:

Chapter 1 Provides an overview of the APQ8016 documentation, gives a high-

level functional description of the device, lists the device features, and
defines marking conventions, terms, and acronyms used throughout this
document.

Chapter 2 Defines the device pin assignments.

Chapter 3 Defines the device electrical performance specifications, including

absolute maximum ratings and operating conditions.

Chapter 4 Provides IC mechanical information, including dimensions, markings,

ordering information, moisture sensitivity, and thermal characteristics.

Chapter 5 Discusses shipping, storage, and handling of the APQ8016.

Chapter 6 Presents procedures and specifications for mounting the APQ8016 onto
printed circuit boards (PCBs).

Chapter 7 Presents APQ8016 reliability data, including a definition of the

qualification samples and a summary of qualification test results.

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Introduction

1.2 APQ8016 introduction

Embedded computing devices continue to integrate more and increasingly complex functions, and
support more functionality while maintaining performance, board space, and cost.
These demands are met by the APQ8016 (Figure 1-1) – with its ARM Cortex-A53 application
processors – which further expand mass-market chipset capabilities by making rich multimedia
features accessible to more consumers worldwide.
The APQ8016 has a high level of integration that reduces the bill-of-material (BOM), which
delivers board-area savings. The cost and time-to-market advantages of this IC will help drive
adoption in mass markets around the world.
Wireless products based on the APQ8016 chipset may include:
 Music player-enabled devices and applications
 Cameras
 Devices with gaming, streaming video, and video conferencing features
 GPS, GLONASS, and BeiDou for global location-based service (with WGR7640).
 Wireless connectivity–Bluetooth, WLAN, and FM receiver (with WCN3620)
The APQ8016 benefits are applied to each of these product types and include:
 Higher integration to reduce PCB surface area, time-to-market, and BOM costs while adding
capabilities and processing power
 Integrated application processors and hardware cores to eliminate multimedia coprocessors,
and to provide superior image quality and resolution for devices while extending application
times
 Higher computing power for high-end applications, and DC power savings for longer run
times
 Position location and navigation systems supported through the WGR7640 global navigation
satellite system (GNSS) receiver
 The APQ8016 Chipset supports Gen 8C operation
 Standalone GPS, GLONASS, and COMPASS
 1 Hz tracking
 Small, power- and thermal-efficient WGR7640 packaging
 A single platform providing dedicated support for all market-leading codecs and other
multimedia formats to support deployments around the world
 DC power reduction using innovative techniques
 Support for the latest, most popular operating systems

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Introduction

B
H A Memory support
APQ8016
EBI LPDDR2/LPDDR3
Chipset & RFFE I/Fs Processors
ARM Quad Connectivity SDC1 eMMC MCP
Cortex – A53 µP
WGR7640 SPMI
Internal memory
SSBI (4) Serial buses
MIPI_RFFE (5)
SSBI(x2)
Status & control dsc Discrete stat & ctl
dsc Display

MDP
dsc
4-ln MIPI_DSI
GNSS
GNSS ADC RPM Cortex M3 µP
RxLO circuits
GNSS CAMIF timing I2C
Rx circuits

switch
WLAN DACs
C

BB t/r
Application-specific 4-ln MIPI_CSI
RF front-end GNSS WLAN ADCs
receiver 2-ln MIPI_CSI external
Air interfaces I2C I2C sources
Qcamera
web cam
SMB1360
GNSS Gen8C Video / VFE
E Battery
GPS, Galileo, many codecs, Qtv, charger
Glonass, Beidou Qcamcorder, system
Connectivity Qvideophone D power

WCN processing Multimedia Input

BLSP (x6)
UART

T
pwr mgt

AR
UIM WLAN / BT / FM Adreno 3D graphics

C
data

I2
I2C
WCN3620 dsc

I
SP
FM Output
FM

SSBI SPI supply

Rx SSBI Audio / codec digital
Rx voltages pwr mgt
FM RF & BB
Support & I/Os

data
Indicators
& clk SD/ Low Power Audio
dsc
MMC extra SPI chip selects User
BT

Bluetooth Vibration
(LPA)
F
WLAN/BT

SSBI
front-end

SSBI
RFFE

interfaces motor
WLAN / BT RF & BB Rx BB SDC2 Cam flash
(switched)
WLAN

WLAN RF command Audio

WLAN command GPIOs / PWR & GND codec Audio
G devices
Keypad Keypad SPMI IC-level others
I2C power-on
dsc interfaces
HS USB w/ PHY
Internal functions Thermal sensors
PM8916
Dual-voltage UIM (x3) Resource & pwr mgt GP clock & pdm outs General from
clks
hskeeping sensors

debug
Security & QFPROM JTAG/QDSS/ENET
SPI
Other peripherals/sensors I2C Mode/config/resets Clock generation
Accelerometer Pressure Ambient light
Geomagnetic Proximity Haptics
Gyros Temperature Near field comm

Figure 1-1 APQ8016 functional block diagram and example application

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Introduction

The APQ8016 is fabricated using the advanced 28 nm LP CMOS process, and is available in the
760 NSP; a 14.0 ×12.0 × 0.96 mm package with many ground pins for improved electrical
grounding, mechanical strength, and thermal conductivity. See Chapter 2 for pin assignment
details and Chapter 4 for mechanical information.
The APQ8016 supports high-performance applications worldwide using GPS, GNSS, and
BeiDou wireless networks.
Complementary ICs within the APQ8016 chipset include:
 GPS IC: WGR7640 is a GNSS receiver input for GPS, GLONASS, and COMPASS
operation
 Power management: PM8916
 Wireless connectivity: WCN3620 for WLAN, Bluetooth, and FM
The APQ8016 chipset and system software solution supports the Convergence Platform for
applications by leveraging the years of systems expertise and field experience with GNSS
technologies.
Since the APQ8016 includes so many diverse functions, its operation is more easily understood
by considering major functional blocks individually. Therefore, the APQ8016 document set is
organized according to the following block partitioning:
 Architecture and baseband processors
 Memory support
 Air interfaces
 Multimedia
 Connectivity
 Internal functions
 Interfaces to other functions (including the other ICs within the chipset)
 Configurable general-purpose input/output (GPIO) ports
Most of the information contained in this device specification is organized accordingly –
including the circuit groupings within its functional block diagram (Figure 1-1), pin descriptions
(Chapter 2), and detailed electrical specifications (Chapter 3).

1.2.1 Device variants

Information about device variants will be provided in future revisions of this document.

1.3 APQ8016 features

NOTE: Some of the hardware features integrated within the APQ8016 must be enabled by software.
Refer to the latest version of the applicable software release notes to identify the enabled
APQ8016 features.

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Introduction

1.3.1 Features integrated into APQ8016

Features integrated into APQ8016 are as follows:
 Designed up to 1.2 GHz Quad ARM Cortex-A53 64-bit application processors with 512 kB
L2 cache
 28 nm LP process for lower active power dissipation, and faster peak CPU performance
 Single-channel, non-PoP high-speed memory – LPDDR2/LPDDR3 SDRAM up to 533 MHz
clock rate
 QDSP6 v5 processor (vocoder) up to 691 MHz
 Three dual-voltage UIM ports
 Qualcomm Adreno™ A306 3D graphics core

1.3.2 Summary of APQ8016 features

APQ8016 features are summarized in Table 1-2.

Table 1-2 Summary of APQ8016 features

Feature APQ8016 capability

Processors
Applications ARM Cortex-A53 microprocessor cores up to 1.2 GHz
 64-bit processor
 Quad core, 512 kB L2 cache
 Primary boot processor
RPM system  Cortex M3: Modem power manager (MPM)
 MPM coordinates shutdown/wakeup, clock rates, and VDDs

Memory support
System memory via EBI Non PoP LPDDR2, LPDDR3 SDRAM; 32-bit wide; up to 533 MHz
Graphics internal memory 128 kB unified SRAM pool on-chip memory (GMEM)
External memory via SDC1 eMMC v4.5/SD flash devices

RF Support
Air interfaces
 WLAN/BT/FM  Yes – all (with WCN3620)
GNSS – Qualcomm IZat™ Gen 8C:
location engine Support for 3 bands concurrently:
 GPS, BeiDou, and Glonass or
 GPS, BeiDou, and Galileo

Multimedia
Display interfaces  HD (1280 x 720) 60 fps; 16/18/24 bpp RGB
 MIPI_DSI  MIPI DSI 4-lane
 General display features  Wifi display – 720p 30/1080p 30
 FHD + 720p external wireless display

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Introduction

Feature APQ8016 capability

Camera interfaces  Qcamera
 Number of CSIs  Two; 1.5 Gbps per lane
 Primary (CSI0)  4-lane; supports CMOS and CCD sensors
 Up to 13 MP sensors
 Secondary (CSI1)  2-lane MIPI_CSI – webcam support up to 8 MP sensors
 Configurations supported  Pixel manipulations, camera modes, image effects, and
post-processing techniques, including defective pixel correction
 General camera features  I2C control
Mobile display processor MDP for display processing
Video applications performance
 Encode  720p 30 fps (H.264 Baseline/MPEG-4)
 30 fps 1080p (MPEG-4/H.264/VP8/H.263)
 WFD 720p @ 30 fps
 Decode  30 fps 1080p (MPEG-
4/H.264/H.263/DivX/MPEG2/VC1/Soreson/VP8)
 WFD 1080p @ 30 fps
Graphics Adreno 306; up to 400 MHz 3D graphics accelerator
Audio
 Low-power audio  Low power audio for mp3 and AAC playback; surround sound;
 Voice codec support  Versatile – many audio playback and voice modes; encoders for
audio and FM
 Audio codec support  recording; many concurrency modes
 G711; Raw PCM; QCELP; EVRC, -B, -WB; AMR-NB, -WB; GSM-
 Enhanced audio EFR,
 Synthesizer  -FR, -HR
 MP3; AAC, +, eAAC; AMR-NB, -WB, G.711, WMA 9/10 Pro
 Dolby Digital Plus and DTS-HD surround sound
 Fluence™ Noise Cancellation
 QAudioFX/Qconcert/QEnsemble
 128-voice polyphony wavetable
Web technologies  V8 JavaScript Engine optimizations
 Webkit browser JPEG hardware decode acceleration
 Networking Stack IP and HTTP tuning
 Flash 10.x and video processor decode optimization

Connectivity
BLSP ports 6, 4-bits each; multiplexed serial interface functions
 UART  Yes – up to 4 Mbps
 I2 C  Yes – cameras, sensors, SMB, etc.
 SPI (master only)  Yes – cameras, sensors, etc.
UIM Three ports – dual voltage (1.8 V/2.85 V)
USB One USB 2.0 high-speed
Secure digital interfaces  Up to two ports, both dual-voltage
 One 8-bit and one 4-bit
 SD 3.0; SD/MMC card; eMMC v4.5
Wireless connectivity  With WCN3620
 WLAN  802.11 a/b/g/n
 Bluetooth  BT 4.0 LE and earlier
 FM radio  Rx

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Introduction

Feature APQ8016 capability

Touch screen support Capacitive panels via external IC (I2C, SPI, and interrupts)
Audio interfaces
 DMIC  One port for digital microphone application
 MI2S  Up to two ports (primary and secondary ports)
 CDC PDM port  Interface between PM8916 and APQ8016 for audio application

Configurable GPIOs
Number of GPIO ports 122 GPIOs – GPIO_0 to GPIO_121
Input configurations Pull-up, pull-down, keeper, or no pull
Output configurations Programmable drive current
Top-level mode multiplexer The logic block used for configuring different IOs and interfaces for the
desired functionality and pad attributes

Internal functions
PLLs and clocks  Multiple clock regimes; watchdog and sleep timers
 19.2 MHz CXO master clock input
 General-purpose outputs: M/N counter, PDM
Resource and power manager  Fundamental to power management
 Key blocks: RPM core, Cortex M3, security controller, MPM
 Improved efficiency via clock control, split-rail power collapse and
voltage scaling; several low-power sleep modes
Debug JTAG, QDSS
Others Thermal sensors; modes and resets; peripheral subsystem

Chipset and RF front-end (RFFE) interface features

RFICs  WGR7640
 GNSS baseband data  Rx analog interface
 Status and control  SSBIs and discrete signals as needed via GPIOs
Power management  PM8916
 2-line SPMI; dedicated clock and reset lines; plus other GPIOs as
needed
WCN wireless connectivity  WCN3620
 WLAN baseband data  Multiplexed Rx/Tx analog interface
 WLAN status and control  Proprietary 5-line interface
 Bluetooth  2-line data interface plus SSBI
 FM radio  1-line data interface plus SSBI1
QCA near field communicator I2C plus other GPIOs as needed
Fabrication technology and package
Digital die 28 nm LP CMOS
Small, thermally efficient 760 NSP: 14.0 × 12.0 × 0.96 mm; 0.4 mm pitch
package
1 Currently not supported in DragonBoard 410c software

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Introduction

1.4 Terms and acronyms

Table 1-3 defines terms and acronyms commonly used throughout this document.

Table 1-3 Terms and acronyms

Term Definition

3GPP 3rd Generation Partnership Project

ADC Analog-to-digital converter

AFR Average failure rate

BAM Bus Access Manager

APC Application microprocessors

AR Area ratio

BLSP BAM Low-Speed Peripheral

bps Bits per second

BT Bluetooth

CSI Camera serial interface

CTS Clear to Send

DAC Digital-to-analog converter

DDR Double data rate

DSI Display serial interface

EBI External bus interface

GLONASS Global orbiting navigation satellite system

GMEM Graphics internal memory

GNSS Global navigation satellite system

GPIO General-purpose input/output

GPS Global positioning system

I2 C Inter-integrated circuit

I2 S Inter-IC sound

JPEG Joint Photographic Experts Group

JTAG Joint Test Action Group (ANSI/ICEEE Std. 1149.1-1760)

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Introduction

Term Definition

kbps kilobits per second

LCD Liquid crystal display

LPA Low-power audio

LSB Defines whether the LSB is the least significant bit or least significant byte. All instances of
LSB used in this manual are assumed to be LSByte, unless otherwise specified.

MDP Mobile display processor

MIPI Mobile industry processor interface

MMC Multimedia card

MPM Modem power management

MSB Defines whether the MSB is the most significant bit or most significant byte. All instances of
MSB used in this manual are assumed to be MSByte, unless otherwise specified.

MSL Moisture-sensitivity level

NSMD Non-solder-mask-defined

NSP Nanoscale package

PDM Pulse-density modulation

PM Power management

QDSS Qualcomm debug subsystem

QFPROM Qualcomm fuse programmable read-only memory

QTI Qualcomm Technologies, Inc.

QUP Qualcomm unified peripheral

RPM Resource power manager

SBI Serial bus interface

SD Secure digital

SDC Secure digital controller

SEE Qualcomm Secure Execution Environment

SFS Secure file system

SIM Subscriber identity module

SMT Surface mount technology

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Introduction

Term Definition

SPI Serial peripheral interface

SPMI System power management interface

SSBI Single-wire SBI

UART Universal asynchronous receiver/transmitter

UIM User identification module

USB Universal serial bus

VDD Supply voltage

VREF Reference voltage

VREG Voltage regulation

WCN Wireless connectivity network

WLAN Wireless local area network

XO Crystal oscillator

1.5 Special marks

Table 1-4 defines special marks used in this document.

Table 1-4 Special marks

Mark Definition

[ ] Brackets ([ ]) sometimes follow a pin, register, or bit name. These brackets

enclose a range of numbers. For example, DATA[7:4] may indicate a range that
is 4 bits in length, or DATA[7:0] may refer to all eight DATA pins.

_N A suffix of _N indicates an active low signal. For example, RESIN_N.

0x0000 Hexadecimal numbers are identified with an x in the number (for example,
0x0000). All numbers are decimal (base 10) unless otherwise specified. Non-
obvious binary numbers have the term binary enclosed in parentheses at the end
of the number; for example, 0011 (binary).

| A blue vertical bar in the outside margin of a page indicates that a change was
made since the previous revision of this document.

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 2 Pin Definitions

The APQ8016 is available in the 760 NSP – see Chapter 4 for package details. A high­level view
of all pin assignments is shown in Figure 2-2. The pins are colored to indicate which function
type they support, as defined in Figure 2-1.

Figure 2-1 APQ8016 pin assignments – legend

The text within Figure 2-2 is difficult to read when viewing an 8½" by 11" hard copy. These other
viewing options are available:
 Print that one page on a 11" by 17" sheet.
 View the graphic soft copy and zoom in – the resolution is sufficient for comfortable reading.
 Download the DragonBoard 410c based on Qualcomm Snapdragon 410 processor GPIO Pin
Assignment Spreadsheet (LM80-P0436-6). This Microsoft Excel spreadsheet lists all
APQ8016 pad numbers (in alphanumeric order), pad names, pad voltages, pad types, and
functional descriptions.

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Pin Definitions

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

EBI0_CK EBI0_CK EBI0_DQ_ EBI0_DQ_ EBI0_DQ_

A NC GPIO_35 GND GND GND GND
E_0 E_1 18 19 2

EBI0_CS_ EBI0_CS_ EBI0_CA_ EBI0_CA_ EBI0_DQ_ EBI0_DQ_ EBI0_DM EBI0_DQ_ EBI0_DQ_

B NC GPIO_29 GND
N_0 N_1 8 5 17 16 _2 4 6

EBI0_CA_ EBI0_CA_ EBI0_DQ_

C GPIO_27 GPIO_36 GND EBI0_CK GND GND
2 6 21

EBI0_CA_ EBI0_CK EBI0_CA_ EBI0_DQ_ EBI0_DQ_ EBI0_DQ EBI0_DQ_ EBI0_DQ_

D GPIO_32 GPIO_31 GND GND
3 B 7 20 22 SB_2 3 5

EBI0_CA_ EBI0_CA_ EBI0_CA_ EBI0_CA_ EBI0_DQ_ EBI0_DQ EBI0_DQ_ EBI0_DQ_

E GPIO_11 GPIO_37 GND
4 1 0 9 23 S_2 0 1

EBI0_DM
F GPIO_28 GPIO_30 GPIO_34 GND EBI0_CAL NC NC GND NC
_0

G GPIO_9 GPIO_33 GPIO_17 GND GND GND GND GND GND GND NC

EBI_VRF
H GPIO_10 GPIO_26 GPIO_8 NC NC NC NC VDD_P3 NC NC
E_D0_D2

EBI_VRE
J TDO GPIO_19 GPIO_18 VDD_P3 VDD_P1 VDD_P1 GND GND VDD_P1 VDD_P1
F_CA

K SRST_N TRST_N GND GPIO_16 GND VDD_P1 VDD_P1 GND VDD_P1 GND VDD_P1

L TMS GND GND GND

VDD_CO VDD_CO VDD_ME VDD_ME VDD_ME VDD_CO

M TCK TDI GND GND NC VDD_APC
RE RE M M M RE

SDC2_CM VDD_ME
N GND GND GND GND
D M

SDC2_DA SDC2_DA
P GND GND GND GND GND GND NC GND NC
TA_0 TA_3

SDC2_CL SDC2_DA
R GND GND
K TA_1

MIPI_CSI0 SDC2_DA VDD_CO VDD_CO VDD_ME VDD_ME VDD_CO VDD_ME

T GND GND GND GND
_LN1_P TA_2 RE RE M M RE M

MIPI_CSI0 MIPI_CSI0 MIPI_CSI0 VDD_CO VDD_CO

U
_LN1_N _LN0_N _LN0_P RE RE

MIPI_CSI0 MIPI_CSI0 VREF_PA

V GND VDD_P3 GND GND GND GND GND GND GND
_LN2_P _CLK_P DS

MIPI_CSI0 MIPI_CSI0
W GND VDD_P2 GND GND
_LN2_N _CLK_N

MIPI_CSI1 MIPI_CSI0 VDD_CO VDD_CO VDD_CO VDD_CO VDD_CO VDD_ME VDD_PLL

Y GND GND
_LN0_P _LN3_P RE RE RE RE RE M 1

MIPI_CSI1 MIPI_CSI0
AA GND GND
_LN0_N _LN3_N

MIPI_CSI1 MIPI_CSI1 MIPI_CSI1 MIPI_DSI_

AB VDD_MIPI NC GND GND GND NC GND NC
_LN1_P _CLK_P _CLK_N LDO

MIPI_CSI1
AC GND NC VDD_MIPI
_LN1_N

VDD_ME VDD_CO VDD_CO VDD_CO

AD NC NC NC GND GND GND NC
M RE RE RE

Figure 2-2 High-level view of APQ8016 pin assignments (top view)

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Pin Definitions

2.1 BAM-enabled low-speed peripheral (BLSP)

The BAM integrates three serial bus cores: UARTDM, SPI, and I2C. The SPI and I2C cores are,
in turn, integrated into a single core called the Qualcomm Unified Peripheral (QUP) where both
the sub-cores share the same FIFO. The UARTDM is integrated separately with its own FIFO.
All the cores share the same bus interface.
The external I/O ports of these cores are shared and only one of the cores can be used at any
given time. However, in the mode where UARTDM is used as a two pin UART interface, the I2C,
which is also a two pin interface, can be used simultaneously with UART functionality.
The BLSP supports the following serial protocols:
 UART_DM
 Up to 4 Mbps UART
 Supports all baud rates from 75 to 115200 bps and 4 Mbps
 5-8 bits character size, 0.5-2 bits stop bit, no/even/odd/space parity
 Optional HW flow control based on CTS/RFR (HW or SW based)
 Other: RX-break, hunt char, sticky error status, overflow detection, FIFO watermarking,
FIFO resizing, HW data timeout, HW inactivity timeout
 I2C (master only), driven by QUP
 Up to 3.4 MHz clock rate
 For timing spec and protocol features, refer to section 3.10.4
 SPI, driven by QUP
 Up to 50 MHz operation on all six possible ports
 For timing spec information, refer to section 3.10.6
The following limitations apply to all six BLSPs:
 The UART controller is muxed behind BLSP1 and BLSP 2. As a result, only BLSP1 and
BLSP2 can be configured for UART.
 I2C and SPI cannot be used at the same time on the same BLSP (since they share the QUP
controller)
 Two 2-pin UART interfaces cannot be used together on the same BLSP interface
 Two I2C interfaces cannot be used simultaneously through the same BLSP interface
Detailed pin assignments are presented in Table 2-1 and Table 2-2.

Table 2-1 BLSP alternate function configurations

Pad name Alternate functions

GPIO[0] BLSP1_SPI_MOSI BLSP1_UART_TX

GPIO[1] BLSP1_SPI_MISO BLSP1_UART_RX

GPIO[2] BLSP1_SPI_CS_N BLSP1_UART_CTS_N BLSP1_I2C_SDA_A

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Pin Definitions

Pad name Alternate functions

GPIO[3] BLSP1_SPI_CLK BLSP1_UART_RFR_N BLSP1_I2C_SCL_A

GPIO[4] BLSP2_SPI_MOSI BLSP2_UART_TX

GPIO[5] BLSP2_SPI_MISO BLSP2_UART_RX

GPIO[6] BLSP2_SPI_CS_N BLSP2_UART_CTS_N BLSP2_I2C_SDA_A

GPIO[7] BLSP2_SPI_CLK BLSP2_UART_RFR_N BLSP2_I2C_SCL_A

GPIO[8] BLSP3_SPI_MOSI

GPIO[9] BLSP3_SPI_MISO

GPIO[10] BLSP3_SPI_CS_N BLSP3_I2C_SDA_A

GPIO[11] BLSP3_SPI_CLK BLSP2_I2C_SCL_A

GPIO[12] BLSP4_SPI_MOSI

GPIO[13 BLSP4_SPI_MISO

GPIO[14] BLSP4_SPI_CS_N BLSP4_I2C_SDA_A

GPIO[15] BLSP4_SPI_CLK BLSP4_I2C_SCL_A

GPIO[16] BLSP5_SPI_MOSI

GPIO[17] BLSP5_SPI_MISO

GPIO[18] BLSP5_SPI_CS_N BLSP5_I2C_SDA_B

GPIO[19] BLSP5_SPI_CLK BLSP5_I2C_SCL_B

GPIO[20] BLSP6_SPI_MOSI

GPIO[21] BLSP6_SPI_MISO

GPIO[22] BLSP6_SPI_CS_N BLSP6_I2C_SDA_A

GPIO[23] BLSP6_SPI_CLK BLSP6_I2C_SCL_A

Table 2-2 BLSP internal pin mapping

Pin 4-pin UART I2C + GPIOs I2C + 2-pin UART 4-pin SPI 4 GPIOs

3 UART_TX_DATA GPIO_XX UART_TX_DATA SPI_MOSI_DATA GPIO_XX

2 UART_RX_DATA GPIO_XX UART_RX_DATA SPI_MISO_DATA GPIO_XX

1 UART_CTS_N I2C_DATA I2C_DATA SPI_CS_N GPIO_XX

0 UART_RFR_N I2C_CLK I2C_CLK I2C_CLK GPIO_XX

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Pin Definitions

2.2 I/O parameter definitions

Table 2-3 I/O description (pad type) parameters

Symbol Description

Pad attribute

AI Analog input (does not include pad circuitry)

AO Analog output (does not include pad circuitry)

B Bidirectional digital with CMOS input

DI Digital input (CMOS)

DO Digital output (CMOS)

H High-voltage tolerant

S Schmitt trigger input

Z High-impedance (high-Z) output

Pad pull details for digital I/Os

nppdpukp Programmable pull resistor. The default pull direction is indicated using capital letters
and is a prefix to other programmable options:
 NP: pdpukp = default no-pull with programmable options following the colon (:)
 PD: nppukp = default pull-down with programmable options following the colon (:)
 PU: nppdkp = default pull-up with programmable options following the colon (:)
 KP: nppdpu = default keeper with programmable options following the colon (:)

KP Contains an internal weak keeper device (keepers cannot drive external buses)

NP Contains no internal pull

PU Contains an internal pull-up device

PD Contains an internal pull-down device

Pad voltage groupings for baseband circuits

P1 EBI Pad group 1 (EBI for LPDDR2/LPDDR3 memory); tied to VDD_P1 pins (1.2 V only)

P2 Pad group 2 (SDC2); tied to VDD_P2 pins (1.8 V or 2.95 V)

P3 Pad group 3 (most peripherals); tied to VDD_P3 pins (1.8 V only)

P4 Pad group 4 (UIM3); tied to VDD_P4 pins (1.8 V or 2.95 V)

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Pin Definitions

Symbol Description

P5 Pad group 5 (UIM1); tied to VDD_P5 pins (1.8 V or 2.95 V)

P6 Pad group 6 (UIM2); tied to VDD_P6 pins (1.8 V or 2.95 V)

P7 Pad group 7 (SDC1); tied to VDD_P7 pins (1.2 V or 1.8 V)

MIPI Supply voltage for MIPI_CSI, MIPI_DSI circuits, and I/Os; tied VDD_MIPI (1.8 V only)

Output current drive strength

EBI pads Pads for EBI are tailored for 1.2 V interfaces and are source terminated; additional
details will be given in future revisions of this document.

SDIO2 pads Programmable drive strength, 2 to 8 mA in 2 mA steps

Others1 Programmable drive strength, 2 to 16 mA in 2 mA steps

1 Digital pads other than EBI pads or high-voltage tolerant pads.

2.2.1 Pin descriptions

Descriptions of all pins are presented in the following tables, organized by functional group:
Table 2-4: Memory support functions
Table 2-5: Multimedia functions
Table 2-6 Connectivity functions
Table 2-7: Internal functions
Table 2-9: Chipset interface functions
Table 2-10: General-purpose input/output ports
Table 2-11: No connection, do not connect, and reserved pins
Table 2-12: Power supply pins
Table 2-13: Ground pins

Table 2-4 Pin descriptions – memory support functions

Pad
Pad name
Pad name and/or characteristics
Pad # or alt Functional description
function
function
Voltage Type

E10 EBI_CA_0 P1 DO LPDDR2/LPDDR3 command/address bit 0

E8 EBI_CA_1 P1 DO LPDDR2/LPDDR3 command/address bit 1

C6 EBI_CA_2 P1 DO LPDDR2/LPDDR3 command/address bit 2

D9 EBI_CA_3 P1 DO LPDDR2/LPDDR3 command/address bit 3

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Pin Definitions

Pad
Pad name
Pad name and/or characteristics
Pad # or alt Functional description
function
function
Voltage Type

E6 EBI_CA_4 P1 DO LPDDR2/LPDDR3 command/address bit 4

B13 EBI_CA_5 P1 DO LPDDR2/LPDDR3 command/address bit 5

C12 EBI_CA_6 P1 DO LPDDR2/LPDDR3 command/address bit 6

D13 EBI_CA_7 P1 DO LPDDR2/LPDDR3 command/address bit 7

B11 EBI_CA_8 P1 DO LPDDR2/LPDDR3 command/address bit 8

E14 EBI_CA_9 P1 DO LPDDR2/LPDDR3 command/address bit 9

F11 EBI_CAL_REXT – AI LPDDR2/LPDDR3 calibration resistor

C10 EBI_CK P1 DO LPDDR2/LPDDR3 differential clock (+)

D11 EBI_CKB P1 DO LPDDR2/LPDDR3 differential clock (-)

A8 EBI_CKE_0 P1 DO LPDDR2/LPDDR3 clock enable 0

A10 EBI_CKE_1 P1 DO LPDDR2/LPDDR3 clock enable 1

B7 EBI_CS0_N P1 DO LPDDR2/LPDDR3 chip select 0

B9 EBI_CS1_N P1 DO LPDDR2/LPDDR3 chip select 1

F23 EBI_DM_0 P1 DO LPDDR2/LPDDR3 data mask for byte 0

E24 EBI_DM_1 P1 DO LPDDR2/LPDDR3 data mask for byte 1

B19 EBI_DM_2 P1 DO LPDDR2/LPDDR3 data mask for byte 2

B31 EBI_DM_3 P1 DO LPDDR2/LPDDR3 data mask for byte 3

E20 EBI_DQ_0 P1 B LPDDR2/LPDDR3 data bit 0

E22 EBI_DQ_1 P1 B LPDDR2/LPDDR3 data bit 1

A20 EBI_DQ_2 P1 B LPDDR2/LPDDR3 data bit 2

D21 EBI_DQ_3 P1 B LPDDR2/LPDDR3 data bit 3

B21 EBI_DQ_4 P1 B LPDDR2/LPDDR3 data bit 4

D23 EBI_DQ_5 P1 B LPDDR2/LPDDR3 data bit 5

B23 EBI_DQ_6 P1 B LPDDR2/LPDDR3 data bit 6

A24 EBI_DQ_7 P1 B LPDDR2/LPDDR3 data bit 7

E28 EBI_DQ_8 P1 B LPDDR2/LPDDR3 data bit 8

C26 EBI_DQ_9 P1 B LPDDR2/LPDDR3 data bit 9

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Pin Definitions

Pad
Pad name
Pad name and/or characteristics
Pad # or alt Functional description
function
function
Voltage Type

A26 EBI_DQ_10 P1 B LPDDR2/LPDDR3 data bit 10

B29 EBI_DQ_11 P1 B LPDDR2/LPDDR3 data bit 11

D29 EBI_DQ_12 P1 B LPDDR2/LPDDR3 data bit 12

C28 EBI_DQ_13 P1 B LPDDR2/LPDDR3 data bit 13

A30 EBI_DQ_14 P1 B LPDDR2/LPDDR3 data bit 14

E30 EBI_DQ_15 P1 B LPDDR2/LPDDR3 data bit 15

B17 EBI_DQ_16 P1 B LPDDR2/LPDDR3 data bit 16

B15 EBI_DQ_17 P1 B LPDDR2/LPDDR3 data bit 17

A14 EBI_DQ_18 P1 B LPDDR2/LPDDR3 data bit 18

A18 EBI_DQ_19 P1 B LPDDR2/LPDDR3 data bit 19

D15 EBI_DQ_20 P1 B LPDDR2/LPDDR3 data bit 20

C14 EBI_DQ_21 P1 B LPDDR2/LPDDR3 data bit 21

D17 EBI_DQ_22 P1 B LPDDR2/LPDDR3 data bit 22

E16 EBI_DQ_23 P1 B LPDDR2/LPDDR3 data bit 23

C34 EBI_DQ_24 P1 B LPDDR2/LPDDR3 data bit 24

F33 EBI_DQ_25 P1 B LPDDR2/LPDDR3 data bit 25

C36 EBI_DQ_26 P1 B LPDDR2/LPDDR3 data bit 26

D35 EBI_DQ_27 P1 B LPDDR2/LPDDR3 data bit 27

E34 EBI_DQ_28 P1 B LPDDR2/LPDDR3 data bit 28

B35 EBI_DQ_29 P1 B LPDDR2/LPDDR3 data bit 29

A34 EBI_DQ_30 P1 B LPDDR2/LPDDR3 data bit 30

B33 EBI_DQ_31 P1 B LPDDR2/LPDDR3 data bit 31

C24 EBI_DQS_0 P1 B LPDDR2/LPDDR3 differential data strobe for byte 0 (+)

E26 EBI_DQS_1 P1 B LPDDR2/LPDDR3 differential data strobe for byte 1 (+)

E18 EBI_DQS_2 P1 B LPDDR2/LPDDR3 differential data strobe for byte 2 (+)

E32 EBI_DQS_3 P1 B LPDDR2/LPDDR3 differential data strobe for byte 3 (+)

B25 EBI_DQS_0B P1 B LPDDR2/LPDDR3 differential data strobe for byte 0 (-)

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Pin Definitions

Pad
Pad name
Pad name and/or characteristics
Pad # or alt Functional description
function
function
Voltage Type

D25 EBI_DQS_1B P1 B LPDDR2/LPDDR3 differential data strobe for byte 1 (-)

D19 EBI_DQS_2B P1 B LPDDR2/LPDDR3 differential data strobe for byte 2 (-)

D31 EBI_DQS_3B P1 B LPDDR2/LPDDR3 differential data strobe for byte 3 (-)

J12 EBI_VREF_CA - AI LPDDR2/LPDDR3 CA reference voltage

H21 EBI_VREF_D0_D2 - AI LPDDR2/LPDDR3 D0 and D2 reference voltage

J26 EBI_VREF_D1_D3 - AI LPDDR2/LPDDR3 D1 and D3 reference voltage

Table 2-5 Pin descriptions – multimedia functions

Pad Pad characteristics

Pad name and/or name or
Pad # Functional description
function alt
Voltage Type
function

Primary camera serial interface – 4-lane MIPI_CSI0

U4 MIPI_CSI0_LN0_N MIPI AI, AO MIPI camera serial interface 0 lane 0 – negative

U6 MIPI_CSI0_LN0_P MIPI AI, AO MIPI camera serial interface 0 lane 0 – positive

W6 MIPI_CSI0_CLK_N MIPI AI MIPI camera serial interface 0 clock – negative

V5 MIPI_CSI0_CLK_P MIPI AI MIPI camera serial interface 0 clock – positive

U2 MIPI_CSI0_LN1_N MIPI AI, AO MIPI camera serial interface 0 lane 1 – negative

T1 MIPI_CSI0_LN1_P MIPI AI, AO MIPI camera serial interface 0 lane 1 – positive

W2 MIPI_CSI0_LN2_N MIPI AI, AO MIPI camera serial interface 0 lane 2 – negative

V1 MIPI_CSI0_LN2_P MIPI AI, AO MIPI camera serial interface 0 lane 2 – positive

AA6 MIPI_CSI0_LN3_N MIPI AI, AO MIPI camera serial interface 0 lane 3 – negative

Y5 MIPI_CSI0_LN3_P MIPI AI, AO MIPI camera serial interface 0 lane 3 – positive

Secondary camera serial interface – 2-lane MIPI_CSI1

AA2 MIPI_CSI1_LN0_N MIPI AI, AO MIPI camera serial interface 1 lane 0 – negative

Y1 MIPI_CSI1_LN0_P MIPI AI, AO MIPI camera serial interface 1 lane 0 – positive

AB5 MIPI_CSI1_CLK_N MIPI AI MIPI camera serial interface 1 clock – negative

AB3 MIPI_CSI1_CLK_P MIPI AI MIPI camera serial interface 1 clock – positive

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Pin Definitions

Pad Pad characteristics

Pad name and/or name or
Pad # Functional description
function alt
Voltage Type
function

AC2 MIPI_CSI1_LN1_N MIPI AI, AO MIPI camera serial interface 1 lane 1 – negative

AB1 MIPI_CSI1_LN1_P MIPI AI, AO MIPI camera serial interface 1 lane 1 – positive

CAM_MCLK0 DO Camera master clock 0

H3 GPIO_26 P3 B-PD:nppukp Configurable I/O

CAM_MCLK1 DO Camera master clock 1

C2 GPIO_27 P3 B-PD:nppukp Configurable I/O

CAM_I2C_SDA B Camera I2C serial data

B3 GPIO_29 P3 B-PD:nppukp Configurable I/O

CAM_I2C_SCL B Camera I2C serial clock

F3 GPIO_30 P3 B-PD:nppukp Configurable I/O

CCI_TIMER0 DO Camera control interface timer 0

D3 GPIO_31 P3 B-PD:nppukp Configurable I/O

CCI_TIMER1 DO Camera control interface timer 1

D1 GPIO_32 P3 B-PD:nppukp Configurable I/O

CCI_TIMER2 DO Camera control interface timer 2

B37 GPIO_38 P3 B-PD:nppukp Configurable I/O

CCI_ASYNC0 DI Camera control interface async 0

G4 GPIO_33 P3 B-PD:nppukp Configurable I/O

CAM1_RST_N DO Camera 1 (front camera) reset

F1 GPIO_28 P3 B-PD:nppukp Configurable I/O

CAM0_STANDBY_N DO Camera 0 (rear camera) standby

F5 GPIO_34 P3 B-PD:nppukp Configurable I/O

CAM0_RSTN_N DO Camera 0 (rear camera) reset

A4 GPIO_35 P3 B-PD:nppukp Configurable I/O

Display serial interface – 4-lane MIPI_DSI0

AH1 MIPI_DSI0_CLK_N MIPI AO MIPI display serial interface 0 clock – negative

AG2 MIPI_DSI0_CLK_P MIPI AO MIPI display serial interface 0 clock – positive

AF1 MIPI_DSI0_LN0_N MIPI AI, AO MIPI display serial interface 0 lane 0 – negative

AE2 MIPI_DSI0_LN0_P MIPI AI, AO MIPI display serial interface 0 lane 0 – positive

AF3 MIPI_DSI0_LN1_N MIPI AI, AO MIPI display serial interface 0 lane 1 – negative

AE4 MIPI_DSI0_LN1_P MIPI AI, AO MIPI display serial interface 0 lane 1 – positive

AH3 MIPI_DSI0_LN2_N MIPI AI, AO MIPI display serial interface 0 lane 2 – negative

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Pin Definitions

Pad Pad characteristics

Pad name and/or name or
Pad # Functional description
function alt
Voltage Type
function

AG4 MIPI_DSI0_LN2_P MIPI AI, AO MIPI display serial interface 0 lane 2 – positive

AL2 MIPI_DSI0_LN3_N MIPI AI, AO MIPI display serial interface 0 lane 3 – negative

AK1 MIPI_DSI0_LN3_P MIPI AI, AO MIPI display serial interface 0 lane 3 – positive

AB7 MIPI_DSI_LDO MIPI AI, AO MIPI display serial interface 0 low-dropout

regulator

MDP_VSYNC_P DO MDP VSYNC Signal

AT5 GPIO_24 P3 B-PD:nppukp Configurable I/O

AG6 MIPI_DSI0_CAL MIPI AI, AO MIPI display serial interface 0 calibration

Table 2-6 Pin descriptions – connectivity functions

Pad characteristics
Pad name and/or Pad name or
Pad # Functional description
function alt function
Voltage Type

High-speed USB 2.0

AC40 USB_HS_DM AI, AO USB HS data minus

AB39 USB_HS_DP AI, AO USB HS data plus

AD35 USB_HS_SYSCLOCK DI USB HS system clock (19.2 MHz)

AC38 USB_HS_REXT AI USB HS external resistor

Secure digital controller 1 (SDC1) interface – supports dual-voltage eMMC NAND

AE36 SDC1_CLK P7 B-NP:pdpukp Secure digital controller 1 clock

AH35 SDC1_CMD P7 B-PD:nppukp Secure digital controller 1 command

AD37 SDC1_DATA_0 P7 B-PD:nppukp Secure digital controller 1 data bit 0

AE38 SDC1_DATA_1 P7 B-PD:nppukp Secure digital controller 1 data bit 1

AG34 SDC1_DATA_2 P7 B-PD:nppukp Secure digital controller 1 data bit 2

AH37 SDC1_DATA_3 P7 B-PD:nppukp Secure digital controller 1 data bit 3

AG40 SDC1_DATA_4 P7 B-PD:nppukp Secure digital controller 1 data bit 4

AG38 SDC1_DATA_5 P7 B-PD:nppukp Secure digital controller 1 data bit 5

AF39 SDC1_DATA_6 P7 B-PD:nppukp Secure digital controller 1 data bit 6

AF35 SDC1_DATA_7 P7 B-PD:nppukp Secure digital controller 1 data bit 7

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Pin Definitions

Pad characteristics
Pad name and/or Pad name or
Pad # Functional description
function alt function
Voltage Type

Secure digital controller 2 (SDC2) interface – supports dual-voltage SD 3.0

R4 SDC2_CLK P2 BH-NP:pdpukp Secure digital controller 2 clock

N6 SDC2_CMD P2 BH-PD:nppukp Secure digital controller 2 command

P3 SDC2_DATA_0 P2 BH-PD:nppukp Secure digital controller 2 data bit 0

R6 SDC2_DATA_1 P2 BH-PD:nppukp Secure digital controller 2 data bit 1

T7 SDC2_DATA_2 P2 BH-PD:nppukp Secure digital controller 2 data bit 2

P7 SDC2_DATA_3 P2 BH-PD:nppukp Secure digital controller 2 data bit 3

SD_CARD_DET_N DI Secure digital card detection

B37 GPIO_38 P3 PD:nppukp Configurable I/O

SD_WRITE_PROTECT DI Secure digital card write protection

G38 GPIO_121 P3 PD:nppukp Configurable I/O

Secure digital controller interfaces – common to all SDCs

V9 VREF_PADS AI Reference for secure digital I/O pads

Dual-voltage UIM interfaces

UIM1_DATA B UIM1 data

G40 GPIO_57 P5 PD:nppukp Configurable I/O

UIM1_CLK DO UIM1 clock

J40 GPIO_58 P5 PD:nppukp Configurable I/O

UIM1_RESET DO UIM1 reset

L38 GPIO_59 P5 PD:nppukp Configurable I/O

UIM1_PRESENT DI UIM1 removal detection

Y39 GPIO_60 P3 PD:nppukp Configurable I/O

UIM2_DATA B UIM2 data

L40 GPIO_53 P6 PD:nppukp Configurable I/O

UIM2_CLK DO UIM2 clock

K39 GPIO_54 P6 PD:nppukp Configurable I/O

UIM2_RESET DO UIM2 reset

H39 GPIO_55 P6 PD:nppukp Configurable I/O

UIM2_PRESENT DI UIM2 removal detection

AA36 GPIO_56 P3 PD:nppukp Configurable I/O

UIM3_DATA B UIM3 data

Y37 GPIO_49 P4 PD:nppukp Configurable I/O

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Pin Definitions

Pad characteristics
Pad name and/or Pad name or
Pad # Functional description
function alt function
Voltage Type

UIM3_CLK DO UIM3 clock

AA34 GPIO_50 P4 PD:nppukp Configurable I/O

UIM3_RESET DO UIM3 reset

Y35 GPIO_51 P4 PD:nppukp Configurable I/O

UIM3_PRESENT DI UIM3 removal detection

AA38 GPIO_52 P3 PD:nppukp Configurable I/O

UIM_BATT_ALARM DI UIM battery alarm

AL38 GPIO_61 P3 PD:nppukp Configurable I/O

Y33 VREF_PADS AI Reference for UIM I/O pads

Sensors and keypad buttons

SMB_INT DI SMB interrupt

G34 GPIO_62 P3 B-PD:nppukp Configurable I/O

MAG_INT DI Magnometer interrupt

L36 GPIO_69 P3 B-PD:nppukp Configurable I/O

GYRO_ACCEL_INT_N DI Gyro interrupt

E38 GPIO_115 P3 B-PD:nppukp Configurable I/O

KYPD_SNS0 DI Keypad sense bit 0

H33 GPIO_107 P3 B-PD:nppukp Configurable I/O

KYPD_SNS1 DI Keypad sense bit 1

K35 GPIO_108 P3 B-PD:nppukp Configurable I/O

KYPD_SNS2 DI Keypad sense bit 2

J34 GPIO_109 P3 B-PD:nppukp Configurable I/O

BAM-based low-speed peripheral interface 1 – see Table 2-2 for application-specific pin assignments

BLSP1_3 B BLSP 1 bit 3; UART or SPI

BA38 GPIO_0 P3 PD:nppukp Configurable I/O

BLSP1_2 B BLSP 1 bit 2; UART or SPI

BB39 GPIO_1 P3 PD:nppukp Configurable I/O

BLSP1_1 B BLSP 1 bit 1; UART, SPI, or I2C

AV35 GPIO_2 P3 PD:nppukp Configurable I/O

BLSP1_0 B BLSP 1 bit 0; UART, SPI, or I2C

AY37 GPIO_3 P3 PD:nppukp Configurable I/O

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Pin Definitions

Pad characteristics
Pad name and/or Pad name or
Pad # Functional description
function alt function
Voltage Type

BAM-based low-speed peripheral interface 2 – see Table 2-2 for application-specific pin assignments

BLSP2_3 B BLSP 2 bit 3; UART or SPI

AT9 GPIO_4 P3 PD:nppukp Configurable I/O

BLSP2_2 B BLSP 2 bit 2; UART or SPI

AY1 GPIO_5 P3 PD:nppukp Configurable I/O

BLSP2_1 B BLSP 2 bit 1; UART, SPI, or I2C

AY3 GPIO_6 P3 PD:nppukp Configurable I/O

BLSP2_0 B BLSP 2 bit 0; UART, SPI, or I2C

AV3 GPIO_7 P3 PD:nppukp Configurable I/O

BAM-based low-speed peripheral interface 3 – see Table 2-2 for application-specific pin assignments

BLSP3_3 B BLSP 3 bit 3; SPI

H5 GPIO_8 P3 PD:nppukp Configurable I/O

BLSP3_2 B BLSP 3 bit 2; SPI

G2 GPIO_9 P3 PD:nppukp Configurable I/O

BLSP3_1 B BLSP 3 bit 1; SPI, or I2C

H1 GPIO_10 P3 PD:nppukp Configurable I/O

BLSP3_0 B BLSP 3 bit 0; SPI, or I2C

E2 GPIO_11 P3 PD:nppukp Configurable I/O

BAM-based low-speed peripheral interface 4 – see Table 2-2 for application-specific pin assignments

BLSP4_3 B BLSP 4 bit 3; SPI

AM39 GPIO_12 P3 PD:nppukp Configurable I/O

BLSP4_2 B BLSP 4 bit 2; SPI

AM35 GPIO_13 P3 PD:nppukp Configurable I/O

BLSP4_1 B BLSP 4 bit 1; SPI, or I2C

AN40 GPIO_14 P3 PD:nppukp Configurable I/O

BLSP4_0 B BLSP 4 bit 0; SPI, or I2C

AN36 GPIO_15 P3 PD:nppukp Configurable I/O

BAM-based low-speed peripheral interface 5 – see Table 2-2 for application-specific pin assignments

BLSP5_3 B BLSP 5 bit 3; SPI

K7 GPIO_16 P3 PD:nppukp Configurable I/O

BLSP5_2 B BLSP 5 bit 2; SPI

G6 GPIO_17 P3 PD:nppukp Configurable I/O

BLSP5_1 B BLSP 5 bit 1; SPI, or I2C

J6 GPIO_18 P3 PD:nppukp Configurable I/O

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Pin Definitions

Pad characteristics
Pad name and/or Pad name or
Pad # Functional description
function alt function
Voltage Type

BLSP5_0 B BLSP 5 bit 0; SPI, or I2C

J4 GPIO_19 P3 PD:nppukp Configurable I/O

BAM-based low-speed peripheral interface 6 – see Table 2-2 for application-specific pin assignments

BLSP6_3 B BLSP 6 bit 3; SPI

AY7 GPIO_20 P3 PD:nppukp Configurable I/O

BLSP6_3 B BLSP 6 bit 2; SPI

AW6 GPIO_21 P3 PD:nppukp Configurable I/O

BLSP6_3 B BLSP 6 bit 1; SPI, or I2C

AV7 GPIO_22 P3 PD:nppukp Configurable I/O

BLSP6_3 B BLSP 3 bit 0; SPI, or I2C

BA2 GPIO_23 P3 PD:nppukp Configurable I/O

Serial peripheral interface (SPI) extra chip selects (supplements BLSP ports configured for SPI protocol) signals

BLSP1_SPI_CS3_N B BLSP 1 Chip select 3

AT9 GPIO_4 P3 PD:nppukp Configurable I/O

BLSP2_SPI_CS3_N B BLSP 2Chip select 3

AY1 GPIO_5 P3 PD:nppukp Configurable I/O

BLSP1_SPI_CS2_N B BLSP 1 Chip select 2

K7 GPIO_16 P3 PD:nppukp Configurable I/O

BLSP2_SPI_CS2_N B BLSP 2 Chip select 2

G6 GPIO_17 P3 PD:nppukp Configurable I/O

BLSP3_SPI_CS2_N B BLSP 3 Chip select 2

E4 GPIO_37 P3 PD:nppukp Configurable I/O

BLSP3_SPI_CS3_N B BLSP 3 Chip select 3

L36 GPIO_69 P3 PD:nppukp Configurable I/O

BLSP1_SPI_CS1_N B BLSP 1 Chip select 1

B39 GPIO_110 P3 PD:nppukp Configurable I/O

BLSP3_SPI_CS1_N B BLSP 3 Chip select 1

F39 GPIO_120 P3 PD:nppukp Configurable I/O

BLSP2_SPI_CS1_N B BLSP 2 Chip select 1

G38 GPIO_121 P3 PD:nppukp Configurable I/O

Audio clock

Audio_MCLK B Audio Master CLK signal

AW38 GPIO_116 P3 PD:nppukp Configurable I/O

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Pin Definitions

Pad characteristics
Pad name and/or Pad name or
Pad # Functional description
function alt function
Voltage Type

Audio MI2S interface #1

SPKR_SCLK B Speaker SCLK signal

D39 GPIO_113 P3 PD:nppukp Configurable I/O

SPKR_WS B Speaker Word Select signal

B39 GPIO_110 P3 PD:nppukp Configurable I/O

SPKR_D0 B Speaker Data0 signal

E40 GPIO_114 P3 PD:nppukp Configurable I/O

SPKR_D1 B Speaker Data1 signal

E38 GPIO_115 P3 PD:nppukp Configurable I/O

Audio MI2S interface #2

MI2S_SCLK B MI2S SCLK signal

AR36 GPIO_118 P3 PD:nppukp Configurable I/O

MI2S_WS B MI2S Word Select signal

AV37 GPIO_117 P3 PD:nppukp Configurable I/O

MI2S_D0 B MI2S Data0 signal

BA40 GPIO_119 P3 PD:nppukp Configurable I/O

MI2S_D1 B MI2S Data1 signal

AW36 GPIO_112 P3 PD:nppukp Configurable I/O

Digital MIC interface

DMIC0_CLK DO Digital MIC0 clock

BA38 GPIO_0 P3 PD:nppukp Configurable I/O

DMIC0_DATA B Digital MIC0 data

BB39 GPIO_1 P3 PD:nppukp Configurable I/O

2.2.1.1 General purpose clocks, PDM, and related signals

The APQ8016 IC has several general purpose clock outputs, as well as general purpose pulse
density modulated (PDM) outputs:
 GP_PDM – a configurable pulse-density output (12-bit value configurable), with the base
frequency set at 4.8 MHz.
 The APQ8016 supports three different instances of this configurable PDM output
 GP_PDM0, 1, and 2 can each be used independently. If there is an A or B option in the
IO name, it means only one or the other can be used.

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Pin Definitions

 GP_CLK – A general purpose clock output that lets the user configure a desired clock output
by first selecting a clock source (GPLL0 or 19.2 MHz) and then programming a desired
division ratio (M/N) and a duty cycle.
 The APQ8016 supports four different instances of this clock output
 GP_CLK0, 1, 2, and 3 can be used independently. If there is an A or B option in the IO
name, it means only one or the other can be used.
 Different division ratios may result in differing jitter, with integer divisors producing the
cleanest outputs.
 GP_MN – Similar to GP_CLK, except the source clock is always 4.8 MHz. It is only
available behind GPIO110.

Table 2-7 Pin descriptions – internal functions

Pad name Pad characteristics

Pad name and/or
Pad # or alt Functional description
function
function Voltage Type

JTAG interface

K1 SRST_N P3 PU JTAG reset for debug

M1 TCK P3 PU JTAG clock input

M3 TDI P3 PU:nppdkp JTAG data input

J2 TDO P3 JTAG data output

L2 TMS P3 PU:nppdkp JTAG mode-select input

K3 TRST_N P3 PD JTAG reset

General purpose clocks, PDM and related signals

GP_PDM_0A DO General-purpose PDM output 0A, 12-bit, XO/4 clock

AY7 GPIO_20 P3 B-PD:nppukp Configurable I/O

GP_PDM_1A DO General-purpose PDM output 1A, 12-bit, XO/4 clock

AA38 GPIO_52 P3 B-PD:nppukp Configurable I/O

GP_PDM_0B DO General-purpose PDM output 0B, 12-bit, XO/4 clock

AU4 GPIO_25 P3 B-PD:nppukp Configurable I/O

GP_PDM_1B DO General-purpose PDM output 1B, 12-bit, XO/4 clock

AW6 GPIO_21 P3 B-PD:nppukp Configurable I/O

GP_PDM_2A DO General-purpose PDM output 2A, 12-bit, XO/4 clock

A38 GPIO_98 P3 B-PD:nppukp Configurable I/O

GP_PDM_2B DO General-purpose PDM output 2B, 12-bit, XO/4 clock

D39 GPIO_113 P3 B-PD:nppukp Configurable I/O

GP_CLK0 DO General-purpose clock 0

D3 GPIO_31 P3 B-PD:nppukp Configurable I/O

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Pin Definitions

Pad name Pad characteristics

Pad name and/or
Pad # or alt Functional description
function
function Voltage Type

GP_CLK1 DO General-purpose clock 1

D1 GPIO_32 P3 B-PD:nppukp Configurable I/O

GP_CLK_1A DO General-purpose clock 1A

Y37 GPIO_49 P4 B-PD:nppukp Configurable I/O

GP_CLK_2A DO General-purpose clock 2A

AA34 GPIO_50 P4 B-PD:nppukp Configurable I/O

GP_CLK_3A DO General-purpose clock 3A

Y35 GPIO_51 P4 B-PD:nppukp Configurable I/O

GP_CLK_1B DO General-purpose clock 1B

C38 GPIO_97 P3 B-PD:nppukp Configurable I/O

GP_CLK_2B DO General-purpose clock 2B

AM39 GPIO_12 P3 B-PD:nppukp Configurable I/O

GP_CLK_3B DO General-purpose clock 3B

AM35 GPIO_13 P3 B-PD:nppukp Configurable I/O

GP_MN DO General-purpose M/N:D counter output

B39 GPIO_110 P3 B-PD:nppukp Configurable I/O

Resets and mode controls

AU32 MODE_0 and P3 DIS-PD Mode_0 and Mode_1 pins control the operating
AT31 MODE_1 mode of the device, per the following truth table:
“00” | Native Mode, used for normal operation
“11” | Test mode, can be used for JTAG Boundary
Scan testing
All other modes are reserved.

AV1 RESOUT_N P3 DO Reset output

FORCED_USB_BOOT DI Force USB boot control

E4 GPIO[37] P3 B-PD:nppukp Configurable I/O

C38 BOOT_CONFIG[14] DI Boot Configuration pins [14:0] control various secure

GPIO[97] P3 B-PD:nppukp boot, debugging, and boot device options.
Many of these options are hard-wired on shipped
BOOT_CONFIG[13] DI devices via qFUSE settings.
BC34 GPIO[94] P3 B-PD:nppukp
As immediate reference, the most often used pins
during board development stage are
BOOT_CONFIG[12] DI
BOOT_CONFIG[3:1], which directly control the boot
BD33 GPIO[93] P3 B-PD:nppukp device used, per the following truth table:
“000” | SDC1, followed by SDC2 if needed.
BOOT_CONFIG[11] DI “001” | SDC2, followed by SDC1 if needed.
AY33 GPIO[92] P3 B-PD:nppukp “010” | SDC1 only
“011” | USB
BOOT_CONFIG[10] DI
BE38 GPIO[91] P3 B-PD:nppukp

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Pin Definitions

Pad name Pad characteristics

Pad name and/or
Pad # or alt Functional description
function
function Voltage Type

BOOT_CONFIG[9] DI
BA32 GPIO[90] P3 B-PD:nppukp

BOOT_CONFIG[8] DI
BD35 GPIO[89] P3 B-PD:nppukp

BOOT_CONFIG[7] DI
BB35 GPIO[88] P3 B-PD:nppukp

BOOT_CONFIG[6] DI
BB37 GPIO[87] P3 B-PD:nppukp

BOOT_CONFIG[5] DI
BD39 GPIO[86] P3 B-PD:nppukp

BOOT_CONFIG[4] DI
BC8 GPIO[84] P3 B-PD:nppukp

BOOT_CONFIG[3] DI
BC40 GPIO[83] P3 B-PD:nppukp

BOOT_CONFIG[2] DI
BC38 GPIO[82] P3 B-PD:nppukp

BOOT_CONFIG[1] DI
BD7 GPIO[81] P3 B-PD:nppukp

BOOT_CONFIG[0] DI
BD5 GPIO[80] P3 B-PD:nppukp

Table 2-8 APQ8016 wakeup pins for modem power management (MPM)

Pad characteristics 1
Pad # Pad name Wakeup functional description
Voltage Type

BB39 GPIO_1 P3 B-PD:nppukp General purpose wakeup

AY1 GPIO_5 P3 B-PD:nppukp General purpose wakeup

G2 GPIO_9 P3 B-PD:nppukp General purpose wakeup

E2 GPIO_11 P3 B-PD:nppukp General-purpose wakeup

AM39 GPIO_12 P3 B-PD:nppukp General-purpose wakeup

AM35 GPIO_13 P3 B-PD:nppukp General-purpose wakeup

AY7 GPIO_20 P3 B-PD:nppukp General-purpose wakeup

AW6 GPIO_21 P3 B-PD:nppukp General-purpose wakeup

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Pin Definitions

Pad characteristics 1
Pad # Pad name Wakeup functional description
Voltage Type

AU4 GPIO_25 P3 B-PD:nppukp General-purpose wakeup

F1 GPIO_28 P3 B-PD:nppukp General-purpose wakeup

D3 GPIO_31 P3 B-PD:nppukp General-purpose wakeup

F5 GPIO_34 P3 B-PD:nppukp General-purpose wakeup

A4 GPIO_35 P3 B-PD:nppukp General-purpose wakeup

C4 GPIO_36 P3 B-PD:nppukp General-purpose wakeup

E4 GPIO_37 P3 B-PD:nppukp General-purpose wakeup

B37 GPIO_38 P3 B-PD:nppukp General-purpose wakeup

Y37 GPIO_49 P4 B-PD:nppukp General-purpose wakeup

AA34 GPIO_50 P4 B-PD:nppukp General-purpose wakeup

Y35 GPIO_51 P4 B-PD:nppukp General-purpose wakeup

AA38 GPIO_52 P3 B-PD:nppukp General-purpose wakeup

K39 GPIO_54 P3 B-PD:nppukp General-purpose wakeup

G34 GPIO_62 P3 B-PD:nppukp General-purpose wakeup

AJ38 GPIO_66 P3 B-PD:nppukp General-purpose wakeup

AL40 GPIO_68 P3 B-PD:nppukp General-purpose wakeup

L36 GPIO_69 P3 B-PD:nppukp General-purpose wakeup

C38 GPIO_97 P3 B-PD:nppukp General-purpose wakeup

A38 GPIO_98 P3 B-PD:nppukp General-purpose wakeup

H33 GPIO_107 P3 B-PD:nppukp General-purpose wakeup

K35 GPIO_108 P3 B-PD:nppukp General-purpose wakeup

J34 GPIO_109 P3 B-PD:nppukp General-purpose wakeup

B39 GPIO_110 P3 B-PD:nppukp General-purpose wakeup

C40 GPIO_111 P3 B-PU:nppukp General-purpose wakeup

AW36 GPIO_112 P3 B-PD:nppukp General-purpose wakeup

D39 GPIO_113 P3 B-PD:nppukp General-purpose wakeup

E40 GPIO_114 P3 B-PD:nppukp General-purpose wakeup

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Pin Definitions

Pad characteristics 1
Pad # Pad name Wakeup functional description
Voltage Type

E38 GPIO_115 P3 B-PD:nppukp General-purpose wakeup

AV37 GPIO_117 P3 B-PD:nppukp General-purpose wakeup

AR36 GPIO_118 P3 B-PD:nppukp General-purpose wakeup

F39 GPIO_120 P3 B-PD:nppukp General-purpose wakeup

G38 GPIO_121 P3 B-PD:nppukp General-purpose wakeup

AE38 SDC1_DATA_1 P7 B-PD:nppukp SDIO wakeup

AH37 SDC1_DATA_3 P7 B-PD:nppukp SD card detect

R6 SDC2_DATA_1 P2 BH-PD:nppukp SDIO wakeup

P7 SDC2_DATA_3 P2 BH-PD:nppukp SD card detect

K1 SRST_N P3 DI JTAG

1 Refer to Table 2-3 for parameter and acronym definitions.

Table 2-9 Pin descriptions – chipset interface functions

Pad name Pad characteristics

Pad name and/or
Pad # or alt Functional description
function
function Voltage Type

RFIC – GNSS Rx baseband interface

BE12 GNSS_BB_IP - AI GNSS receiver baseband input, in-phase

plus

BD11 GNSS_BB_IM - AI GNSS receiver baseband input, in-phase

minus

BC14 GNSS_BB_QP - AI GNSS receiver baseband input,

quadrature plus

BB13 GNSS_BB_QM - AI GNSS receiver baseband input,

quadrature minus

RFIC – status and control signals

SSBI_WTR0_RX B SSBI 1 for RFIC 0

AT35 GPIO_103 P3 B-PD:nppukp Configurable I/O

SSBI_WTR0_TX B SSBI 2 for RFIC 0

AW40 GPIO_104 P3 B-PD:nppukp Configurable I/O

LM80-P0436-7 Rev. B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 38
Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Pin Definitions

Pad name Pad characteristics

Pad name and/or
Pad # or alt Functional description
function
function Voltage Type

SSBI_WTR1_RX B SSBI 1 for RFIC 1

AU36 GPIO_105 P3 B-PD:nppukp Configurable I/O

SSBI_WTR1_TX B SSBI 2 for RFIC 1

AY39 GPIO_106 P3 B-PD:nppukp Configurable I/O

WCN – WLAN signals

WLAN_DATA0 B WLAN data bit 0

BD3 GPIO_42 P3 B-PD:nppukp Configurable I/O

WLAN_DATA1 B WLAN data bit 1

BB1 GPIO_41 P3 B-PD:nppukp Configurable I/O

WLAN_DATA2 B WLAN data bit 2

BB5 GPIO_40 P3 B-PD:nppukp Configurable I/O

WLAN_CLK DO-Z WLAN Clock

BB3 GPIO_44 P3 B-PD:nppukp Configurable I/O

WLAN_SET DO-Z WLAN Set

BA6 GPIO_43 P3 B-PD:nppukp Configurable I/O

AR14 WLAN_BB_IM - AI, AO WLAN baseband Rx/Tx switched, in-

phase minus

AP15 WLAN_BB_IP - AI, AO WLAN baseband Rx/Tx switched, in-

phase plus

AP13 WLAN_BB_QM - AI, AO WLAN baseband Rx/Tx switched,

quadrature minus

AR12 WLAN_BB_QP - AI, AO WLAN baseband Rx/Tx switched,

quadrature plus

AU14 WLAN_REXT - AI WLAN external resistor

AR8 WLAN_XO - DI WLAN clock

WCN – Bluetooth signals

B Bluetooth dual-function signal – serial data

AW8 BT_DATA GPIO_48 P3 B-PD:nppukp and strobe
Configurable I/O

DO Bluetooth control
BT_CTL GPIO_47
BA4 P3 B-PD:nppukp Configurable I/O

B Bluetooth single-wire serial bus interface

BT_SSBI GPIO_39
BC2 P3 B-PD:nppukp Configurable I/O

LM80-P0436-7 Rev. B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 39
Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Pin Definitions

Pad name Pad characteristics

Pad name and/or
Pad # or alt Functional description
function
function Voltage Type

WCN – FM signals

B FM radio serial data interface

FM_DATA GPIO_46
AY9 P3 B-PD:nppukp Configurable I/O

B FM radio single-wire serial bus interface

FM_SSBI GPIO_45
AY5 P3 B-PD:nppukp Configurable I/O

PMIC interfaces

AK37 PMIC_SPMI_CLK P3 DO Slave and PBUS interface for PMICs –

data

AJ36 PMIC_SPMI_DATA P3 B Slave and PBUS interface for PMICs –

clock

E36 PS_HOLD P3 DO Power-supply hold signal to PMIC

F35 RESIN_N P3 DI Reset input

G36 SLEEP_CLK P3 DI Sleep clock

AL34 CXO P3 DI Core crystal oscillator (system clock at

19.2 MHz

A36 CXO_EN P3 DO Core crystal oscillator enable

GPS control

EXT_GPS_LNA_EN DO EXT_GPS_LNA_EN
BC32 GPIO_96 P3 PD:nppukp Configurable I/O

Table 2-10 Pin descriptions – general-purpose input/output ports

Pad characteristics
Configurable
Pad # Pad name Functional description
function
Voltage Type

BA38 GPIO_0 P3 B-PD:nppukp Configurable I/O

BLSP1_3 B BLSP #1, bit 3; UART or SPI
DMIC0_CLK DO Digital MIC0 clock

BB39 GPIO_1 P3 B-PD:nppukp Configurable I/O

BLSP1_2 B BLSP #1, bit 2; UART or SPI
DMIC0_DATA DI Digital MIC0 data

AV35 GPIO_2 P3 B-PD:nppukp Configurable I/O

BLSP1_1 B BLSP #1, bit 1; UART, SPI or I2C

AY37 GPIO_3 P3 B-PD:nppukp Configurable I/O

BLSP1_0 B BLSP #1, bit 0; UART, SPI or I2C

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Pin Definitions

Pad characteristics
Configurable
Pad # Pad name Functional description
function
Voltage Type

AT9 GPIO_4 P3 B-PD:nppukp Configurable I/O

BLSP2_3 B BLSP #2, bit 3; UART or SPI
BLSP1_SPI_CS3_N DO Chip select 3 for SPI on BLSP1

AY1 GPIO_5 P3 B-PD:nppukp Configurable I/O

BLSP2_2 B BLSP #2, bit 2; UART or SPI
BLSP2_SPI_CS3_N DO Chip select 3 for SPI on BLSP2

AY3 GPIO_6 P3 B-PD:nppukp Configurable I/O

BLSP2_1 B BLSP #2, bit 1; UART, SPI, or I2C

AV3 GPIO_7 P3 B-PD:nppukp Configurable I/O

BLSP2_0 B BLSP #2, bit 0; UART, SPI, or I2C

H5 GPIO_8 P3 B-PD:nppukp Configurable I/O

BLSP3_3 B BLSP #3, bit 3; SPI or I2C

G2 GPIO_9 P3 B-PD:nppukp Configurable I/O

BLSP3_2 B BLSP #3, bit 2; SPI or I2C

H1 GPIO_10 P3 B-PD:nppukp Configurable I/O

BLSP3_1 B BLSP #3, bit 1; SPI, or I2C

E2 GPIO_11 P3 B-PD:nppukp Configurable I/O

BLSP3_0 B BLSP #3, bit 0; SPI, or I2C

AM39 GPIO_12 P3 B-PD:nppukp Configurable I/O

BLSP4_3 B BLSP #4, bit 3; SPI, or I2C
GP_CLK_2B DO General-purpose clock output 2B

AM35 GPIO_13 P3 B-PD:nppukp Configurable I/O

BLSP4_2 B BLSP #4, bit 2; SPI, or I2C
GP_CLK_3B DO General-purpose clock output 3B

AN40 GPIO_14 P3 B-PD:nppukp Configurable I/O

BLSP4_1 B BLSP #4, bit 1; SPI, or I2C

AN36 GPIO_15 P3 B-PD:nppukp Configurable I/O

BLSP4_0 B BLSP #4, bit 0; SPI, or I2C

K7 GPIO_16 P3 B-PD:nppukp Configurable I/O

BLSP5_3 B BLSP #5, bit 3; SPI, or I2C
BLSP1_SPI_CS2_N DO Chip select 2 for SPI on BLSP1

G6 GPIO_17 P3 B-PD:nppukp Configurable I/O

BLSP5_2 B BLSP #5, bit 2; SPI, or I2C
BLSP2_SPI_CS2_N DO Chip select 2 for SPI on BLSP1

J6 GPIO_18 P3 B-PD:nppukp Configurable I/O

BLSP5_1 B BLSP #5, bit 1; SPI, or I2C

J4 GPIO_19 P3 B-PD:nppukp Configurable I/O

BLSP5_0 B BLSP #5, bit 0; SPI, or I2C

LM80-P0436-7 Rev. B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 41
Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Pin Definitions

Pad characteristics
Configurable
Pad # Pad name Functional description
function
Voltage Type

AY7 GPIO_20 P3 B-PD:nppukp Configurable I/O

BLSP6_3 B BLSP #6, bit 3; SPI, or I2C
GP_PDM_0A DO General-purpose PDM output 0A,
12-bit, XO/4 clock

AW6 GPIO_21 P3 B-PD:nppukp Configurable I/O

BLSP6_2 B BLSP #6, bit 2; SPI, or I2C
GP_PDM_1B DO General-purpose PDM output 1B,
12-bit, XO/4 clock

AV7 GPIO_22 P3 B-PD:nppukp Configurable I/O

BLSP6_1 B BLSP #6, bit 1; SPI, or I2C

BA2 GPIO_23 P3 B-PD:nppukp Configurable I/O

BLSP6_0 B BLSP #6, bit 0; SPI, or I2C

AT5 GPIO_24 P3 B-PD:nppukp Configurable I/O

MDP_VSYNC_P DI MDP vertical sync – primary

AU4 GPIO_25 P3 B-PD:nppukp Configurable I/O

DSI_RST_N DO Display reset
GP_PDM_0B DO General-purpose PDM output 0B,
12-bit, XO/4 clock

H3 GPIO_26 P3 B-PD:nppukp Configurable I/O

CAM_MCLK0 DO Camera master clock 0

C2 GPIO_27 P3 B-PD:nppukp Configurable I/O

CAM_MCLK1 DO Camera master clock 1

F1 GPIO_28 P3 B-PD:nppukp Configurable I/O

CAM1_RST_N DO Camera 1 (front camera) reset

B3 GPIO_29 P3 B-PD:nppukp Configurable I/O

CAM_I2C_SDA B Camera control interface I2C 0
serial data

F3 GPIO_30 P3 B-PD:nppukp Configurable I/O

CAM_I2C_SCL B Camera control interface I2C 0
serial Clock

D3 GPIO_31 P3 B-PD:nppukp Configurable I/O

CCI_TIMER0 DO Camera control interface timer 0
GP_CLK0 DO General-purpose clock 0

D1 GPIO_32 P3 B-PD:nppukp Configurable I/O

CCI_TIMER1 DO Camera control interface timer 1
GP_CLK1 DO General-purpose clock 1

G4 GPIO_33 P3 B-PD:nppukp Configurable I/O

CCI_ASYNC0 DI Camera control interface async 0

F5 GPIO_34 P3 B-PD:nppukp Configurable I/O

CAM0_STANDBY_N DO Camera 0 (rear camera) standby

LM80-P0436-7 Rev. B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 42
Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Pin Definitions

Pad characteristics
Configurable
Pad # Pad name Functional description
function
Voltage Type

A4 GPIO_35 P3 B-PD:nppukp Configurable I/O

CAM0_RST_N DO Camera 0 (rear camera) reset

C4 GPIO_36 P3 B-PD:nppukp Configurable I/O

FLASH_LED_RESET DO LED Flash reset

E4 GPIO_37 P3 B-PD:nppukp Configurable I/O

BLSP3_SPI_CS2_N DO Chip select 2 for SPI on BLSP3
FORCED_USB_BOOT DI Force USB boot control

B37 GPIO_38 P3 B-PD:nppukp Configurable I/O

SD_CARD_DET_N DI Secure digital card detection
CCI_TIMER2 DO Camera control interface timer 2

BC2 GPIO_39 P3 B-PD:nppukp Configurable I/O

BT_SSBI B Bluetooth single-wire serial bus
interface

BB5 GPIO_40 P3 B-PD:nppukp Configurable I/O

WLAN_DATA2 B WLAN data bit 2

BB1 GPIO_41 P3 B-PD:nppukp Configurable I/O

WLAN_DATA1 B WLAN data bit 1

BD3 GPIO_42 P3 B-PD:nppukp Configurable I/O

WLAN_DATA0 B WLAN data bit 0

BA6 GPIO_43 P3 B-PD:nppukp Configurable I/O

WLAN_SET DO-Z WLAN set

BB3 GPIO_44 P3 B-PD:nppukp Configurable I/O

WLAN_CLK DO-Z WLAN clock

AY5 GPIO_45 P3 B-PD:nppukp Configurable I/O

FM_SSBI B FM-radio SSBI

AY9 GPIO_46 P3 B-PD:nppukp Configurable I/O

FM_DATA B FM radio serial data interface

BA4 GPIO_47 P3 B-PD:nppukp Configurable I/O

BT_CTL DO Bluetooth control

AW8 GPIO_48 P3 B-PD:nppukp Configurable I/O

BT_DATA B Bluetooth dual function: data and
strobe

Y37 GPIO_49 P4 B-PD:nppukp Configurable I/O

UIM3_DATA B UIM3 data
GP_CLK_1A DO General-purpose clock output 1A

AA34 GPIO_50 P4 B-PD:nppukp Configurable I/O

UIM3_CLK DO UIM3 clock
GP_CLK_2A DO General-purpose clock output 2A

LM80-P0436-7 Rev. B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 43
Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Pin Definitions

Pad characteristics
Configurable
Pad # Pad name Functional description
function
Voltage Type

Y35 GPIO_51 P4 B-PD:nppukp Configurable I/O

UIM3_RST DO UIM3 reset
GP_CLK_3A DO General-purpose clock output 3A

AA38 GPIO_52 P3 B-PD:nppukp Configurable I/O

UIM3_PRESENT DI UIM3 removal detection
GP_PDM_1A DO General-purpose PDM output 1A,
12-bit, XO/4 clock

L40 GPIO_53 P6 B-PD:nppukp Configurable I/O

UIM2_DATA B UIM2 data

K39 GPIO_54 P6 B-PD:nppukp Configurable I/O

UIM2_CLK DO UIM2 clock

H39 GPIO_55 P6 B-PD:nppukp Configurable I/O

UIM2_RST DO UIM2 reset

AA36 GPIO_56 P3 B-PD:nppukp Configurable I/O

UIM2_PRESENT DI UIM2 removal detection

G40 GPIO_57 P5 B-PD:nppukp Configurable I/O

UIM1_DATA B UIM1 data

J40 GPIO_58 P5 B-PD:nppukp Configurable I/O

UIM1_CLK DO UIM1 clock

L38 GPIO_59 P5 B-PD:nppukp Configurable I/O

UIM1_RST DO UIM1 reset

Y39 GPIO_60 P3 B-PD:nppukp Configurable I/O

UIM1_PRESENT DI UIM1 removal detection

AL38 GPIO_61 P3 B-PD:nppukp Configurable I/O

UIM_BATT_ALARM DI UIM battery alarm

G34 GPIO_62 P3 B-PD:nppukp Configurable I/O

SMB_INT DI SMB interrupt

AJ40 GPIO_63 P3 B-PD:nppukp Configurable I/O

CDC_PDM0_CLK1 DO PDM0 Clock

AH39 GPIO_64 P3 B-PD:nppukp Configurable I/O

CDC_PDM0_SYNC1 DO PDM0 sync signal

AK39 GPIO_65 P3 B-PD:nppukp Configurable I/O

CDC_PDM0_TX01 DI PDM0 Transmit signal 0

AJ38 GPIO_66 P3 B-PD:nppukp Configurable I/O

CDC_PDM0_RX01 DO PDM0 Receive signal 0

AK35 GPIO_67 P3 B-PD:nppukp Configurable I/O

CDC_PDM0_RX11 DO PDM0 Receive signal 1

LM80-P0436-7 Rev. B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 44
Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Pin Definitions

Pad characteristics
Configurable
Pad # Pad name Functional description
function
Voltage Type

AL40 GPIO_68 P3 B-PD:nppukp Configurable I/O

CDC_PDM0_RX21 DO PDM0 Receive signal 2

L36 GPIO_69 P3 B-PD:nppukp Configurable I/O

MAG_INT DI Magnometer interrupt
BLSP3_SPI_CS3_N DO Chip select 3 for SPI on BLSP3

AN38 GPIO_70 P3 B-PD:nppukp Configurable I/O

AR38 GPIO_71 P3 B-PD:nppukp Configurable I/O

AT39 GPIO_72 P3 B-PD:nppukp Configurable I/O

AU40 GPIO_73 P3 B-PD:nppukp Configurable I/O

AP37 GPIO_74 P3 B-PD:nppukp Configurable I/O

AV39 GPIO_75 P3 B-PD:nppukp Configurable I/O

AP35 GPIO_76 P3 B-PD:nppukp Configurable I/O

BC4 GPIO_77 P3 B-PD:nppukp Configurable I/O

BE4 GPIO_78 P3 B-PD:nppukp Configurable I/O

BC6 GPIO_79 P3 B-PD:nppukp Configurable I/O

BD5 GPIO_80 P3 B-PD:nppukp Configurable I/O

BOOT_CONFIG_0 DI Boot configuration control bit 0
(WDOG_DISABLE)

BD7 GPIO_81 P3 B-PD:nppukp Configurable I/O

BOOT_CONFIG_1 DI Boot configuration control bit 1

BC38 GPIO_82 P3 B-PD:nppukp Configurable I/O

BOOT_CONFIG_2 DI Boot configuration control bit 2

BC40 GPIO_83 P3 B-PD:nppukp Configurable I/O

BOOT_CONFIG_3 DI Boot configuration control bit 3

BC8 GPIO_84 P3 B-PD:nppukp Configurable I/O

BOOT_CONFIG_4 DI Boot configuration control bit 4

BE6 GPIO_85 P3 B-PD:nppukp Configurable I/O

SDC1_EMMC_1P2_EN DI Enables 1.2 V I/O for eMMC on
SDC1

BD39 GPIO_86 P3 B-PD:nppukp Configurable I/O

BOOT_CONFIG_5 DI Boot configuration control bit 5

BB37 GPIO_87 P3 B-PD:nppukp Configurable I/O

BOOT_CONFIG_6 DI Boot configuration control bit 6

LM80-P0436-7 Rev. B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 45
Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Pin Definitions

Pad characteristics
Configurable
Pad # Pad name Functional description
function
Voltage Type

BB35 GPIO_88 P3 B-PD:nppukp Configurable I/O

BOOT_CONFIG_7 DI Boot configuration control bit 7

BD35 GPIO_89 P3 B-PD:nppukp Configurable I/O

BOOT_CONFIG_8 DI Boot configuration control bit 8

BA32 GPIO_90 P3 B-PD:nppukp Configurable I/O

BOOT_CONFIG_9 DI Boot configuration control bit 9

BE38 GPIO_91 P3 B-PD:nppukp Configurable I/O

BOOT_CONFIG_10 DI Boot configuration control bit 10

AY33 GPIO_92 P3 B-PD:nppukp Configurable I/O

BOOT_CONFIG_11 DI Boot configuration control bit 11

BD33 GPIO_93 P3 B-PD:nppukp Configurable I/O

BOOT_CONFIG_12 DI Boot configuration control bit 12

BC34 GPIO_94 P3 B-PD:nppukp Configurable I/O

BOOT_CONFIG_13 DI Boot configuration control bit 13

BB31 GPIO_95 P3 B-PD:nppukp Configurable I/O

BC32 GPIO_96 P3 B-PD:nppukp Configurable I/O

EXT_GNSS_LNA_EN DO External GNSS LNA enable

C38 GPIO_97 P3 B-PD:nppukp Configurable I/O

LCD_DRIVER_5V_EN DO 5 V display driver enable
GP_CLK_1B DO General-purpose clock output 1B
BOOT_CONFIG_14 DI Boot configuration control bit 14

A38 GPIO_98 P3 B-PD:nppukp Configurable I/O

LCD_BL_EN DO Display backlight enable
GP_PDM_2A DO General-purpose PDM 2A output

BE34 GPIO_99 P3 B-PD:nppukp Configurable I/O

BE36 GPIO_100 P3 B-PD:nppukp Configurable I/O

BB33 GPIO_101 P3 B-PD:nppukp Configurable I/O

BE32 GPIO_102 P3 B-PD:nppukp Configurable I/O

AT35 GPIO_103 P3 B-PD:nppukp Configurable I/O

SSBI_WTR0_RX B SSBI 1 for RFIC 0

AW40 GPIO_104 P3 B-PD:nppukp Configurable I/O

SSBI_WTR0_TX B SSBI 2 for RFIC 0

AU36 GPIO_105 P3 B-PD:nppukp Configurable I/O

SSBI_WTR1_RX B SSBI 1 for RFIC 1

AY39 GPIO_106 P3 B-PD:nppukp Configurable I/O

SSBI_WTR1_TX B SSBI 2 for RFIC 1

LM80-P0436-7 Rev. B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 46
Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Pin Definitions

Pad characteristics
Configurable
Pad # Pad name Functional description
function
Voltage Type

H33 GPIO_107 P3 B-PD:nppukp Configurable I/O

KYPD_SNS0 DI Keypad sense bit 0

K35 GPIO_108 P3 B-PD:nppukp Configurable I/O

KYPD_SNS1 DI Keypad sense bit 1

J34 GPIO_109 P3 B-PD:nppukp Configurable I/O

KYPD_SNS2 DI Keypad sense bit 2

B39 GPIO_110 P3 B-PD:nppukp Configurable I/O

BLSP1_SPI_CS1_N DO Chip select 1 for SPI on BLSP1
MI2S_1_WS B MI2S #1 word select (L/R)
GP_MN DO General-purpose M/N:D counter
USB_HS_ID DI output
USB ID pin for host mode detection

C40 GPIO_111 P3 B-PU:nppukp Configurable I/O

AW36 GPIO_112 P3 B-PD:nppukp Configurable I/O

MI2S_2_D1 B MI2S #2 serial data channel 1

D39 GPIO_113 P3 B-PD:nppukp Configurable I/O

MI2S_1_SCLK B MI2S #1 bit clock
GP_PDM_2B DO General-purpose PDM 2B output

E40 GPIO_114 P3 B-PD:nppukp Configurable I/O

MI2S_1_D0 B MI2S #1 serial data channel 0

E38 GPIO_115 P3 B-PD:nppukp Configurable I/O

GYRO_ACCEL_INT_N DI Gyro interrupt
MI2S_1_D1 B MI2S #1 serial data channel 1

AW38 GPIO_116 P3 B-PD:nppukp Configurable I/O

MI2S_1_MCLK DO MI2S #1 master clock

AV37 GPIO_117 P3 B-PD:nppukp Configurable I/O

MI2S_2_WS B MI2S #2 word select (L/R)

AR36 GPIO_118 P3 B-PD:nppukp Configurable I/O

MI2S_2_SCLK B MI2S #2 bit clock

BA40 GPIO_119 P3 B-PD:nppukp Configurable I/O

MI2S_2_D0 B MI2S #2 serial data channel 0

F39 GPIO_120 P3 B-PD:nppukp Configurable I/O

BLSP3_SPI_CS1_N DO Chip select 1 for SPI on BLSP3

G38 GPIO_121 P3 B-PD:nppukp Configurable I/O

BLSP2_SPI_CS1_N DO Chip select 2 for SPI on BLSP2

1 This is a PDM interface specific to the QC Codec used in this chipset, as opposed to the general purpose
PDM available on another set of IOs.

LM80-P0436-7 Rev. B MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 47
Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Pin Definitions

NOTE: GPIO pins can support multiple functions. To assign GPIOs to particular functions (such as the
options listed in the table above), designers must identify all their application’s requirements and
map each GPIO to its function – carefully avoiding conflicts in GPIO assignments. Refer to
Table 2-10 for a list of all supported functions for each GPIO.

NOTE: System designers must examine each GPIO’s external connection and programmed configuration,
and take necessary steps to avoid excessive leakage current. Combinations of the following
factors must be controlled properly:

– GPIO configuration
• Input versus output
• Pull-up or pull-down
– External connections
• Unused inputs
• Connections to high-impedance (tri-state) outputs
• Connections to external devices that may not be attached

To help designers define their products’ GPIO assignments, an Excel spreadsheet is provided that
lists all APQ8016 GPIOs (in numeric order), pad numbers, pad voltages, pull states, and available
configurations.
You can download this spreadsheet APQ8016 GPIO Pin Assignments (LM80-P0436-6) at:
https://www.qualcomm.com/products/snapdragon/embedded-computing.

Table 2-11 Pin descriptions – No connection, do not connect, and reserved pins

Functional
Pad # Pad name
description

A2, A40, AB11, AB19, AB23, AC6, AD1, AD23, AD27, AD3, AD31, AD5, AJ6, NC No connect; not
AK25, AK27, AK3, AK5, AL4, AL6, AM27, AM5, AM7, AN2, AN4, AN6, AP25, connected internally
AP3, AP5, AP7, AT1, AT17, AT19, AT21, AT25, AT3, AU16, AU18, AU2, AU20,
AU24, AV21, AV23, AV25, AV27, AV29, AV31, AW16, AW18, AW20,AW22,
AW24, AW26, AW28, AW30, AW32, AY19, AY25, AY29, B1, BA18, BA20, BA24,
BA30, BB15, BB17, BB21, BB29, BB9, BC16, BC20, BC30, BD1, BD15, BD21,
BD29, BD9, BE14, BE2, BE20, BE40, D33, D37, F15, F17, F21, G22, G26, H11,
H13, H15, H19, H23, H25, H27, H29, H31, H7, M19, P19, P23, P25, AA40

BA36, AY35, AN8, AY15, AY17, BA14, BA16 DNC Do not connect;
connected internally, do
not connect externally

Table 2-12 Pin descriptions – power supply pins

Pad # Pad name Functional description

AP17 VDD_A1 Power for analog circuits – low voltage

AP19 GND GND for APQ

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Pin Definitions

Pad # Pad name Functional description

AR18, AR20 VDD_A2 Power for analog circuits – high voltage

AR22, AR24 GND GND for APQ

AB25, AB27, AB29, AB31, K29, K31, K33, M23, M25, M27, VDD_APC Power for applications microprocessors
M29, M31, M33, P27, P29, P31, P33, T25, T27, T29, T33,
V25, V27, V29, V31, V33, Y25, Y27, Y29, Y31

AF31, U8, AD13, AD15, AD17, AD25, AD29, AH11, AH17, VDD_CORE Power for digital core circuits
AH19, AH21, AM17, AM19, AR10, M11, M21, M9, T11,
T21, T9, U22, U24, Y11, Y13, Y15, Y17, Y9

AD11, AG28, AH13, AH15, AH23, AH25, AH27, AH29, VDD_MEM Power for on-chip memory
AJ28, AL28, AM11, AM9, AN28, AP29, AU10, K25, M15,
N14, T13, T15, T23, T31, Y19, J28, K27, M13, M17, AP27

AE6, AE8, AB9, AC8 VDD_MIPI Power for MIPI circuits (CSI and DSI)

AH5 VDD_MIPI_DSI_PLL Power for MIPI _DSI PHY PLL

J10, J14, J20, J22, J24, J30, K11, K15, K19, K23 VDD_P1 Power for pad group 1 – EBI pads

W8 VDD_P2 Power for pad group 2 – SDC2 pads

AA32, AG32, AK9, AP33, AT11, AT33, AT7, AU30, AU34, VDD_P3 Power for pad group 3 – most I/O pads
AU8, F31, H17, J8, V7

AB35 VDD_P4 Power for pad group 4 – UIM3 pads

L34 VDD_P5 Power for pad group 5 – UIM1 pads

AC34 VDD_P6 Power for pad group 6 – UIM2 pads

AF33 VDD_P7 Power for pad group 7 – SDC1 pads

Y21, AG16, AE22 VDD_PLL1 Power for PLL circuits – low voltage

W24, AP23, AN14 VDD_PLL2 Power for PLL circuits – high voltage

AJ8 VDD_QFPROM_PRG Power for programming the QFPROM;

otherwise GND

AE30 VDD_USB_HS Power for USB PHY interface – digital

voltage

AD33 VDD_USBPHY_1P8 Power for USB PHY interface – low

voltage

AC32 VDD_USBPHY_3P3 Power for USB PHY interface – high

voltage

AT15 VDD_WLAN Power for WLAN ADC circuits

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Pin Definitions

Table 2-13 Pin descriptions – ground pins

Pad Functional
Pad #
name description

A12, A16, A22, A28, A32, A6, AA24, AA26, AA28, AA30, AA4, AA8, AB13, AB15, AB17, AB21, GND Ground
AC30, AC4, AD19, AD21, AD7, AE16, AE20, AF11, AF13, AF15, AF17, AF19, AF21, AF23, AF25,
AF27, AF29, AF5, AF9, AG18, AG20, AH31, AH7, AH9, AJ2, AJ34, AJ4, AK11, AK13, AK15,
AK17, AK19, AK21, AK23, AK29, AK31, AK33, AK7, AL30, AL8, AM1, AM13, AM15, AM21, AM23,
AM25, AM29, AM3, AM31, AM33, AN20, AP9, AR26, AR4, AR6, AT13, AT23, AT27, AT29, AU12,
AU22, AU26, AU28, AU38, AU6, AV11, AV13, AV15, AV17, AV19, AV33, AV5, AV9, AW10,
AW12, AW14, AW2, AW34, AW4, AY11, AY13, AY21, AY23, AY27, B5, BA12, BA22, BA26,
BA28, BA8, BB19, BB23, BB25, BB27, BB7, BC12, BC18, BC22, BC24, BC26, BC28, BC36,
BD13, BD17, BD19, BD23, BD25, BD27, BD37, BE10, BE16, BE18, BE22, BE24, BE26, BE28,
BE8, C18, C20, C32, C8, D27, D5, D7, E12, F19, F25, F27, F29, F37, F7, G10, G12, G14, G16,
G18, G20, G24, G28, G30, G32, G8, H35, H37, J16, J18, J32, J36, J38, K17, K21, K37, K5, K9,
L30, L32, L4, L6, L8, M35, M37, M39, M5, M7, N2, N22, N24, N26, N28, N30, N32, N34, N36,
N38, N4, N40, N8, P11, P13, P15, P17, P21, P35, P37, P39, P5, P9, R22, R24, R26, R28, R30,
R32, R34, R36, R38, R40, R8, T17, T19, T3, T35, T37, T39, T5, U26, U28, U30, U32, U34, U36,
U38, U40, V11, V13, V15, V17, V19, V21, V23, V3, V35, V37, V39, W16, W22, W26, W28, W30,
W32, W34, W36, W38, W4, W40, Y23, Y3

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 3 Electrical Specifications

3.1 Absolute maximum ratings

Absolute maximum ratings (Table 3-1) reflect conditions that the APQ8016 device may be
exposed to beyond the operating limits, without experiencing immediate functional failure. They
are limiting values, to be considered individually when all other parameters are within their
specified operating ranges. Functionality and long-term reliability can be expected only within
the operating conditions, as described in Section 3.2.

Table 3-1 Absolute maximum ratings

Parameter Min Max Unit

Power-supply voltages

VDD_A1 Analog circuits -0.30 1.56 V

VDD_A2 Analog circuits -0.30 2.16 V

VDD_APC Application microprocessors -0.30 1.62 V

VDD_CORE Digital core circuits -0.30 1.55 V

VDD_MEM On-chip memory -0.30 1.55 V

VDD_MIPI_DSI_PLL Power for MIPI_DSI PHY PLL -0.30 2.16 V

VDD_P1 Digital pad circuits -0.30 1.44 V

VDD_P2 Digital pad circuits – 2.95 V -0.30 3.25 V

Digital pad circuits – 1.80 V -0.30 2.16

VDD_P3 Digital pad circuits -0.30 2.16 V

VDD_P4 Digital pad circuits – 2.95 V -0.30 3.25 V

Digital pad circuits – 1.80 V -0.30 2.16

VDD_P5 Digital pad circuits – 2.95 V -0.30 3.25 V

Digital pad circuits – 1.80 V -0.30 2.16

VDD_P6 Digital pad circuits – 2.95 V -0.30 3.25 V

Digital pad circuits – 1.80 V -0.30 2.16

VDD_P7 Digital pad circuits -0.30 2.45 V

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Electrical Specifications

Parameter Min Max Unit

VDD_PLL1 PLL circuits -0.30 1.55 V

VDD_PLL2 PLL circuits -0.30 2.16 V

VDD_QFPROM_PRG QFPROM programming voltage -0.30 2.16 V

VDD_USBPHY_1P8 USB PHY low-voltage circuit -0.30 2.16 V

VDD_USBPHY_3P3 USB PHY high-voltage circuit -0.30 3.63 V

VDD_USB_HS Core circuits for USB -0.30 1.55 V

VDD_WLAN WLAN ADC circuits -0.30 1.56 V

Signal pins

V_IN Voltage on any non-power input pin -0.3 Vxx + 20% 1 V

VIN_P7 Voltage on any eMMC input pin -0.30 2.45 V

I_IN Latch-up current -100 100 mA

ESD protection – see Section 7.1

Thermal conditions – see Section 4.5

1. VXX is the supply voltage associated with the input or output pin to which the test voltage is applied.

3.2 Operating conditions

Operating conditions include parameters that are under the control of the design team:
power-supply voltage, power-distribution impedances, and thermal conditions (Table 3-3). The
APQ8016 meets all performance specifications listed in Section 3.3 through Section 3.12 when
used within the operating conditions, unless otherwise noted in those sections (provided the
absolute maximum ratings have never been exceeded).

Table 3-2 Operating conditions for APC and CORE rails 1

Parameter Min Typ Max Unit

VDD_APC Quad Cortex A53 (operating at a maximum

frequency of 1.15+ GHz)
 Turbo mode3 1.07 – 1.42 V
 Nominal mode 0.97 – 1.22 V
 SVS mode2 0.97 1.05 1.12 V

VDD_CORE  Turbo mode3 1.05 – 1.36 V

 Nominal mode 0.93 – 1.22 V
 SVS mode 0.84 – 1.12 V
1 Parts with voltages outside the specified ranges are not guaranteed to operate properly
2 AVS type I is not enabled on the APC rail in SVS mode

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Electrical Specifications

3 APQ8016 supports voltage rail scaling to save power according to dynamic system performance
requirements. Turbo mode is used to enable critical system busses such as the core CPUS, the
Graphics core, and the memory bus interface to reach peak frequency operational targets as required
by system loading.

Table 3-3 Operating conditions

Parameter Min Typ 2 Max Unit

Power-supply voltages

VDD_A1 Power for analog circuits – low voltage for PA 1.25 1.3 1.35 V
DAC and Tx DAC circuits
VDD_WLAN Power for WLAN ADC circuits

VDD_MEM Power supply for internal memory cores

VDD_PLL1 Power for PLL circuits – low voltage
VDD_USB_HS Power for USB core circuits
 Turbo mode3 1.22 1.2875 1.33 V
 Nominal mode 1.10 1.15 1.19 V
 SVS mode 1.00 1.05 1.09 V

VDD_PLL2 Power for PLL circuits – high voltage 1.72 1.80 1.93 V
VDD_A2 Power for analog circuits – high voltage for
analog baseband receiver and SVideo circuits
VDD_USBPHY_1P8 Power for USB PHY interface – low voltage

VDD_P1 Power for pad group 1 – EBI pads 1.15 1.20 1.25 V
VDD_MIPI Power for MIPI circuits (CSI and DSI)

VDD_P2 Power for pad group 2

SDC2 pads low voltage 1.67 1.8 1.93 V
SDC2 pads high voltage 2.75 2.95 3.04 V

VDD_P3 Power for pad group 3 – most I/O pads 1.67 1.8 1.93 V

VDD_P4 Power for pad group 4

UIM3 pads low voltage 1.67 1.8 1.93 V
UIM3 pads high voltage 2.75 2.95 3.04 V

VDD_P5 Power for pad group 5

UIM1 pads low voltage 1.67 1.8 1.93 V
UIM1 pads high voltage 2.75 2.95 3.04 V

VDD_P6 Power for pad group 6

UIM2 pads low voltage 1.67 1.8 1.93 V
UIM2 pads high voltage 2.75 2.95 3.04 V

VDD_P7 Power for pad group 7 – SDC1 pads 1.67 1.8 1.93 V

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Electrical Specifications

Parameter Min Typ 2 Max Unit

VDD_MIPI_DSI_PLL Power for MIPI_DSI PHY PLL 1.72 1.8 1.95 V

VDD_QFPROM_PRG Power for programming the QFPROM; 1.67 1.8 1.93 V

otherwise ground

VDD_USBPHY_3P3 Power for USB PHY interface – high voltage 2.97 3.08 3.50 V

Thermal conditions

TC Device operating temperature (case) -30 +25 +85 °C

TA 1 3GPP2-mode operating temperature (ambient) -30 +25 +60 °C

3GPP-mode operating temperature (ambient) -20 +25 +60 °C

1
These temperature ranges are defined by the 3GPP2 system specification.
2 Typical voltages represent the recommended output settings of the companion PMIC device.
3 APQ8016 supports voltage rail scaling to save power according to dynamic system performance

requirements. Turbo mode is used to enable critical system busses such as the core CPUS, the
Graphics core, and the memory bus interface to reach peak frequency operational targets as required
by system loading.

3.2.1 Core voltage minimization (retention mode)

The MPM supports VDD minimization, also known as VDD_CORE retention mode. This
technique reduces the leakage of the digital logic by reducing VDD to the minimum required to
maintain the register and memory state.
The V(MIN) for state retention is found through characterization. As in any normal distribution,
retention voltages vary across devices. Three fuses are blown to set the core voltage in retention
mode. These fuses are used by software. The fuse locations in Table 3-4 refer to register
0x0005C00C SECURITY_CONTROL_CORE_QFPROM_CORR_PTE2.

Table 3-4 Core voltage in retention mode

VDD_CORE Bit 7 (MSB) Bit 6 Bit 5 (LSB)

0.65 V 0 0 0

0.5 V 0 0 1

0.65 V 0 1 1

3.3 Power delivery network specification

This section covers the power delivery network (PDN) maximum impedance specification.

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Electrical Specifications

3.3.1 PDN system specification (PCB + baseband IC)

Table 3-5 lists the PCB + baseband IC PDN requirements. Meeting this specification requires the
use of a commercial circuit simulator program (e.g., ADS) and the APQ8016 S-parameter model.

Table 3-5 PCB + baseband IC PDN impedance vs. frequency

Required PCB routing Max impedance

Power domain inductance
(caps shorted) 1 DC to 10 Hz 10 Hz to 10 MHz 10–500 MHz

VDD_MEM 500 pH max. 11 mΩ 104 mΩ 250 mΩ

VDD_CORE 250 pH 5 mΩ 79 mΩ 160 mΩ

VDD_APC 200 pH 4 mΩ 45 mΩ 140 mΩ

1 Meeting the PCB routing inductance is the required starting point to reap maximum benefits from the PDN
capacitor optimization process.

3.3.2 PDN specification (PCB-only)

Table 3-6 lists the PCB-only PDN requirements. Refer to this specification only if a commercial
circuit simulator program (e.g., ADS) is not available.

Table 3-6 PCB-only PDN impedance vs. frequency

Pin number of Pin number of negative

Max impedance
Power positive ports ports
domain
DC to 10 Hz 10 Hz to 25 MHz

VDD_MEM 11 mΩ 78 mΩ All VDD_MEM pins All GND pins

VDD_CORE 5 mΩ 78 mΩ All VDD_CORE pins All GND pins

VDD_APC 4 mΩ 45 mΩ All VDD_APC pins All GND pins

VDD_P1 35 mΩ 141 mΩ J10, J14, K11 G10, G12, G14, G16, K9, J16

141 mΩ J20, J22 G18, G20, G24, J18, K21

141 mΩ J24, K23 G24, K21

141 mΩ K15, K19 K17, K21

141 mΩ J30 G28, G30, G32, J32

NOTE: The PDN DC specification for VDD_P1 applies for both APQ and external memory domains
powered by VREG_L2_1P2 under the assumption that the maximum current drawn by memory
device is 250 mA. The PDN AC specification for VDD_P1 applies only for APQ domain
powered by VREG_L2_1P2.

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Electrical Specifications

3.4 DC power characteristics

3.4.1 Dhrystone and rock bottom maximum power

Table 3-7 lists values for Dhrystone and rock bottom power specifications.

Table 3-7 Dhrystone and rock bottom power specifications

APQ version Dhrystone (W) at 85°C (Tj) 1 2 3 Rock bottom (mW) at 25°C (Tj) 3

APQ8016 (1.15+ GHz) 3.78 11.8

1 Dhrystone should be measured using the QTI custom Dhrystone script that will be provided upon request.
2 The Dhrystone specification applies only to APQ8016 CS devices. Dhrystone should be run and measured

on all four cores together.

3 Rock bottom (VDD_CORE and VDD_MEM) should be measured at VDD_CORE and VDD_MEM rails

when VDD_CORE and VDD_MEM are at retention voltage.

3.5 Power sequencing

The PM8916 includes poweron circuits that provide the proper power sequencing for the entire
APQ8016 chipset. The supplies are turned on as groups of regulators that are selected by the
hardware configuration of some PMIC pins.
A high-level summary of the required poweron sequence:
 VDD_MEM (on-chip memory), VDD_PLL1
 VDD_CORE (digital core circuits)
 VDD_APC (Cortex A53 microprocessor)
 VREF_SDC (SDC reference voltage)
 VDD_P3 (I/Os), VDD_P7 (SDC1), VDD_DDR_1P8
 VDD_USBPHY_1P8, VDD_PLL2
 VDD_P1 (EBI and DDR I/Os), VDD_DDR_1P2
 VREG_XO
 EBI0_VREF_XX (LPDDR2/3 reference voltage)
 VDD_USB_3P3
 VDD_QFPROM_PRG, VDD_P2 (SDC2)
Comments regarding this sequence:
 The core voltage (VDD_CORE) needs to power up before the pad circuits (VDD_Px), so that
internal circuits can take control of the I/Os and pads.
 If pad voltages power up first, the output drivers might be stuck in unknown states, and might
cause large leakage currents until VDD_CORE powers on.
 The general-purpose pad voltage (VDD_P3) needs to precede the analog voltages
(VDD_Ax), since the SSBIs are initialized to their default states before VDD_Ax powers up
(analog circuits are controlled by SSBI).

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Electrical Specifications

 Other non-critical supplies are included within the poweron sequence. Any other desired
supplies can be powered on by software after the sequence is completed.
 Each domain needs to reach its 90% value before the next domain starts ramping up. For
example, when VDD_MEM reaches 90% of its value, then the VDD_CORE supply can start
ramping up.

3.6 Digital logic characteristics

A digital I/O’s performance specification depends upon its pad type, its usage, and/or its supply
voltage:
 Some are dedicated for interconnections between the APQ8016 and other ICs within the
chipset, and therefore do not require specification.
 Some are defined by existing standards (such as I2C, SPI, etc). This device complies with
those standards and additional specifications are not required.
 All other digital I/Os require performance specifications, and are organized within this
section as described in Table 3-8.

Table 3-8 Digital I/Os specified in this section

Pad voltage Usage Table

1.2 V EBI0 (P1) Table 3-9

1.8 V GPIO (P3) Table 3-10

Dual- V SDC2 (P2), GPIO (P5, P6, P4), UIM1 (P5), UIM2 (P6), UIM3 (P4) Table 3-11
(1.8 V/2.95 V)

Dual- V SDC1(P7) Table 3-12

(1.2 V/1.8 V)

Table 3-9 1.2 V digital I/O characteristics

Parameter Comments Min Max Unit

EBI0 pads only (as identified in Table 3-8)

VREF Reference voltage 0.49 * VDD_Px 0.51 * VDD_Px V

VIH High-level input voltage CMOS/Schmitt VREF + 0.13 – V

VIL Low-level input voltage CMOS/Schmitt – VREF - 0.13 V

IIH Input high leakage current No pull-down – 2 µA

IIL Input low leakage current No pull-up -2 – µA

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Electrical Specifications

Parameter Comments Min Max Unit

IIHPD Input high leakage current 40 200 µA

with pull-down

IILPU Input low leakage current -200 -40 µA

with pull-up

IOZHKP High-level, tri-state leakage -120 -10 µA

current with keeper

IOZLKP Low-level, tri-state leakage 10 120 µA

current with keeper

VOH High-level output voltage CMOS, at rated drive 0.9 * VDD_Px – V

strength1

VOL Low-level output voltage CMOS, at rated drive – 0.1 * VDD_Px V

strength1

CI/O I/O capacitance2 1.25 2.50 pF

1 Refer to Table 2-1 for each output pin’s drive strength (IOH and IOL); the drive strengths of many output

pins are programmable, and depend on the associated supply voltage.

2 Input capacitance and I/O capacitance values are guaranteed by design, but not 100% tested.

Table 3-10 1.8 V digital I/O characteristics

Parameter Comments Min Max Unit

GPIO (P3) (as identified in Table 3-8)

VIH High-level input voltage CMOS/Schmitt 0.65 * VDD_Px – V

VIL Low-level input voltage CMOS/Schmitt – 0.35 * VDD_Px V

VOH High-level output voltage CMOS, at rated drive VDD_Px - 0.45 V

strength1

VOL Low-level output voltage CMOS, at rated drive – 0.45 V

strength3

RP Pull resistance2 Pull-up and pull-down 55 390 kΩ

RK Keeper resistance2 30 150 kΩ

IIH Input high leakage current3 No pull-down – 1 µA

IIL Input low leakage current4 No pull-up -1 – µA

VSHYS Schmitt hysteresis voltage 100 – mV

CI/O I/O capacitance – 5 pF

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Electrical Specifications

Parameter Comments Min Max Unit

RFFE & SPMI pins

VIH High-level input voltage CMOS/Schmitt 0.65 * VDD_PX – V

VIL Low-level input voltage CMOS/Schmitt – 0.35 * VDD_Px V

VOH High-level output voltage CMOS, at rated drive 0.8 * VDD_PX V

strength

VOL Low-level output voltage CMOS, at rated drive – 0.2 * VDD_Px V

strength

RP Pull resistance Pull-up and pull-down 10 50 kΩ

RK Keeper resistance 10 50 kΩ

IIH Input high leakage current No pull-down – 1 µA

IIL Input low leakage current No pull-up -1 – µA

VSHYS Schmitt hysteresis voltage 165 – mV

1 Refer to Table 2-1 for each output pin’s drive strength (IOH and IOL); the drive strengths of many output
pins are programmable, and depend on the associated supply voltage.
2 Refer to Table 2-1 for pull-up, pulldown, and keeper options for each pad (where appropriate).
3 Pad voltage = VDD_Px max.
4 Over all valid pad voltages.

Table 3-11 Dual-voltage 1.8 V/2.95 V digital I/O characteristics

Parameter Comments Min Max Unit

Common to dual-voltage pads 1.8 V/2.95 V (as identified in Table 3-8)

RP Pull resistance1 Pull-up and pull-down 10 100 kΩ

RK Keeper resistance1 10 100 kΩ

VSHYS Schmitt hysteresis voltage 100 – mV

CI/O IO capacitance – 5 pF

Common to SDC2 pad and UIM pad at 2.95 V only (as identified in Table 3-8)

IIH Input high leakage current No pull-down – 10 µA

IIL Input low leakage current No pull-up -10 – µA

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Electrical Specifications

Parameter Comments Min Max Unit

Common to UIM pads, either voltage (as identified in Table 3-8)

VIH High-level input voltage CMOS/Schmitt 0.7 * VDD_Px VDD_Px + 0.3 V

VIL Low-level input voltage CMOS/Schmitt -0.3 0.2 * VDD_Px V

VOH High-level output voltage CMOS, at rated drive 0.8 * VDD_Px VDD_Px V
strength2

VOL Low-level output voltage CMOS, at rated drive 0 0.4 V

strength2

SDC2 pads at 2.95 V only (as identified in Table 3-8)

VIH High-level input voltage CMOS/Schmitt 0.625 * VDD_Px VDD_Px + 0.3 V

VIL Low-level input voltage CMOS/Schmitt -0.3 0.25 * VDD_Px V

VOH High-level output voltage CMOS, at rated drive 0.75 * VDD_Px VDD_Px V
strength 2

VOL Low-level output voltage CMOS, at rated drive 0 0.125 * VDD_Px V

strength2

Common to SDC2 pad and UIM pad at 1.8 V only (as identified in Table 3-8)

IIH Input high leakage current No pull-down – 2 µA

IIL Input low leakage current No pull-up -2 – µA

SDC2 pads at 1.8 V only (as identified in Table 3-8)

VIH High-level input voltage CMOS/Schmitt 1.27 2 V

VIL Low-level input voltage CMOS/Schmitt -0.3 0.58 V

VOH High-level output voltage CMOS, at rated drive 1.4 V

strength

VOL Low-level output voltage CMOS, at rated drive 0 0.45 V

strength
1 Refer to Table 2-1 for pull-up, pull-down, and keeper options for each pad (where appropriate).
2 Refer to Table 2-1 for each output pin’s drive strength (IOH and IOL); the drive strengths of many output
pins are programmable, and depend on the associated supply voltage.

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Electrical Specifications

Table 3-12 Dual-voltage 1.2 V/1.8 V digital I/O characteristics

Parameter Comments Min Max Unit

Common to all dual-voltage pads 1.2 V / 1.8 V

VIH High-level input voltage CMOS/Schmitt 0.625 * – V

VDD_Px

VIL Low-level input voltage CMOS/Schmitt – 0.35 * V

VDD_Px

IIH Input high leakage current No pull-down – 2 µA

IIL Input low leakage current No pull-up -2 – µA

RP Pull resistance1 Pull-up and pull-down 10 100 kΩ

RK Keeper resistance1 10 100 kΩ

CIN Input capacitance – 5 pF

SDC1 (P7) pad at 1.2 V only

VOH High-level output voltage CMOS, at rated drive strength 0.75 * – V

VDD_Px

VOL Low-level output voltage CMOS, at rated drive strength – 0.25 * V

VDD_Px

SDC1 (P7) pad at 1.8 V only

VOH High-level output voltage CMOS, at rated drive strength VDD_Px - – V

0.45

VOL Low-level output voltage CMOS, at rated drive strength – 0.45 V

1 Refer to Table 2-3 for pull-up, pull-down, and keeper options for each pad (where appropriate).
In all digital I/O cases, VOL and VOH are linear functions with respect to the drive current (given
in Table 2-3). They can be calculated using the relationships expressed in Figure 3-1.

Figure 3-1 IV curve for VOL and VOH (valid for all VDD_Px)

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Electrical Specifications

3.7 Timing characteristics

Specifications for the device timing characteristics are included (where appropriate) under each
function’s section, along with all its other performance specifications. Some general comments
about timing characteristics and pertinent pad-design methodologies are included here.

NOTE: All APQ8016 devices are characterized with actively terminated loads, so all baseband timing
parameters in this document assume no bus loading. This discussion is described further in
Section 3.7.2.

3.7.1 Timing-diagram conventions

The conventions used within timing diagrams throughout this document are shown in Figure 3-2.

Waveform Description

Don't care or bus is driven

Signal is changing from low to high

Signal is changing from high to low

Bus is changing from invalid to valid

Keeper Bus is changing from valid to keeper

Bus is changing from Hi-Z to valid

Denotes multiple clock periods

Figure 3-2 Timing-diagram conventions

For each signal in the diagram:

 One clock period (T) extends from one rising clock edge to the next rising clock edge.
 The high level represents 1, the low level represents 0, and the middle level represents the
floating (high-impedance) state.
 When both the high and low levels are shown over the same time interval, the meaning
depends on the signal type:
 For a bus-type signal (multiple bits) – the processor or external interface is driving a
value, but that value may or may not be valid.
 For a single signal – indicates don’t care.

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Electrical Specifications

3.7.2 Rise and fall time specifications

The testers that characterize APQ8016 devices have actively terminated loads, making the rise
and fall times quicker (mimicking a no-load condition). The impact that different external load
conditions have on rise and fall times is shown in Figure 3-3.

Specified switch low points Specified switch high points

(active terminated load) (active terminated load)
Actual switch low
VDD_PX
point @ 30 pF
Simulated driving VOH
30 pF signal load VOL
Actual switch high
0V
point @ 30 pF
Actual switch low
VDD_PX
point @ 80 pF
Simulated driving VOH
80 pF signal load VOL
Actual switch high
0V
point @ 80 pF

Figure 3-3 Rise and fall times under different load conditions

To account for external load conditions, rise or fall times must be added to parameters that start
timing at the APQ device and terminate at an external device (or vice versa). Adding these rise
and fall times is equivalent to applying capacitive load derating factors.

NOTE: Board designers should use the relevant APQ8016 IBIS File for this analysis.

3.7.3 Pad design

The APQ8016 device uses a generic CMOS pad driver design. The intent of the pad design is to
create pin response and behavior that is symmetric with respect to the associated VDD_Px supply
(Figure 3-4). The input switch point for pure input-only pads is designed to be VDD_Px/2 (or 50%
of VDD_Px). The documented switch points (guaranteed over worst-case combinations of process,
voltage, and temperature by both design and characterization) are 35% of VDD_Px for VIL and 65%
of VDD_Px for VIH.

switch points
VDD_PX

VIH 65% VDD_PX

Input 50%
VIL 35% VDD_PX

0V

Figure 3-4 Digital input signal switch points

Outputs (address, chip selects, clocks, etc.) are designed and characterized to source or sink a
large DC output current (several mA) at the documented VOH (min) and VOL(max) levels over
worst-case process/voltage/temperature. Because the pad output structures (Figure 3-5) are
essentially CMOS drivers that may have a small amount of IR loss (estimated at less than 50 mV
under worst-case conditions), the expected zero DC load outputs are estimated to be as follows:

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 VOH ~ VDD_Px - 50 mV or more

 VOL ~ 50 mV or less

VDD_Px

P_out = low
P_out IR loss < 50 mV
output APQ pad
pad P_out = high
IR loss < 50 mV
Pad voltage:
HIGH (max) > VDD_Px – 50 mV
LOW (min) < 50 mV

Figure 3-5 Output-pad equivalent circuit

The DC output drive strength can be approximated by linear interpolations between VOH (min)
and VDD_Px - 50 mV, and between VOL (max) and 50 mV. For example, an output pad driving low
that guarantees 4.5 mA at VOL (max) will provide approximately 3.0 mA or more at
2/3 × [VOL (max) - 50 mV], and 1.5 mA or more at 1/3 × [VOL (max) - 50 mV]. Likewise, an
output pad driving high that guarantees 2.5 mA at VOH (min) will provide approximately 1.25 mA
or more at ½ × [VDD_Px - 50 mV + VOH (min)].
The output pads are essentially CMOS outputs with a corresponding FET-type output
voltage/current transfer function. When an output pad is shorted to the opposite power rail, the
pad is capable of sourcing or sinking ISC (SC = short-circuit) of current, where the magnitude of
ISC is larger than the current capability at the intended output logic levels.
Since the target application includes a radio, output pads are designed to minimize output slew
rates. Decreased slew rates limit high-frequency spectral components that tend to desensitize the
companion radio.
Output drivers’ rise time (t(r)) and fall time (t(f)) values are functions of board loading.
Bidirectional pins include both input and output pad structures, and behave accordingly when
used as inputs or outputs within the system. Both input and output behaviors were described
above.

3.8 Memory support

All timing parameters in this document assume no bus loading. Rise/fall time numbers must be
factored into the numbers in this document. For example, setup-time numbers will get worse and
hold-time numbers may get better.

3.8.1 EBI0 memory support

The APQ8016 EBI0 port supports an external LPDDR2/3 SDRAM memory:
 Interface frequency of up to 533 MHz
 1.2V IO interface

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3.8.1.1 EBI0 pad drive strength

Pads for EBI0 are tailored for its 1.2 V interface and are source-terminated. Before the source
termination, the pad drive strength is 15 mA to 60 mA. But at the pads, after the source
termination, the drive strength at IOL, IOH is equivalent to 0.90 mA to 3.35 mA in nonlinear
steps when the JEDEC standard range (90% – 10%) is followed.

3.8.1.2 LPDDR2/3 SDRAM clock

For any timing analysis, the measurement point for all signals is at 50% of VDD_Px. All output
timing parameters represent the point of the output signal transition; additional accounting for
signal rise and fall times for specific bus loading is required.

t(ck)

EBI0_DCLK

EBI0_DCLKB

Three examples of the clock cross-over point

1 2 3
EBI0_DCLK
VDD/2 VOD
EBI0_DCLKB
Vixca
Vixca

Figure 3-6 DDR SDRAM DCLK and DCLKB

Table 3-13 DDR SDRAM clock-timing parameters

Parameter Comments Min Typ Max Unit

1/tCK DDR clock frequency 10 – 533 (LPDDR2) MHz

533 (LPDDR3)

Duty cycle 45 – 55 %

Vixca1 Clock crossover-point ± offset from VDD/2 – – 120 mV

VOD Differential output voltage 0.44 – – V

1 Crosstalk due to high CA activity might cause parameters to exceed the Vixca limit.

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3.8.1.3 LPDDR2/3 SDRAM strobe

EBI0_DQS_x

EBI0_DQSB_x

Three examples of the strobe cross-over point

1 2 3
EBI0_DQS_x
VDD/2 VOD
EBI0_DQSB_x
Vixdq
Vixdq

Figure 3-7 DDR SDRAM DQS_x and DQSB_x

Table 3-14 DDR SDRAM strobe timing parameters

Parameter Comments Min Typ Max Unit

VIXDQ Clock cross-over point ± offset from VDDQ/2 – – 120 mV

VOD Differential output voltage 0.44 – – V

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3.8.1.5 LPDDR2 SDRAM read and write timing

EBI0_DCLK

EBI0_DCLKB
t(is) t(ih)
t(ipw)

EBI0_CA[MSB:0] ADDR
CMD/ADDR
t(dqsck)

EBI0_DQS[MSB:0]

EBI0_DQSB[MSB:0]

t(dqsq)
t(qhs) t(dipw)
EBI0_DQ[MSB:0]

Figure 3-8 LPDDR2 SDRAM read timing diagram

Table 3-15 LPDDR2 SDRAM read timing specifications

Parameter Comments Min Typ Max Unit

LPDDR2 (533 MHz) – common to read and write

t(is) Address & control in setup time before CK 0.22 – – ns

t(ih) Address & control input hold time after CK 0.22 – – ns

t(dipw) DQ & DM pulse width 0.35 – – tCK

t(ipw) Address & control input pulse width 0.40 – – tCK

t(tdiff) Input transition slew rate from VIL to VIH Differential clock 2.0 – – V/ns

t(t) Input transition time from VIL to VIH Other than diff clock 1.0 – – V/ns

LPDDR2 (533 MHz) – read cycle

t(dqsck) DQS access time from clock 2.50 – 5.50 ns

t(dqsq) DQS to DQ skew limit – – 0.2 ns

t(rpre) Read preamble 0.90 – – t(ck)

t(qhs) Data hold skew factor – – 0.23 ns

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EBI0_DCLK

EBI0_DCLKB
t(is) t(ih)
t(ipw)

EBI0_CA[MSB:0] ADDR
CMD/ADDR

CASE 1 t(dqsh) t(dss)

t(dqss) max
t(dqss) = MAX
t(dqsl)
EBI0_DQS[MSB:0]

EBI0_DQSB[MSB:0]
t(ds)
t(dh)
EBI0_DQ[MSB:0]

CASE 2 t(dsh)
t(dqss) = MIN t(dqss) min t(dqsl) t(dqsh)

EBI0_DQS[MSB:0]

EBI0_DQSB[MSB:0]
t(ds)
t(dh)
EBI0_DQ[MSB:0]

Figure 3-9 LPDDR2 SDRAM write timing diagram

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Table 3-16 LPDDR2 SDRAM write timing specifications

Parameter Comments Min Typ Max Unit

LPDDR2 (533 MHz) – common to read and write

t(is) Address & control in setup time before CK 0.22 – – ns

t(ih) Address & control input hold time after CK 0.22 – – ns

t(dipw) DQ & DM pulse width 0.35 – – tCK

t(ipw) Address & control input pulse width 0.40 – – tCK

t(tdiff) Input transition slew rate from VIL to VIH Differential clock 2.0 – – V/ns

t(t) Input transition time from VIL to VIH Other than diff clock 1.0 – – V/ns

LPDDR2 (533 MHz) – write cycle

t(ds) DQ and DM input setup time before DQS 0.21 – – ns

t(dh) DQ and DM input hold time after DQS 0.21 – – ns

t(dqsh) DQS input high-level width 0.40 – – t(ck)

t(dqsl) DQS input low-level width 0.40 – – t(ck)

t(dqss) First DQS latching transition 0.75 – 1.25 t(ck)

t(dss) DQS falling edge to CK setup time 0.20 – – t(ck)

t(dsh) DQS falling edge hold time after CK 0.20 – – t(ck)

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3.8.1.6 LPDDR3 SDRAM read and write timing

EBI0_DCLK

EBI0_DCLKB
t(is) t(ih)
t(ipw)

EBI0_CA[MSB:0] ADDR
CMD/ADDR
t(dqsck)

EBI0_DQS[MSB:0]

EBI0_DQSB[MSB:0]

t(dqsq)
t(qhs) t(dipw)
EBI0_DQ[MSB:0]

Figure 3-10 LPDDR3 SDRAM read timing diagram

Table 3-17 LPDDR3 SDRAM read timing specifications

Parameter Comments Min Typ Max Unit

LPDDR3 (533 MHz) – common to read and write

t(isca) Address & control in setup time before CK 0.175 – – ns

t(ihca) Address & control input hold time after CK 0.175 – – ns

t(dipw) DQ & DM pulse width 0.35 – – t(ck)

t(iscs) CS_n input setup time 0.29 – – ns

t(ihcs) CS_n input hold time 0.29 – – ns

t(ipwcs) CS_n input pulse width 0.7 – – t(ck)

t(ipw) Address & control input pulse width 0.35 – – t(ck)

t(tdiff) Input transition slew rate from VIL to VIH Differential clock 2.0 – – V/ns

t(t) Input transition time from VIL to VIH Other than diff clock 1.0 – – V/ns

LPDDR3 (533 MHz) – read cycle

t(dqsck) DQS access time from clock 2.50 – 5.50 ns

t(dqsq) DQS to DQ skew limit – – 0.165 ns

t(qhs) Data hold skew factor – – 0.713 ns

t(rpre) Read preamble 0.9 – – t(ck)

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EBI0_DCLK

EBI0_DCLKB
t(is) t(ih)
t(ipw)

EBI0_CA[MSB:0] ADDR
CMD/ADDR

CASE 1 t(dqsh) t(dss)

t(dqss) max
t(dqss) = MAX
t(dqsl)
EBI0_DQS[MSB:0]

EBI0_DQSB[MSB:0]
t(ds)
t(dh)
EBI0_DQ[MSB:0]

CASE 2 t(dsh)
t(dqss) = MIN t(dqss) min t(dqsl) t(dqsh)

EBI0_DQS[MSB:0]

EBI0_DQSB[MSB:0]
t(ds)
t(dh)
EBI0_DQ[MSB:0]

Figure 3-11 LPDDR3 SDRAM write timing diagram

Table 3-18 LPDDR3 SDRAM write timing specifications

Parameter Comments Min Typ Max Unit

LPDDR3 (533 MHz) – common to read and write

t(isca) Address & control in setup time before CK 0.175 – – ns

t(ihca) Address & control input hold time after CK 0.175 – – ns

t(dipw) DQ & DM pulse width 0.35 – – t(ck)

t(iscs) CS_n input setup time 0.29 – – ns

t(ihcs) CS_n input hold time 0.29 – – ns

t(ipwcs) CS_n input pulse width 0.7 – – t(ck)

t(ipw) Address & control input pulse width 0.35 – – t(ck)

t(tdiff) Input transition slew rate from VIL to VIH Differential clock 2.0 – – V/ns

t(t) Input transition time from VIL to VIH Other than diff clock 1.0 – – V/ns

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Parameter Comments Min Typ Max Unit

LPDDR3 (533 MHz) – write cycle

t(ds) DQ and DM input setup time before DQS 0.175 – – ns

t(dh) DQ and DM input hold time after DQS 0.175 – – ns

t(dqsh) DQS input high-level width 0.40 – – t(ck)

t(dqsl) DQS input low-level width 0.40 – – t(ck)

t(dqss) First DQS latching transition 0.75 – 1.25 t(ck)

t(dss) DQS falling edge to CK setup time 0.2 – – t(ck)

t(dsh) DQS falling edge hold time after CK 0.2 – – t(ck)

3.8.2 eMMC on SDC1

See Section 3.10.1 for secure digital interface details.

3.9 Multimedia
Multimedia parameters that require performance specification are addressed in this section.

3.9.1 Camera interfaces

The APQ8016 supports two MIPI_CSIs:
 CSI0 is a single 4-lane CSI
 CSI1 is a 2-lane CSI

Table 3-19 Supported MIPI_CSI standards and exceptions

Applicable standard Feature exceptions APQ variations

MIPI Alliance Specification for D-PHY, v0.65 and v0.9/v1.0, Supports only None
October 8, 2007 unidirectional data
http://www.mipi.org/specifications/physical-layer receiving.
(Complete specifications are available to MIPI members only.)

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3.9.2 Audio support

The APQ8016 device provides the system's audio functions with the analog audio codec
integrated into PM8916 device. A proprietary audio PDM interface through GPIO[63:68] was
used for transmission of audio data with PM8916 integrated analog codec.
APQ audio-related audio interfaces that support other audio devices included:
 I2S – Section 3.10.3
 I2C – Section 3.10.4

3.9.3 Display support

The APQ8016 supports a 4-lane MIPI_DSI.

Table 3-20 Supported MIPI_DSI standards and exceptions

Applicable standard Feature exceptions APQ variations

MIPI Alliance Specification v1.01 for Display Serial Interface None None
http://www.mipi.org/specifications/display-interface
(Specifications are available to MIPI members only.)

MIPI D-PHY Specification v0.65, v0.81, v0.90 None None

http://www.mipi.org/specifications/physical-layer
(Complete specifications are available to MIPI members only.)

3.10 Connectivity
The connectivity functions supported by the APQ8016 device that require electrical specifications
include:
 Secure digital (SD), including SD cards and multimedia cards (MMC)
 Universal serial bus (USB)
 Inter-IC sound (I2S) interfaces
 Inter-integrated circuit (I2C) interfaces
 Serial peripheral interface (SPI) ports
Pertinent specifications for these functions are included in the following subsections.

NOTE: In addition to reviewing the following hardware specifications, also be sure to review the latest
software release notes for software-based performance features or limitations.

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3.10.1 Secure digital interfaces

Table 3-21 Supported SD standards and exceptions

Feature Device
Applicable standard
exceptions variations

Multi Media Card Host Specification, version 4.5.1 None Timing

specifications –
Secure Digital: Physical Layer Simplified Specification, version 3 None see Figure 3-12
and Table 3-22
SDIO Card Specification, version 2.0 None
https://www.sdcard.org/downloads/pls/simplified_specs/archive/partE1_200.pdf
(Simplified specification version 3.00 is available for free download.)

Case 1 – single data rate

SDCx_CLK

t(csurd) t(chrd)
t(dsurd)

Read
t(pddwr)
t(pdcwr) t(cdvrd)
t(dvdrd)

Write

Case 2 – double data rate

SDCx_CLK

t(csurd) t(chrd)

Command
Read
t(pdcwr)
Command
Write

t(dsurd) t(dhrd) t(dsurd) t(dhrd)

Data Read
t(pddwr) t(pddwr)

Data Write

Figure 3-12 Secure digital interface timing diagram

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Table 3-22 Secure digital interface timing specifications

Parameter Min Typ Max Unit

Single data rate (SDR) mode – SDC1 up to 200 MHz

t(cvdrd) Command valid 2.4 – – ns

t(dvdrd) Data valid 2.4 – – ns

t(pddwr) Propagation delay on data write -1.45 – 0.85 ns

t(pdcwr) Propagation delay on command write -1.45 – 0.85 ns

Double data rate (DDR) mode – SDC1 up to 52 MHz

t(chrd) Command hold 1.5 – – ns

t(csurd) Command setup 5.53 – – ns

t(dhrd) Data hold 1.5 – – ns

t(dsurd) Data setup 1.65 – – ns

t(pddwr) Propagation delay on data write 2.5 – 6.15 ns

t(pdcwr) Propagation delay on command write -7.85 – 2.65 ns

SDR mode – SDC2 up to 208 MHz

t(cvdrd) Command valid 2.4 – – ns

t(dvdrd) Data valid 2.4 – – ns

t(pddwr) Propagation delay on data write -1.36 – 0.76 ns

t(pdcwr) Propagation delay on command write -1.36 – 0.76 ns

DDR mode – SDC2 up to 50 MHz

t(chrd) Command hold 1.5 – – ns

t(csurd) Command setup 6.3 – – ns

t(dhrd) Data hold 1.5 – – ns

t(dsurd) Data setup 2 – – ns

t(pddwr) Propagation delay on data write 0.8 – 6 ns

t(pdcwr) Propagation delay on command write -8.2 – 3 ns

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Parameter Min Typ Max Unit

SDR mode – SDC2 up to 100 MHz

t(chrd) Command hold 1.5 – – ns

t(csurd) Command setup 2.5 – – ns

t(dhrd) Data hold 1.5 – – ns

t(dsurd) Data setup 2.5 – – ns

t(pddwr) Propagation delay on data write -3.7 – 1.5 ns

t(pdcwr) Propagation delay on command write -3.7 – 1.5 ns

3.10.2 USB interfaces

Table 3-23 Supported USB standards and exceptions

Applicable standard Feature exceptions Device variations

Universal Serial Bus Specification, Revision 2.0 None Operating voltages,

(April 27, 2000 or later) http://www.usb.org/developers/docs/ system clock, and
(Available for free download.) VBUS – see
Table 3-24

On-The-Go Supplement to the USB 2.0 Specification Supports host mode None
(June 24, 2003, Revision 1.0A or later) aspect of OTG only
http://www.usb.org/developers/docs/
(Available for free download as part of the USB 2.0

Table 3-24 Device-specific USBPHY specifications

Parameter Comments Min Typ Max Unit

Supply voltages

Dual-supply (see Table 3-3 for specifications)

VDD_USB_1P8 – 1.80 – V
VDD_USB_3P3 – 3.075 – V

USB_SYSCLK

Frequency 19.2 MHz clock is required – 19.2 – MHz

Clock deviation -400 – 400 ppm

Jitter (peak-to-peak) 0.5 to 1.75 MHz 0 – 60 ps

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Parameter Comments Min Typ Max Unit

Duty cycle 40 – 60 %

Low-level input voltage (VIL) – – 0.85 V

High-level input voltage (VIH) 1.27 – – V

USB_VBUS

Valid USB_HS_VBUS detection voltage 2.00 – 5.25 V

3.10.3 I2S interface

The MI2S (multiple I2S) interface for microphone and speaker functions is supported by
APQ8016. MI2S is a multichannel I2S. The standard I2S specifications defined by Philips consists
of one data line and our I2S interface adds one or more data lines and thus it is called MI2S.
Protocol is the same as I2S and with MI2S, but more audio channels can be supported. The
following information applies to MI2S.

Table 3-25 Supported I2S standards and exceptions

Applicable standards Feature exceptions APQ variations

Phillips I2S Bus Specifications revised 1. Only the normal I2S format is supported: data When an external
June 5, 1996 is transmitted on the falling edge of clock and SCK clock is
https://www.sparkfun.com/datasheets latched at rising edge used, a duty cycle
/BreakoutBoards/I2SBUS.pdf 2. Only 16, 23, and 32- bit modes are supported of 45% to 55% is
(Available for free download.) 3. I2S IOs are 1.8V nominal, 2.0V max required.

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High-level I2S timing

SCK

WS

SD LSB MSB LSB MSB

WORD (n – 1) WORD (n + 1)
WORD (n) LEFT CHANNEL
RIGHT CHANNEL RIGHT CHANNEL

I2S timing details – Tx & Rx T

t(LC) t(HC)

SCK

t(htr)
SD and WS
transmitter
t(dtr)
t(sr) t(hr)
SD and WS
receiver

Figure 3-13 I2S timing diagram

Table 3-26 I2S interface timing

Parameter Comments1 Min Typ Max Unit

Using internal SCK

Frequency – – 12.2882 MHz

T Clock period 81.380 – – ns

t(HC) Clock high 0.45 · T – 0.55 · T ns

t(LC) Clock low 0.45 · T – 0.55 · T ns

t(sr) SD and WS input setup time 16.276 – – ns

t(hr) SD and WS input hold time 0 – – ns

t(dtr) SD and WS output delay – – 65.100 ns

t(htr) SD and WS output hold time 0 – – ns

Using external SCK

Frequency – – 12.288 MHz

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Parameter Comments1 Min Typ Max Unit

T Clock period 81.380 – – ns

t(HC) Clock high 0.45 · T – 0.55 · T ns

t(LC) Clock low 0.45 · T – 0.55 · T ns

t(sr) SD and WS input setup time 16.276 – – ns

t(hr) SD and WS input hold time 0 – – ns

t(dtr) SD and WS output delay – – 65.100 ns

t(htr) SD and WS output hold time 0 – – ns

1 Load capacitance is between 10 and 40 pF.
2 12.288 MHz is the maximum I2S interface frequency, but the actual frequency used is programmable and
depends on the number of bits and sampling rate desired.

3.10.4 Digital microphone PDM interface

Mbias
PM8916
Vs
Sel
0.1uF
clk
Dmic L Data2 APQ8016
Vs
Sel
0.1uF
clk
Dmic R Data1 Select (Sel) Mode Internal Signal
Vs Right (Data1) DMIC 1
GND Left (Data2) DMIC 2

TCLK

DMIC_CLK

TRH TLH

DMIC_DATA
Data Right(Data 1) Data Left(Data 2)
TRSU TLSU

Figure 3-14 APQ8016 digital mic PDM interface timing

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Table 3-27 Digital microphone timing

Parameter Min Type Max Unit

DMIC clock period (TCLK) 163 – 1666 ns
Data left setup time to DMIC clock rising edge (TLSU) 30 – – ns
Data left hold time from DMIC clock rising edge (TLH) 5 – – ns
Data right setup time to DMIC clock falling edge (TRSU) 30 – – ns
Data right hold time from DMIC clock falling edge (TRH) 5 – – ns

Table 3-28 Digital microphone input path performance for sampling rates of 8 kHz,
16 kHz, 32 kHz, and 48 kHz

Parameter Conditions Min Type Max Units

Frequency response

Frequency response Passband: 20 Hz to 0.4*Fs; digital gain = 0 dB; -0.01 0 0.01 dB

input = -20 dBFs

Transition band 1: 0.4* Fs to 0.4375* Fs; -1 – 0.1 dB

digital gain = 0 dB; input = -20 dBFs

Transition band 2: 0.5*Fs; digital gain = 0 dB; -25 – – dB

input = -20 dBFs

Stopband: >0.5625*Fs; digital gain = 0 dB; input = -80 – – dB

-20 dBFs

General requirements

Clock rate MCLK = 9.6 MHz (Default system master clock – 600 – kHz
frequency)
– 1.2 – MHz

– 2.4 – MHz

– 3.2 – MHz

– 4.8 – MHz

MCLK = 12.288 MHz – 768 – kHz

– 1.536 – MHz

– 2.048 – MHz

– 3.072 – MHz

– 4.096 – MHz

– 6.144 – MHz

Input capacitance – 1 5 pF

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Parameter Conditions Min Type Max Units

Board capacitance – 10 50 pF

3.10.5 I2C interface

Table 3-29 Supported I2C standards and exceptions

Applicable standard Feature exceptions APQ variations

I2C Specification, version 5.0, 1. Slave mode is not supported Multimaster is not supported
October 2012 2. 10-bit addressing is not supported
3. Multi-master is not supported
4. HS mode is not supported

3.10.6 Serial peripheral interface

The APQ8016 supports SPI as a master only. Any one of the six BLSP ports can be configured as
an SPI master. Figure 3-15 is an example of BLSP @ 50 MHz (see Table 3-30).

SPI_CS_N to SPI_CLK timing is fixed at 1 clock period

SPI_CS_N
T
T 50% clock duty cycle is shown but is not a requirement
SPI_CLK
t(mov)
t(mov) value is positive if after clock transition (shown); negative if before)
SPI_DATA_MOSI
t(mis) t(mih)
SPI_DATA_MISO

Figure 3-15 SPI master timing diagram

Table 3-30 SPI master timing characteristics at 50 MHz

Parameter Comments Min Typ Max Unit

T1 SPI clock period: 50 MHz max 20.0 – – ns

t(ch) Clock high 9.0 – – ns

t(cl) Clock low 9.0 – – ns

t(mov) Master output valid -5.0 – 5.0 ns

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Electrical Specifications

Parameter Comments Min Typ Max Unit

t(mis) Master input setup 5.0 – – ns

t(mih) Master input hold 1.0 – – ns

1 The minimum clock period includes 1% jitter of the maximum frequency.

3.11 Internal functions

Some internal functions require external interfaces to enable their operation. These include clock
generation, modes and resets, and JTAG functions – as specified in the following subsections.

3.11.1 Clocks
Clocks that are specific to particular functions are addressed in the corresponding sections of this
document. Others are specified here in this section.

3.11.1.1 19.2 MHz XO input

T

t(xoh)
t(xoh) t(xol)
t(xol)

XO

Average
(DC component)

Figure 3-16 XO timing parameters

Table 3-31 XO timing parameters

Parameter Comments1 Min Typ Max Unit

t(xoh) XO logic high 22.6 – 29.5 ns

t(xol) XO logic low 22.6 – 29.5 ns

T XO clock period – 52.083 – ns

1/T Frequency 19.2 MHz must be used. – 19.2 – MHz

1 See GPS Quality, 19.2 MHz 2520 Package Size, Crystal and TH + Xtal Mini-Specification (LM80-P0598-8)
for more details.

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3.11.1.2 Sleep clock

T

t(xoh) t(xol)

Sleep clock Vpp

Average
(DC component)

Figure 3-17 Sleep-clock timing diagram

Table 3-32 Sleep-clock timing parameters

Parameter Comments Min Typ Max Unit

t(xoh) Sleep-clock logic high 4.58 – 25.94 µs

t(xol) Sleep-clock logic low 4.58 – 25.94 µs

T Sleep-clock period – 30.518 – µs

F Sleep-clock frequency F = 1/T – 32.768 – kHz

Vpp Peak-to-peak voltage – 1.8 – V

3.11.2 Modes and resets

Mode and reset functions are basic digital I/Os that meet the performance specifications presented
in Section 3.6.

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Electrical Specifications

3.11.3 JTAG
t(tckcy)
t(tckh) t(tckl)
TCK

t(htms)
t(sutms)
TMS

t(htdi)
t(sutdi)
TDI

t(do)
TDO

Figure 3-18 JTAG-interface timing diagram

Table 3-33 JTAG-interface timing characteristics

Parameter Comments Min Typ Max Unit

t(tckcy) TCK period 50 – – ns

t(tckh) TCK pulse width high 20 – – ns

t(tckl) TCK pulse width low 20 – – ns

t(sutms) TMS input setup time 5 – – ns

t(htms) TMS input hold time 20 – – ns

t(sutdi) TDI input setup time 5 – – ns

t(htdi) TDI input hold time 20 – – ns

t(do) TDO data-output delay – – 15 ns

3.12 RF and power management interfaces

The supported chipset and RF front-end (RFFE) interfaces are listed in Table 3-34 and Table 3-
35, respectively. The digital I/Os must meet the logic-level requirements specified in Section 3.6.
The Rx and Tx baseband interfaces are proprietary, and therefore are not specified.

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3.12.1 RF front-end (RFFE)

Table 3-34 Supported RFFE standards and exceptions

Applicable standard Feature exceptions APQ variations

MIPI Alliance Specification for RF Front-End Control Interface, None None

version 1.0

The maximum operation frequency of SCLK is 26 MHz, although lower rates may be utilized. A
Slave might not be able to support a 26 MHz clock frequency during a read operation. In this
case, known as half-speed operation, a 13 MHz clock frequency may be implemented for only the
read back.

TclHigh

VTPmax
SCLK
VTNmin
TD
TD

VOHmin
SDATA
VOLmax
Figure 3-18 Waveform

Table 3-35 RFFE data

Half speed device Full speed device

Symbol Description Units
Min Max Min Max

Tsclkoh Clock output high time 24 11.25 ns

Tsclkol Clock output low time 24 11.25 ns

Tsclkotr Clock output transition (rise/fall) time 1 3.5 10 3.5 6.5 ns

Tsclkdch Clock output duty cycle high time 2, 3 45 55 45 55 ns

Tsclkdcl Clock output duty cycle low time 2, 3 45 55 45 55 ns

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Electrical Specifications

Table 3-36 Rx/Tx data

Parameter Description LSL USL units

Tsu Rx data setup time with respect to falling edge of clock 15.75 – ns

Thd Rx data hold time with respect to falling edge of clock 0 – ns

Tpd Tx data output delay w.r.to rising edge of clock NA 10.25 ns

TclHigh Tx clock duty cycle 0.45*Tck 0.55*Tck ns

3.12.2 System power management interface (SPMI)

Table 3-37 SPMI standards and exceptions

Applicable standard Feature exceptions APQ variations

MIPI Alliance Specification for System Power Management Interface None None
(SPMI) version 1.0

Table 3-38 Supported SPMI standards

Interface Parameter Description Target frequency Spec min Spec max Units

SPMI Tsu Input data set up time 19.2 MHz 1 1 ns

Thd Input data hold time 5 5 ns

TdataZ data release time - 11 ns

Tpd Output data delay - 11 ns

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 4 Mechanical Information

4.1 Device physical dimensions

The APQ8016 is available in the 760-pin nanoscale package (NSP) that includes dedicated
ground pins for improved grounding, mechanical strength, and thermal continuity. The 760 NSP
has a 14.0 mm × 12.0 mm body with a maximum height of 0.96 mm. Pin A1 is located by an
indicator mark on the top of the package, and by the ball pattern when viewed from below. A
simplified version of the 760NSP outline drawing is shown in Figure 4-1.

Figure 4-1 760 NSP (14.0 × 12.0 × 0.96 mm) outline drawing

NOTE: Figure 4-1 is a simplified outline drawing.

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Mechanical Information

4.2 Part marking

Figure 4-2 APQ8016 device marking (top view, not to scale)

4.2.1 Specification-compliant devices

Table 4-1 APQ8016 device marking line definitions

Line Marking Description

1 QUALCOMM Qualcomm name or logo

2 APQ8016 QTI product name

3 PBB P = product configuration code (see Table 4-2)

BB = feature code (see Table 4-2)

An additional line may appear on the part marking for some samples; this is manufacturing
information that is only relevant to QTI and QTI suppliers.

4 FXXXXXXX F = supply source code

 F = A (for GF)
 F = B (for TSMC)
 F = C (for Samsung)
XXXXXXX = traceability number

5 ASYWWRR A = assembly site code

 A = U (Amkor, Shanghai)
 A = K (SPIL Taiwan)
 A = V (STATSChipPAC, China)
 A = E (ASE, Kaohsiung, Taiwan)
S = assembly sequence number
Y = single-digit year code
WW = work week (based on calendar year)
RR = product revision (see Table 4-2)

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Mechanical Information

4.3 Device ordering information

4.3.1 Specification-compliant devices

This device can be ordered using the identification code shown in Figure 4-3 and explained in this
section.

Device ID
AAA-AAAA — P — CCC DDDD — EE — RR — S — BB
code

Symbol Product Config Number Package Shipping Product Source Feature

definition name code of pins type package revision code code

Example APQ-8016 — 0 — 760 NSP — NSP — 00 — 0 — VV

‘CCC’ is not a fixed length; it depends Package type varies in

on the # of pins in the package the # of characters

Feature code (BB) may not be included when identifying older devices.

Figure 4-3 APQ8016 device identification code

Device ordering information details for all samples available to date are summarized in Table 4-2.

Table 4-2 Device identification code/ordering information details

Product configuration Product HW revision Sample HW S BB

Device
code (P) revision (RR) number type version value1 value2

APQ-8016 1 00 0x0 0706 0E1 ES/CS v1.0 0 VV

1 “S” is the source configuration code that identifies all of the qualified die fabrication-source combinations
available at the time a particular sample type was shipped. S values are defined in Table 4-3.
2 BB is the feature code that identifies an IC’s specific feature set, which distinguishes it from other versions

or variants. All feature sets available at the time of this document’s release are defined in Table 4-2.

NOTE: Devices with date code (YWW) = 1423 or later are CS devices.

Table 4-3 Source configuration code

S value Die F value = A F value = B F value = C

0 Digital GF TSMC Samsung

Other columns and rows will be added in future revisions of this document, if needed.

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Mechanical Information

4.4 Device moisture-sensitivity level

Plastic-encapsulated surface mount packages are susceptible to damage induced by absorbed
moisture and high temperature. A package’s moisture-sensitivity level (MSL) indicates its ability
to withstand exposure after it is removed from its shipment bag, while it is on the factory floor
awaiting PCB installation. A low MSL rating is better than a high rating; a low MSL device can
be exposed on the factory floor longer than a high MSL device. All pertinent MSL ratings are
summarized in Table 4-4.

Table 4-4 MSL ratings summary

MSL Out-of-bag floor life Comments

1 Unlimited ≤ 30°C/85% RH

2 1 year ≤ 30°C/60% RH

2a 4 weeks ≤ 30°C/60% RH

3 168 hours ≤ 30°C/60% RH

4 72 hours ≤ 30°C/60% RH

5 48 hours ≤ 30°C/60% RH

5a 24 hours ≤ 30°C/60% RH

6 Mandatory bake before use. After bake, must be ≤ 30°C/60% RH

re-flowed within the time limit specified on the label.

The latest IPC/JEDEC J-STD-020 standard revision for moisture-sensitivity qualification are
followed. The APQ8016 device samples are currently classified as MSL3 at 255 (+5, -0)°C.
This qualification temperature (255 (+5, -0)°C) should not be confused with the peak temperature
within the recommended solder reflow profile (see Section 6.2.3 for more details).

4.5 Thermal characteristics

Rather than provide thermal resistance values θJC and θJA, validated thermal-package models are
provided through the CDMATech Support website. A thermal model for each device is provided
within the Power_Thermal subfolder for each chipset family. Designers can obtain thermal
resistance values by conducting their own thermal simulations.

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 5 Carrier, Storage, & Handling Information

5.1 Carrier

5.1.1 Tape and reel information

All carrier tape systems conform to EIA-481 standards.
A simplified sketch of the APQ8016 tape carrier is shown in Figure 5-1, including the proper part
orientation, maximum number of devices per reel, and key dimensions.

Pin A1 faces feed holes

Tape width

Taping direction Pocket pitch

Tape feed: Single Reel diameter: 330 mm Tape width: 24 mm

Units per reel: 2000 Hub diameter: 178 mm Pocket pitch: 16 mm

Figure 5-1 Carrier tape drawing with part orientation

Tape-handling recommendations are shown in Figure 5-2 Tape handling.

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Carrier, Storage, & Handling Information

Handle only at the edges

Figure 5-2 Tape handling

5.2 Storage

5.2.1 Bagged storage conditions

APQ8016 devices delivered in tape and reel carriers must be stored in sealed, moisture barrier,
anti-static bags. If the storage environment maintains an ambient temperature lower than 40°C
and relative humidity less than 90%, the expected shelf life is at least 24 months.

5.2.2 Out-of-bag duration

The out-of-bag duration is the time a device can be on the factory floor before being installed
onto a PCB. It is defined by the device MSL rating, as described in Section 4.4.

5.3 Handling
Tape handling was described in Section 5.1.1. Other (IC-specific) handling guidelines are
presented in the following sections.

5.3.1 Baking
It is not necessary to bake the APQ8016 if the conditions specified in Section 5.2.1 and Section
5.2.2 not been exceeded.
It is necessary to bake the APQ8016 if any condition specified in Section 5.2.1 or Section 5.2.2
has been exceeded. The baking conditions are specified on the moisture-sensitive caution label
attached to each bag.

CAUTION If baking is required, the devices must be transferred into trays that can be baked to at least
125°C. Devices should not be baked in tape and reel carriers at any temperature.

5.3.2 Electrostatic discharge

Electrostatic discharge (ESD) occurs naturally in laboratory and factory environments. An
established high-voltage potential is always at risk of discharging to a lower potential. If this
discharge path is through a semiconductor device, destructive damage may result.

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Carrier, Storage, & Handling Information

ESD countermeasures and handling methods must be developed and used to control the factory
environment at each manufacturing site.
This product must be handled according to the ESD Association standard: ANSI/ESD
S20.20-1999, Protection of Electrical and Electronic Parts, Assemblies, and Equipment.
Refer to Chapter 7 for the APQ8016 device ESD ratings.

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 6 PCB Mounting Guidelines

6.1 RoHS compliance

The device is lead-free and RoHS-compliant. Its SnAgCu solder balls use SAC305 composition
on the top and SAC125/Ni on the bottom. Lead-free (or Pb-free) semiconductor products are
defined as having a maximum lead concentration of 1000 ppm (0.1% by weight) in raw
(homogeneous) materials and end products.

6.2 SMT parameters

This section describes board-level characterization process parameters. It is included to assist
customers with their SMT process development; it is not intended to be a specification for their
SMT processes.

6.2.1 Land pad and stencil design

The land pattern and stencil recommendations presented in this section are based on
characterizations for lead-free solder pastes on an eight-layer PCB, built primarily to the
specifications described in JEDEC JESD22-B111.
Characterization of the land patterns according to each customer's processes, materials,
equipment, stencil design, and reflow profile prior to PCB production is recommended.
Optimizing the solder stencil pattern design and print process is critical to ensure print
uniformity, decrease voiding, and increase board-level reliability.
General land pattern guidelines:
 Non-solder-mask-defined (NSMD) pads provide the best reliability.
 Keep the solderable area consistent for each pad, especially when mixing via-in-pad and
non-via-in-pad in the same array.
 Avoid large solder mask openings over ground planes.
 Traces for external routing are recommended to be less than or equal to half the pad diameter,
to ensure consistent solder-joint shapes.
One key parameter that should be evaluated is the ratio of aperture area to sidewall area, known
as the area ratio (AR). Square apertures are recommended for optimal solder-paste release. In this
case, a simple equation can be used relating the side length of the aperture to the stencil thickness
(as shown and explained in Figure 6-1). Larger area ratios enable better transfer of solder paste to
the PCB, minimize defects, and ensure a more stable printing process. Inter-aperture spacing
should be at least as thick as the stencil; otherwise, paste deposits may bridge.

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification PCB Mounting Guidelines

L
L
Aperture

AR = L / 4T

Figure 6-1 Area ratio (AR)

Example Land Pattern and stencil designs are available for the 760 NSP.

6.2.2 Reflow profile

Reflow profile conditions typically used for lead-free systems are listed in Table 6-1, and are
shown in Figure 6-2.

Table 6-1 Typical SMT reflow profile conditions (for reference only)

Profile stage Description Temp range Condition

Preheat Initial ramp < 150°C 3°C/sec max

Soak Flux activation 150 to 190°C 60 to 75 sec

Ramp Transition to liquidus (solder-paste 190 to 220°C < 30 sec

melting point)

Reflow Time above liquidus 220 to 245°C 1 50 to 70 sec

Cool down Cool rate – ramp to ambient < 220°C 6°C/sec max
1 During the reflow process, the recommended peak temperature is 245°C (minimum). This temperature
should not be confused with the peak temperature reached during MSL testing, as described in Section
6.2.3.

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Stay above 220°C for 50 to 70 seconds

250

Cool down
Reflow
200
Temperature (°C)

Ramp
Soak

6°C/sec
Preheat

max
150
max
/sec
3°C

100
t t+20 t+40 t+60 t+80 t+100 t+120 t+140 t+160 t+180 t+200
Time (sec)

Figure 6-2 Typical SMT reflow profile

6.2.3 SMT peak package-body temperature

This document states a peak package-body temperature in two other places within this document;
without explanation, they may appear to conflict. The two places are listed below, along with an
explanation of the stated value and its meaning within that section’s context.
 Section 4.4 – Device moisture-sensitivity level
APQ8016 devices are classified as MSL3@255°C. The temperature (255°C) included in this
designation is the lower limit of the range stated for moisture resistance testing during the
device qualification process, as explained immediately below.
 Section 6.2.2– Reflow profile
During a production board’s reflow process, the temperature experienced by the package
must be controlled. Obviously the temperature must be high enough to melt the solder and
provide reliable connections, but it must not be so high that the device can be damaged. The
recommended peak temperature during production assembly is 245°C. This temperature is
comfortably above the solder melting point (220°C), yet well below the proven temperature
reached during qualification (255°C or more).

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6.2.4 SMT process verification

Verification of the SMT process is recommended prior to high-volume board assembly, including
the following:
 In-line solder-paste deposition monitoring
 Reflow profile measurement and verification
 Visual and x-ray inspection after soldering to confirm adequate alignment, solder voids,
solder-ball shape, and solder bridging
 Cross-section inspection of solder joints for wetting, solder-ball shape, and voiding

6.3 Board-level reliability

Characterization tests have been conducted to assess the device’s board-level reliability, including
the following physical tests on evaluation boards:
 Drop shock (JESD22-B111)
 Temperature cycling (JESD22-A104)
 Cyclic bend testing – optional (JESD22-B113)

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 7 Part Reliability

7.1 Reliability evaluation summary

7.1.1 APQ8016 reliability evaluation report for device from GF-F8

Table 7-1 GF-F8 silicon reliability results

Tests, standards, and conditions Sample size Result

DPPM rate (ELFR) and average failure rate (AFR) in FIT 0F/356 DPPM < 1000 1
(λ) failure in billion device-hours Cum FITs < 25 FITs1
HTOL: JESD22-A108-D
Total samples from three different wafer lots

0F/356 > 40 1
Mean time to failure (MTTF) t = 1/λ in million hours
Total samples from three different wafer lots

ESD – human-body model (HBM) rating: 2000 V

JESD22-A114-F 3
Total samples from one wafer lot

ESD – charge-device model (CDM) rating:

JESD22-C101-D 3 500 V
Target: 500 V
Total samples from one wafer lot

Latch-up (I-test):
EIA/JESD78C 6 Pass
Trigger current: ±100 mA; temperature: 85°C
Total samples from one wafer lot

Latch-up (V supply over-voltage):

EIA/JESD78A 6 Pass
Trigger voltage: each VDD pin, stress at 1.5 × Vdd max per
device specification; temperature: 85°C
Total samples from one wafer lot
1 Cum FITs from multiple products under GF F8, 28 nm LP process.

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Table 7-2 GF-F8 package reliability results

ATC SPIL ASE SCC Result

assembly assembly assembly assembly
Tests, standards, and conditions
source source source source
sample size sample size sample size sample size

Moisture resistance test (MRT): 480 480 480 Pass

J-STD-020 480
Reflow at 260°C +0/-5°C
Total samples from three different assembly
lots at each SAT

Temperature cycle: JESD22-A104-D 240 240 240 240 Pass

Temperature: -55°C to 125°C; number of
cycles: 1000
Soak time at minimum/maximum
temperature: 8–10 minutes

Cycle rate: 2 cycles per hour (CPH)

Preconditioning: JESD22-A113
MSL 1, reflow temperature: 260°C +0/-5°C
Total samples from three different assembly
lots at each SAT

Unbiased highly accelerated stress test: 240 240 240 240 Pass
JESD22-A118
130°C/85% RH and 96 hours. duration
Preconditioning: JESD22-A113-F
MSL 1, reflow temperature: 260°C +0/-5°C
Total samples from three different assembly
lots at each SAT

Biased highly accelerated stress test: 135 1 135 1 135 2 135 1 Pass
JESD22-A110
130°C/85% RH and 264 hours duration
Preconditioning: JESD22-A113-F
MSL 1, reflow temperature: 260°C +0/-5°C
Total samples from three different assembly
lots at each SAT

High-temperature storage life: 240 240 240 240 Pass

JESD22-A103-C
Temperature 150°C, 500, 1000 hours.
Total samples from three different assembly
lots at each SAT

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ATC SPIL ASE SCC Result

assembly assembly assembly assembly
Tests, standards, and conditions
source source source source
sample size sample size sample size sample size

Flammability – – – –
Note: flammability test – not required
UL-STD-94
QTI ICs are exempt from the flammability
requirements due to their sizes per UL/EN
60950-1, as long as they are mounted on
materials rated V-1 or better. Most PWBs
onto which QTI ICs mount are rated V-0
(better than V-1).

Physical dimensions: JESD22-B100-A 75 75 75 75 Pass

Case outline drawing: QTI internal document
Total samples from three different assembly
lots at each SAT

Solder ball shear: JESD22-B117 30 30 30 30

Total samples from three different assembly Pass
lots at each SAT

Internal/external visual 75 75 75 75
Total samples from three different assembly Pass
lots at each SAT
1 Data is bridged from the 488 NSP 12 x 12 mm package.
2 Data is bridged from the 745 PNSP 12 x 12 mm package.

7.1.2 APQ8016 reliability evaluation report for device from TSMC-F15

Table 7-3 TSMC-F15 silicon reliability results

Tests, standards, and conditions Sample size Result

DPPM rate (ELFR) and average failure rate (AFR) in FIT (λ) failure 0F/360 DPPM < 1000 1
in billion device-hours Cum FITs < 25 FITs 1
HTOL: JESD22-A108-D
Total samples from three different wafer lots

Mean time to failure (MTTF) t = 1/λ in million hours 0F/360 > 40 1

Total samples from three different wafer lots

ESD – human-body model (HBM) rating: 3

JESD22-A114-F 2000 V
Total samples from one wafer lot

ESD – charge-device model (CDM) rating: 3

JESD22-C101-D 500 V
Target: 500 V
Total samples from one wafer lot

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Tests, standards, and conditions Sample size Result

Latch-up (I-test): 6
EIA/JESD78C
Pass
Trigger current: ±100 mA; temperature: 85°C
Total samples from one wafer lot

Latch-up (V supply over-voltage): 6 Pass

EIA/JESD78A
Trigger voltage: each VDD pin, stress at 1.5 × Vdd max per device
specification; temperature: 85°C
Total samples from one wafer lot

1 Cum FITs from multiple products under TSMC-F15, 28 nm LP process.

Table 7-4 TSMC-F15 package reliability results

ATC SPIL ASE SCC

assembly assembly assembly assembly
Tests, standards, and conditions Result
source source source source
sample size sample size sample size sample size

Moisture resistance test (MRT): 480 480 480 480 Pass

J-STD-020
Reflow at 260°C +0/-5°C
Total samples from three different
assembly lots at each SAT

Temperature cycle: JESD22-A104-D 240 240 240 240 Pass

Temperature: -55°C to 125°C; number
of cycles: 1000
Soak time at minimum/maximum
temperature: 8–10 minutes.
Cycle rate: 2 cycles per hour (CPH)
Preconditioning: JESD22-A113
MSL 1, reflow temperature: 260°C
+0/-5°C
Total samples from three different
assembly lots at each SAT

Unbiased highly accelerated stress 240 240 240 240 Pass

test: JESD22-A118
130°C/85% RH and 96 hours duration
Preconditioning: JESD22-A113-F
MSL 1, reflow temperature: 260°C
+0/-5°C
Total samples from three different
assembly lots at each SAT

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ATC SPIL ASE SCC

assembly assembly assembly assembly
Tests, standards, and conditions Result
source source source source
sample size sample size sample size sample size

Biased highly accelerated stress 1351 135 1 135 2 135 1 Pass

test: JESD22-A110
130°C/85% RH and 264 hours
duration
Preconditioning: JESD22-A113-F
MSL 1, reflow temperature: 260°C+0/-
5°C
Total samples from three different
assembly lots at each SAT

High-temperature storage life: 240 240 240 240 Pass

JESD22-A103-C
Temperature 150°C, 500, 1000 hours
Total samples from three different
assembly lots at each SAT

Flammability – – – –
Note: Flammability test – not required
UL-STD-94
QTI ICs are exempt from the
flammability requirements due to their
sizes per UL/EN 60950-1, as long as
they are mounted on materials rated
V-1 or better. Most PWBs onto which
QTI ICs mount are rated V-0 (better
than V-1).

Physical dimensions: JESD22- 75 75 75 75 Pass

B100-A
Case outline drawing: QTI internal
document
Total samples from three different
assembly lots at each SAT

Solder ball shear: JESD22-B117 30 30 30 30 Pass

Total samples from three different
assembly lots at each SAT

Internal/external visual 75 75 75 75 Pass

Total samples from three different
assembly lots at each SAT
1 Data is bridged from the 488 NSP 12 x 12 mm package.
2 Data is bridged from the 745 PNSP 12 x 12 mm package.

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Part Reliability

7.1.3 APQ8016 reliability evaluation report for device from Samsung

Table 7-5 Samsung silicon reliability results

Tests, standards, and conditions Sample size Result

DPPM rate (ELFR) and average failure rate (AFR) in FIT 456 DPPM < 1000 1
(λ) failure in billion device-hours Cum FITs < 25 FITs 1
HTOL: JESD22-A108-D
Total samples from three different wafer lots

Mean time to failure (MTTF) t = 1/λ in million hours 456 > 40 1

Total samples from three different wafer lots

ESD – human-body model (HBM) rating: 3 2000 V

JESD22-A114-F
Total samples from one wafer lot

ESD – charge-device model (CDM) rating: 3 500 V

JESD22-C101-D
Target: 500 V
Total samples from one wafer lot

Latch-up (I-test): 6 Pass

EIA/JESD78C
Trigger current: ±100 mA; temperature: 85C
Total samples from one wafer lot

Latch-up (V supply over-voltage): 6 Pass

EIA/JESD78A
Trigger voltage: each VDD pin, stress at 1.5 × Vdd max per
device specification; temperature: 85°C
Total samples from one wafer lot

1 Cum FITs from multiple products under the Samsung, 28 nm LP process.

Table 7-6 Samsung package reliability results

ATC SPIL ASE SCC Result

assembly assembly assembly assembly
Tests, standards, and conditions
source source source source
sample size sample size sample size sample size

Moisture resistance test (MRT): 480 480 480 480 Pass

J-STD-020
Reflow at 260°C +0/-5°C
Total samples from three different assembly
lots at each SAT

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Part Reliability

ATC SPIL ASE SCC Result

assembly assembly assembly assembly
Tests, standards, and conditions
source source source source
sample size sample size sample size sample size

Temperature cycle: JESD22-A104-D 240 240 240 240 Pass

Temperature: -55°C to 125C; number of
cycles: 1000
Soak time at minimum/maximum
temperature: 8–10 minutes.
Cycle rate: 2 cycles per hour (CPH)
Preconditioning: JESD22-A113
MSL 3, reflow temperature: 260°C
+0/-5°C
Total samples from three different assembly
lots at each SAT

Unbiased highly accelerated stress test: 240 240 240 240 Pass
JESD22-A118
130°C/85% RH and 96 hours duration
Preconditioning: JESD22-A113-F
MSL 3, reflow temperature: 260°C
+0/-5°C
Total samples from three different assembly
lots at each SAT

Biased highly accelerated stress test: 1351 135 1 1352 135 1 Pass
JESD22-A110
130°C/85% RH and 264 hours duration
Preconditioning: JESD22-A113-F
MSL 3, reflow temperature: 260°C
+0/-5°C
Total samples from three different assembly
lots at each SAT

High-temperature storage life: JESD22- 240 240 240 240 Pass

A103-C
Temperature 150°C, 500, 1000 hours
Total samples from three different assembly
lots at each SAT

Flammability – – – –
Note: Flammability test – not required
UL-STD-94
QTI ICs are exempt from the flammability
requirements due to their sizes per UL/EN
60950-1, as long as they are mounted on
materials rated
V-1 or better. Most PWBs onto which QTI ICs
mount are rated V-0 (better than V-1).

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification Part Reliability

ATC SPIL ASE SCC Result

assembly assembly assembly assembly
Tests, standards, and conditions
source source source source
sample size sample size sample size sample size

Physical dimensions: 75 75 75 75 Pass

JESD22-B100-A
Case outline drawing: QTI internal document
Total samples from three different assembly
lots at each SAT

Solder ball shear: JESD22-B117 30 30 30 30

Total samples from three different assembly Pass
lots at each SAT

Internal/external visual 75 75 75 75 Pass

Total samples from three different assembly
lots at each SAT
1 Data is bridged from the 488 NSP 12 x 12 mm package.
2 Data is bridged from the 745 PNSP 12 x 12 mm package.

7.2 Qualification sample description

Table 7-7 Device characteristics
Device Specifications
Device name APQ8016

Package type 760 NSP

Package body size 14 mm × 12 mm × 0.96 mm
Fab process 28 nm CMOS
Fab sites  GF
 TSMC
 Samsung
Assembly sites  Amkor, Shanghai
 SPIL, Taiwan
 STATSChipPAC, China
 ASE, Kaohsiung, Taiwan
Solder ball pitch 0.4 mm

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Qualcomm® Snapdragon™ 410 Processor APQ8016 Device Specification EXHIBIT 1

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