Xilinx Spartan-6
FPGA Board Setup
Jeremy Sandoval
University of Washington
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Table of Contents
Hardware Overview: Xilinx Spartan-6 FPGA
Relation to ATLAS IBL ROD
Software Overview: Xilinx ISE Design Suite
VHDL Programming
Next Steps
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Hardware Overview: Spartan-6 FPGA
Field Programmable Gate Array
The Spartan-6 family is built on a
45-nanometer [nm], 9-metal
layer, dual-oxide process
technology.
The Spartan-6 was marketed in
2009 as a low-cost solution for
automotive, wireless
communications, flat-panel
display and video surveillance
applications
Updated FPGA technology for
ATLAS IBL ROD, Previous Read
Out Driver utilized Spartan-2 Source:
FPGA http://www.robotshop.com/content/images/digilent-
atlys-spartan-6-fpga-development-kit-large.jpg
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ATLAS Insertable B-Layer
New pixel detector layer to be
installed this year (2013)
Will be integrated into the general
pixel readout software framework
ROD (Read Out Driver) Card will
interface with 32 FE-I4 ASICs at a
rate of 160 Mbit/s
ROD card proposes two XILINX
Spartan6 programmable devices
and one Virtex5 with Power PC
capabilities.
Commercial devices allow for reuse
of most of the VHDL code that was
designed to implement the firmware
Source (for both pictures): ATLAS IBL: Integration of on the current ROD card for the
new HW/SW readout features for the additional ATLAS pixel and SCT experiments
layer of Pixel Detector (PDF Flyer)
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Xilinx ISE Software
The Xilinx ISE (Integrated Software
Environment) Design Suite is used for
synthesis and analysis of HDL
(Hardware Description Language)
designs.
Allows developer to:
o synthesize their design
o perform timing analysis
o examine RTL diagrams
o simulate a designs reaction to
different stimuli
o configure the target device with the
programmer
Xilinx ISE 14.4 Screen Shot
Learning how to use Xilinx ISE 14.4 Source: forums.xilinx.com
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VHDL
Very High-speed Integrated Circuit
Hardware Description Language
Xilinix provides training exercises
and tutorials for beginner VHDL
programmers who have experience
coding in Verilog
Completed two 1 hour training
sessions:
o Basic HDL Coding Techniques
o Virtex 6 and Spartan 6 HDL Coding
Techniques
FPGA Prototyping by VHDL
Examples, by Pong P. Chu
Example Adder VHDL Code
Source:
http://en.wikipedia.org/wiki/File:Vhdl_signed_ad
der.png
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Next Steps
Continuing Xilinx VHDL tutorials and
exercises
Learn how to read/write/access
registers on the Spartan-6 FPGA
Continue becoming familiar with
the Off Detector Read Out
Architecture (described in IBLROD
IEEE paper)
