COMP 103

Lecture 07

Pass Transistor Logic

[All lecture notes are adapted from Mary Jane Irwin, Penn State, which were adapted from Rabaeys Digital Integrated
Circuits, 2002, J. Rabaey et al.]

Comp103-L7.1

Review: Static Complementary CMOS

High noise margins
z VOH and VOL are at VDD and
GND, respectively
VDD
Low output impedance, high
In1 input impedance
In2 PUN

No static power consumption

InN
F(In1,In2,InN) z Never a direct path between
VDD and GND in steady state
In1
In2 PDN Delay a function of load

InN capacitance and transistor on

resistance
Comparable rise and fall
PUN and PDN are dual logic networks times (under the appropriate
relative transistor sizing
conditions)
Comp103-L7.2
 NMOS Transistors in Series/Parallel

Primary inputs drive both gate and source/drain

terminals
NMOS switch closes when the gate input is high

A B
X = Y if A and B
X Y
A

B X = Y if A or B
X Y

Remember - NMOS transistors pass a strong 0 but a

weak 1

Comp103-L7.3

PMOS Transistors in Series/Parallel

Primary inputs drive both gate and source/drain

terminals
PMOS switch closes when the gate input is low
A B
X = Y if A and B = A + B
X Y
A

B X = Y if A or B = A B
X Y

Remember - PMOS transistors pass a strong 1 but a

weak 0

Comp103-L7.4
 Pass Transistor (PT) Logic
B

A
B
F=
0

Gate is static a low-impedance path exists to both

supply rails under all circumstances
N transistors instead of 2N

No static power consumption

Ratioless

Bidirectional (versus undirectional)

Comp103-L7.5

VTC of PT AND Gate

B
1.5/0.25 2

B=VDD, A=0VDD
Vout, V

0.5/0.25

1
A 0.5/0.25
B A=VDD, B=0VDD
F= AB
A=B=0VDD
0 0.5/0.25
0
0 1 2
Vin, V

z Pure PT logic is not regenerative - the signal

gradually degrades after passing through a number
of PTs (can fix with static CMOS inverter insertion)
Comp103-L7.6
 Differential PT Logic (CPL)
A
A PT Network
B F
F
B

A
A Inverse PT F
B Network F
B

B B B B B B

A A A

F=AB B F=A+B A F=AB

B

A A A
F=AB F=A+B F=AB
B B A
AND/NAND OR/NOR XOR/XNOR

Comp103-L7.7

CPL Properties

Differential so complementary data inputs and outputs

are always available (so dont need extra inverters)
Still static, since the output defining nodes are always
tied to VDD or GND through a low resistance path
Design is modular; all gates use the same topology, only
the inputs are permuted.
Simple XOR makes it attractive for structures like adders
Fast (assuming number of transistors in series is small)
Additional routing overhead for complementary signals
Still have static power dissipation problems

Comp103-L7.8
 CPL Full Adder

B B Cin Cin

A !Sum

A Sum

B B Cin Cin

A !Cout
B Cin

A Cout
B Cin

Comp103-L7.9

NMOS Only PT Driving an Inverter

In = VDD
Vx = M2
VGS
A = VDD VDD-VTn
D S
B M1

Vx does not pull up to VDD, but VDD VTn

Threshold voltage drop causes static power

consumption (M2 may be weakly conducting forming a
path from VDD to GND)
Notice VTn increases of pass transistor due to body
effect (VSB)
Comp103-L7.10
 Voltage Swing of PT Driving an Inverter

3
In
In = 0 VDD
1.5/0.25 2
x = 1.8V

Voltage, V
D
S
x
VDD Out
0.5/0.25
1
B 0.5/0.25
Out
0
0 0.5 1 1.5 2
Time, ns

Body effect large VSB at x - when pulling high (B is

tied to GND and S charged up close to VDD)
So the voltage drop is even worse
Vx = VDD - (VTn0 + ((|2f| + Vx) - |2f|))
Comp103-L7.11

Cascaded NMOS Only PTs

B = VDD B = VDD C = VDD

G
M1 x M2 y Out
M1 A = VDD
A = VDD x = VDD - VTn1
S
G
M2 y Out
C = VDD
S

Swing on y = VDD - VTn1 - VTn2 Swing on y = VDD - VTn1

z Pass transistor gates should never be cascaded as on

the left
z Logic on the right suffers from static power dissipation
and reduced noise margins
Comp103-L7.12
 Solution 1: Level Restorer

Level Restorer
on
Mr
B off
A=1 M2 Out=0
Mn
x= 0
A=0 Out =1
1
M1

Full swing on x (due to Level Restorer) so no static

power consumption by inverter
No static backward current path through Level Restorer
and PT since Restorer is only active when A is high
For correct operation Mr must be sized correctly (ratioed)

Comp103-L7.13

Transient Level Restorer Circuit Response

3 W/L2=1.50/0.25
W/Ln=0.50/0.25
W/L1=0.50/0.25

2 node x never goes below VM

of inverter so output never
switches
W/Lr=1.75/0.25
Voltage, V

W/Lr=1.50/0.25
1

W/Lr=1.25/0.25
W/Lr=1.0/0.25
0
0 100 200 300 400 500
Time, ps

Restorer has speed and power impacts: increases the

capacitance at x, slowing down the gate; increases tr (but
decreases tf)
Comp103-L7.14
 Solution 2: Multiple VT Transistors
Technology solution: Use (near) zero VT devices for the
NMOS PTs to eliminate most of the threshold drop (body
effect still in force preventing full swing to VDD)

low VT transistors
In2 = 0V A = 2.5V
on

Out

off but
leaking
In1 = 2.5V B = 0V
sneak path

Impacts static power consumption due to subthreshold

currents flowing through the PTs (even if VGS is below VT)
Comp103-L7.15

Solution 3: Transmission Gates (TGs)

Most widely used C
C
solution
A B
A B C

C = GND C = GND

A = VDD B A = GND B

C = VDD C = VDD

Full swing bidirectional switch controlled by the gate

signal C, A = B if C = 1
Comp103-L7.16
 Resistance of TG

W/Lp=0.50/0.25
30
0V
25
Rn Rp
20 2.5V Vout
Resistance, k

Rp
15 Rn
2.5V
10
Req W/Ln=0.50/0.25
5

0
0 1 2
Vout, V

Comp103-L7.17

TG Multiplexer
S S F
S
VDD

In2

S F

In1

F = !(In1 S + In2 S) GND

In1 S S In2

Comp103-L7.18
 Transmission Gate XOR

A AB

Comp103-L7.19

TG Full Adder

Cin

A Sum

Cout

Comp103-L7.20
 Differential TG Logic (DPL)

B A B A B A B A

A A

F=AB B F=AB
GND
B A

B
GND

VDD A

A F=AB B F=AB
VDD A

B B
AND/NAND XOR/XNOR

Comp103-L7.21