Advanced Scoreboard
Techniques using UVM
Franois Cerisier
Test and Verification Solutions
DVClub 9th Sept 2013
Abstract
Abstract
This presentation describes scoreboarding techniques using UVM. It reviews the
scoreboard principles and UVM features for scoreboarding and extends to more
advanced techniques to verify full transaction contents, data, attributes and
responses for data flow designs, bridges and interconnects.
The presentation will go through the analysis_port requirements, search in lists,
queues and pools and using the UVM factory to architect a generic scoreboard
for complex multi protocol interconnects.
Biography
Franois Cerisier has an Engineering Diploma in Digital Signal Processing from
PolytechSophia, University of Nice-Sophia-Antipolis and over 13 years of
experience in verification of IPs, CPUs and System-On-Chips and in
hardware/software co-verification. Franois gained verification methodology
expertise from industrial projects of major semiconductor companies (including
Infineon, Broadcom, ST-Microelectronics, ST-Ericsson, NXP) and EDA start-ups.
He is now leading Test and Verification Solutions subsidiary in France to provide
verification services and consulting.
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Agenda
Introduction
Scoreboard Principles
Case 1: Bridge / Data flow design
Case 2: More complex data flow design
Case 3: Memory controllers
Connecting Scoreboard to Agent
analysis_port
Storing and searching for referenced data
Pool
Queues
Scoreboards for complex designs
Requirements for predictor
Divide and Conquer
Using the UVM Factory
Interconnect Scoreboard Architecture Example
Conclusion
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Scoreboard Tutorials
UVM User Guide
Quick explanation how to connect a scoreboard
UVM Cookbook, Verification Academy
Straight to the code of a out of order
comparator/predictor
Books, Online Materials, UVM Trainings
A lot about UVM
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Random Verification Aspects
Verification using Constrained Random Generation :
Generation of random test scenarios
Automate tests
Functional Coverage
Know what has been automatically covered
Checks
Know that the design complies to a protocol
assertions
Know that the design does what it should do
transaction checks
scoreboards
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Scoreboard Roles
Check the design is doing what we expect
transaction content
Data, address, attributes, opcode, response code
transaction ordering
FIFO
OOO
Precedence relationship
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Data flow design example
DUT
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Typical UVM testbench
Test
sequences
sequences
Bus A VIP Bus B VIP
Master Agent sequences Slave Agent
sequencer
driver driver
vif
vif
DUT
monitor monitor
assertions assertions
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Scoreboard principles data flow design
Test
sequences
sequences
Bus A VIP Bus B VIP
Master Agent sequences Slave Agent
sequencer
driver driver
vif
vif
DUT
monitor monitor
assertions assertions
trans Ref Match ?
trans
Transaction Compare /
Storage
Predictor Search
Scoreboard
Response Scoreboard
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Scoreboard principles complex data flow design
Test
sequences
sequences
Bus A VIP Bus B VIP
Master Agent sequences Slave Agent
sequencer
driver driver
vif
vif
DUT
monitor monitor
assertions assertions
trans Ref Match ?
trans
TLM Compare /
Reference Storage
Model Search
Request Scoreboard
Response Scoreboard
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Scoreboard principles memory controller
Test
sequences
sequences
Bus A VIP Reads are checked against
Master Agent
previous Writes
sequencer
driver
vif
DUT
monitor
assertions Read
trans
Write Ref Match ?
trans trans
Transaction Compare /
Storage
Predictor Search
Scoreboard
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Connecting the scoreboard Analysis Ports
UVM 1.1 Class Reference Manual
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Connecting the scoreboard UVM Example
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Storing Data / Transactions
Storage structure strongly depends on
ordering model
FIFO queues
OOO dynamic arrays, queues
Memory associative array (indexed by address)
Others:
Associative array of queues
Data type:
Memory scalar, bytes, integers,
Data path:
Scalar
Transaction Item Class
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Storage of transactions
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Transaction Match
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Predictor / Reference Model
Predictor required when:
Compared transaction has not the same format as the
input
(protocol bridges)
Design is transforming data
(encryption, filter, encoder,)
Re-Use concern:
Encapsulation: implemented as a separated class
uvm_analysis_port / imp to connect
UVM Factory to extend, replace existing objects
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Divide and Conquer
What if the design has
Different transaction paths/routes
Different behaviour depending on
Address segments
Opcodes or other transaction attributes
Option 1: TLM Reference Model
Option 2: Divide and Conquer
Replace complex predictor with several simpler
scoreboards
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Divide and Conquer AXI read/write separation
DUT scoreboard
FIFO read
scoreboard
FIFO write
scoreboard
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Improving reuse
UVM Factory
Same architecture
Different implementation, different behavior
OOO read
DUT scoreboard scoreboard
FIFO read
scoreboard
FIFO write
scoreboard
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Complex NoC / Fabrics scoreboard example
DUT
NoC
Master 5 AHB APB Slave 4
Master VIP to Scbd VIP to Scbd Slave
NoC Scoreboard VIP
VIP Monitors adapters Address Map & adapters VIP Monitors
AHB
Configuration
AHB adapter Master I/F 5
Monitor
UVM
Agent
APB UVM
Slave I/F 4 AHB adapter
Monitor Agent
UVM AXI
AXI adapter Master I/F 4
Agent Monitor
AHB UVM
UVM Slave I/F 3 AHB adapter
OCP Monitor Agent
OCP adapter Master I/F 3
Agent Monitor
UVM AXI / ACE-Lite AXI UVM
AXI adapter Master I/F 2 Route M2 to S2 Slave I/F 2 AHB adapter
Monitor
Agent Monitor Agent
ACE Scoreboard
AXI
AXI adapter Master I/F 1 OCP UVM
Monitor Route M1 to S1 Slave I/F 1 AHB adapter
Coherency Domain
UVM ACE Master ACE I/F
Monitor Agent
ACE adapter
Agent Monitor 1
AXI AXI UVM
AXI adapter Slave I/F 0 AHB adapter
Monitor
Master I/F 0 Route M0 to S0 Monitor Agent
UVM ACE Master ACE I/F
ACE adapter
Agent Monitor 0 th
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Conclusion
Scoreboards verify transaction functional correctness
SystemVerilog provides agregate types for transaction storage &
search
Dynamic Arrays, Associative Arrays, Queues, Classes
UVM ease scoreboard development, providing:
UVM analysis ports ( easier than call backs)
uvm_transaction compare() / do_compare() methods
UVM factory for extension, replacement & reuse.
Divide and Conquer:
keep simple things simple.
Compose simple blocks to build complex behavior
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Thank you
Questions?
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