I. Blocking vs.

Nonblocking Assignments
Verilog supports two types of assignments within always
blocks, with subtly different behaviors.
Blocking assignment: evaluation and assignment are immediate
always @ (a or b or c)
begin
x = a | b; 1. Evaluate a | b, assign result to x
y = a ^ b ^ c; 2. Evaluate a^b^c, assign result to y
z = b & ~c; 3. Evaluate b&(~c), assign result to z
end
Nonblocking assignment: all assignments deferred until all
right-hand sides have been evaluated (end of simulation
timestep)
always @ (a or b or c)
begin
x <= a | b; 1. Evaluate a | b but defer assignment of x
y <= a ^ b ^ c; 2. Evaluate a^b^c but defer assignment of y
z <= b & ~c; 3. Evaluate b&(~c) but defer assignment of z
end 4. Assign x, y, and z with their new values

Sometimes, as above, both produce the same result.

Sometimes, not!
6.111 Fall 2007 Lecture 6, Slide 1
 Why two ways of assigning values?
Conceptual need for two kinds of assignment (in always blocks):

a a x
b
b c y

Blocking: a = b x = a & b
Evaluation and assignment
are immediate b = a y = x | c
Non-Blocking: a <= b x <= a & b
Assignment is postponed until
all r.h.s. evaluations are done b <= a y <= x | c
When to use: Sequential Combinational
( only in always blocks! ) Circuits Circuits

6.111 Fall 2007 Lecture 6, Slide 2

 Assignment Styles for Sequential Logic

Flip-Flop Based q1 q2
in D Q D Q D Q out
Digital Delay
Line
clk

Will nonblocking and blocking assignments both

produce the desired result?
module nonblocking(in, clk, out); module blocking(in, clk, out);
input in, clk; input in, clk;
output out; output out;
reg q1, q2, out; reg q1, q2, out;
always @ (posedge clk) always @ (posedge clk)
begin begin
q1 <= in; q1 = in;
q2 <= q1; q2 = q1;
out <= q2; out = q2;
end end
endmodule endmodule

6.111 Fall 2007 Lecture 6, Slide 3

 Use Nonblocking for Sequential Logic
always @ (posedge clk) always @ (posedge clk)
begin begin
q1 <= in; q1 = in;
q2 <= q1; q2 = q1;
out <= q2; out = q2;
end end
At each rising clock edge, q1, q2, and At each rising clock edge, q1 = in.
out simultaneously receive the old values After that, q2 = q1 = in; After that,
of in, q1, and q2. out = q2 = q1 = in; Finally out = in.

q1 q2 q1 q2
in D Q D Q D Q out in D Q out

clk clk

Blocking assignments do not reflect the intrinsic behavior of

multi-stage sequential logic

Guideline: use nonblocking assignments for

sequential always blocks
6.111 Fall 2007 Lecture 6, Slide 4
 Use Blocking for Combinational Logic
Blocking Behavior abc xy
always @ (a or b or c)
(Given) Initial Condition 110 11 begin
a changes; x = a & b;
always block triggered 010 11
y = x | c; a x
x = a & b; 010 01 b
end y
y = x | c; 010 00 c

Nonblocking Behavior abc xy Deferred

(Given) Initial Condition 110 11
a changes; always @ (a or b or c)
always block triggered 010 11 begin
x <= a & b; 010 11 x<=0 x <= a & b;
y <= x | c; 010 11 x<=0, y<=1 y <= x | c;
end
Assignment completion 010 01

Nonblocking assignments do not reflect the intrinsic behavior of

multi-stage combinational logic
While nonblocking assignments can be hacked to simulate correctly
(expand the sensitivity list), its not elegant
Guideline: use blocking assignments for
combinational always blocks
6.111 Fall 2007 Lecture 6, Slide 5
 II. Single-clock Synchronous Circuits
Well use Flip Flops and Registers groups of FFs sharing a clock input in a
highly constrained way to build digital systems.

Single-clock Synchronous Discipline:

No combinational cycles
Single clock signal shared among
all clocked devices
Only care about value of
combinational circuits just
before rising edge of clock
Period greater than every
combinational delay
Change saved state after noise-
inducing logic transitions have
stopped!

6.111 Fall 2007 Lecture 6, Slide 6

 Clocked circuit for on/off button
module onoff(clk,button,light);
input clk,button;
Does this work
output light; with a 1Mhz
reg light; CLK?
always @ (posedge clk)
begin
if (button) light <= ~light;
end
endmodule
0
D
1
Q
LE D Q LIGHT
BUTTON
CLK
CLK

SINGLE GLOBAL CLOCK LOAD-ENABLED REGISTER

6.111 Fall 2007 Lecture 6, Slide 7
 Asynchronous Inputs in Sequential Systems
What about external signals?
Cant guarantee
Sequential System setup and hold
times will be met!
Clock

When an asynchronous signal causes a setup/hold

violation...
I II III
Q ?

D
Clock
Transition is missed on Transition is caught on Output is metastable
first clock cycle, but first clock cycle. for an indeterminate
caught on next clock amount of time.
cycle.
Q: Which cases are problematic?
6.111 Fall 2007 Lecture 6, Slide 8
 Asynchronous Inputs in Sequential Systems

All of them can be, if more than one happens

simultaneously within the same circuit.
Idea: ensure that external signals directly feed
exactly one flip-flop
Clocked
Synchronous
System
Async Q0
D Q
Input
Sequential System
D Q Clock

Q1
D Q

Clock
Clock

This prevents the possibility of I and II occurring in different places

in the circuit, but what about metastability?

6.111 Fall 2007 Lecture 6, Slide 9

 Handling Metastability
Preventing metastability turns out to be an impossible problem
High gain of digital devices makes it likely that metastable
conditions will resolve themselves quickly
Solution to metastability: allow time for signals to stabilize
Can be Very unlikely to be Extremely unlikely to
metastable metastable for >1 be metastable for >2
right after clock cycle clock cycle
sampling

Complicated
D Q D Q D Q Sequential Logic
System

Clock

How many registers are necessary?

Depends on many design parameters(clock speed, device speeds, )
In 6.111, a pair of synchronization registers is sufficient

6.111 Fall 2007 Lecture 6, Slide 10

 III. Finite State Machines
Finite State Machines (FSMs) are a useful abstraction for
sequential circuits with centralized states of operation
At each clock edge, combinational logic computes outputs and
next state as a function of inputs and present state

inputs Combinational outputs

+ Logic +
present next
state state

n n

Q Flip- D
Flops
CLK

6.111 Fall 2007 Lecture 6, Slide 11

 Example 1: Light Switch
State transition diagram

BUTTON=1

LIGHT LIGHT
BUTTON=0 BUTTON=0
= 0 = 1

BUTTON=1

Logic diagram
Combinational logic

1
D Q LIGHT
BUTTON
CLK

6.111 Fall 2007

Register Lecture 6, Slide 12
 Example 2: 4-bit Counter
Logic diagram

4 4
+1 count

Verilog clk
# 4-bit counter
module counter(clk, count);
input clk;
output [3:0] count;
reg [3:0] count;

always @ (posedge clk) begin

count <= count+1;
end
endmodule
6.111 Fall 2007 Lecture 6, Slide 13
 Example 2: 4-bit Counter
Logic diagram

4 4
+1 1 count

Verilog enb clk

# 4-bit counter with enable
module counter(clk,enb,count);
input clk,enb;
output [3:0] count; Could I use the following instead?
reg [3:0] count; if (enb) count <= count+1;

always @ (posedge clk) begin

count <= enb ? count+1 : count;
end
endmodule
6.111 Fall 2007 Lecture 6, Slide 14
 Example 2: 4-bit Counter
Logic diagram

0 1 4 4
+1 1 count
0
0

Verilog enb clr clk

# 4-bit counter with enable and synchronous clear
module counter(clk,enb,clr,count); Isnt this a lot like
input clk,enb,clr; Exercise 1 in Lab 2?

output [3:0] count;

reg [3:0] count;

always @ (posedge clk) begin

count <= clr ? 4b0 : (enb ? count+1 : count);
end
endmodule
6.111 Fall 2007 Lecture 6, Slide 15
 Two Types of FSMs
Moore and Mealy FSMs : different output generation
Moore FSM:
next
state
S+
inputs outputs
Comb. D Flip- Q Comb.
x0...xn Logic
n
Flops Logic yk = fk(S)
CLK
n

present state S

Mealy FSM:
direct combinational path!
outputs
yk = fk(S, x0...xn)
inputs S+ Comb.
Comb. D Flip- Q
x0...xn n Logic
Logic Flops
CLK
n

6.111 Fall 2007 Lecture 6, Slide 16

 Design Example: Level-to-Pulse
A level-to-pulse converter produces a
single-cycle pulse each time its input goes
high.
Its a synchronous rising-edge detector.
Sample uses:
Buttons and switches pressed by humans for
arbitrary periods of time
Single-cycle enable signals for counters

Level to
L Pulse P
Converter
...output P produces a
Whenever input L goes
single pulse, one clock
from low to high...
CLK period wide.

6.111 Fall 2007 Lecture 6, Slide 17

 Step 1: State Transition Diagram
Block diagram of desired system:
Synchronizer Edge Detector

unsynchronized Level to
user input
D Q D Q L Pulse P
FSM
CLK

State transition diagram is a useful FSM representation and

design aid:
if L=1 at the clock edge,
then jump to state 01.
L=1 L=1 Binary values of states

00 01 11
L=0 Low input, High input,
Waiting for rise
Edge Detected!
Waiting for fall
L=1
P=0 P=1 P=0
L=0
L=0
if L=0 at the clock edge, This is the output that results from
then stay in state 00. this state. (Moore or Mealy?)

6.111 Fall 2007 Lecture 6, Slide 18

 Step 2: Logic Derivation
Transition diagram is readily converted to a Curren Next
In Out
t State State
state transition table (just a truth table)
S1 S0 L S1+ S0+ P
L=1 L=1
0 0 0 0 0 0
L=0 L=1 0 0 1 0 1 0
00 01 11
Low input, High input,
Waiting for rise
Edge Detected!
Waiting for fall
0 1 0 0 0 1
P=1
P=0 P=0 0 1 1 1 1 1
L=0 L=0
1 1 0 0 0 0
1 1 1 1 1 0
Combinational logic may be derived using Karnaugh maps
+
S1S0 for S1 :
L 00 01 11 10
0 0 0 0 X
1 0 1 1 X L S+ P
Comb. D Flip- Q Comb.
n S1
for P:
+: Logic Flops Logic
S1S0 for S0 CLK S0 0 1
L 00 01 11 10 n
0 0 X
0 0 0 0 X S 1 1 0
S1+ = LS0 P = S1S0
1 1 1 1 X
S0 + = L

6.111 Fall 2007 Lecture 6, Slide 19

 Moore Level-to-Pulse Converter
next
state
S+
inputs outputs
Comb. D Flip- Q Comb.
x0...xn Logic
n
Flops Logic yk = fk(S)
CLK
n

present state S
S1 = LS0
+
P = S1S0
S0 + = L

Moore FSM circuit implementation of level-to-pulse converter:

S0 + S0
L D Q
P
CLK Q

D Q
S1 + S1
Q

6.111 Fall 2007 Lecture 6, Slide 20

 Design of a Mealy Level-to-Pulse
direct combinational path!

S+ Comb.
Comb. D Flip- Q
n Logic
Logic Flops
CLK
n
S

Since outputs are determined by state and inputs, Mealy FSMs

may need fewer states than Moore FSM implementations
1. When L=1 and S=0, this output is
asserted immediately and until the
state transition occurs (or L changes). L 1
2
P
L=1 | P=1 Clock
L=0 | P=0 0 1 State
Input is low Input is high
Output transitions immediately.
L=0 | P=0
State transitions at the clock edge.
L=1 | P=0
2. While in state S=1 and as long as L
remains at 1, this output is asserted.

6.111 Fall 2007 Lecture 6, Slide 21

 Mealy Level-to-Pulse Converter
Pres. Next
In Out
L=1 | P=1 State State
0 1 S L S+ P
Input is low Input is high
0 0 0 0
L=0 | P=0 0 1 1 1
L=0 | P=0 L=1 | P=0
1 0 0 0
1 1 1 0

Mealy FSM circuit implementation of level-to-pulse converter:

P
S+ S
L D Q

CLK Q
S

FSMs state simply remembers the previous value of L

Circuit benefits from the Mealy FSMs implicit single-
cycle assertion of outputs during state transitions

6.111 Fall 2007 Lecture 6, Slide 22

 Moore/Mealy Trade-Offs

How are they different?

Moore: outputs = f( state ) only
Mealy outputs = f( state and input )
Mealy outputs generally occur one cycle earlier than a Moore:

Moore: delayed assertion of P Mealy: immediate assertion of P

L L

P P

Clock Clock

State[0] State

Compared to a Moore FSM, a Mealy FSM might...

Be more difficult to conceptualize and design
Have fewer states

6.111 Fall 2007 Lecture 6, Slide 23

 Light Switch Revisited

1
D Q LIGHT

BUTTON D Q

CLK

Level-to-Pulse Light Switch

FSM FSM

6.111 Fall 2007 Lecture 6, Slide 24