PIC16F627A/628A/648A

4.0 MEMORY ORGANIZATION 4.2 Data Memory Organization

The data memory (Figure 4-2 and Figure 4-3) is
4.1 Program Memory Organization partitioned into four banks, which contain the General
The PIC16F627A/628A/648A has a 13-bit program Purpose Registers (GPRs) and the Special Function
counter capable of addressing an 8K x 14 program Registers (SFRs). The SFRs are located in the first 32
memory space. Only the first 1K x 14 (0000h-03FFh) locations of each bank. There are General Purpose
for the PIC16F627A, 2K x 14 (0000h-07FFh) for the Registers implemented as static RAM in each bank.
PIC16F628A and 4K x 14 (0000h-0FFFh) for the Table 4-1 lists the General Purpose Register available
PIC16F648A are physically implemented. Accessing a in each of the four banks.
location above these boundaries will cause a wrap-
around within the first 1K x 14 space (PIC16F627A), TABLE 4-1: GENERAL PURPOSE STATIC
2K x 14 space (PIC16F628A) or 4K x 14 space RAM REGISTERS
(PIC16F648A). The Reset vector is at 0000h and the PIC16F627A/628A PIC16F648A
interrupt vector is at 0004h (Figure 4-1).
Bank0 20-7Fh 20-7Fh
FIGURE 4-1: PROGRAM MEMORY MAP Bank1 A0h-FF A0h-FF
AND STACK Bank2 120h-14Fh, 170h-17Fh 120h-17Fh
PC<12:0> Bank3 1F0h-1FFh 1F0h-1FFh
CALL, RETURN 13 Addresses F0h-FFh, 170h-17Fh and 1F0h-1FFh are
RETFIE, RETLW implemented as common RAM and mapped back to
addresses 70h-7Fh.
Stack Level 1
Stack Level 2 Table 4-2 lists how to access the four banks of registers
via the Status register bits RP1 and RP0.

Stack Level 8 TABLE 4-2: ACCESS TO BANKS OF

REGISTERS
Reset Vector 000h Bank RP1 RP0
0 0 0
1 0 1
Interrupt Vector 0004 2 1 0
On-chip Program 0005
3 1 1
Memory
PIC16F627A, 4.2.1 GENERAL PURPOSE REGISTER
PIC16F628A and FILE
PIC16F648A
The register file is organized as 224 x 8 in the
03FFh
PIC16F627A/628A and 256 x 8 in the PIC16F648A.
Each is accessed either directly or indirectly through
On-chip Program
Memory the File Select Register (FSR), See Section 4.4
Indirect Addressing, INDF and FSR Registers.
PIC16F628A and
PIC16F648A
07FFh

On-chip Program
Memory
PIC16F648A only

0FFFh

1FFFh

2009 Microchip Technology Inc. DS40044G-page 17

PIC16F627A/628A/648A
FIGURE 4-2: DATA MEMORY MAP OF THE PIC16F627A AND PIC16F628A
File
Address

Indirect addr.(1) 00h Indirect addr.(1) 80h Indirect addr.(1) 100h Indirect addr.(1) 180h
TMR0 01h OPTION 81h TMR0 101h OPTION 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h 105h 185h
PORTB 06h TRISB 86h PORTB 106h TRISB 186h
07h 87h 107h 187h
08h 88h 108h 188h
09h 89h 109h 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch 10Ch 18Ch
0Dh 8Dh 10Dh 18Dh
TMR1L 0Eh PCON 8Eh 10Eh 18Eh
TMR1H 0Fh 8Fh 10Fh 18Fh
T1CON 10h 90h
TMR2 11h 91h
T2CON 12h PR2 92h
13h 93h
14h 94h
CCPR1L 15h 95h
CCPR1H 16h 96h
CCP1CON 17h 97h
RCSTA 18h TXSTA 98h
TXREG 19h SPBRG 99h
RCREG 1Ah EEDATA 9Ah
1Bh EEADR 9Bh
1Ch EECON1 9Ch
1Dh EECON2(1) 9Dh
1Eh 9Eh
CMCON 1Fh VRCON 9Fh 11Fh
20h General 120h
A0h Purpose
General General Register
Purpose Purpose 48 Bytes 14Fh
Register Register
150h
80 Bytes
80 Bytes

6Fh EFh 16Fh 1EFh

70h F0h 170h 1F0h
accesses accesses accesses
16 Bytes
70h-7Fh 70h-7Fh 70h-7Fh
7Fh FFh 17Fh 1FFh
Bank 0 Bank 1 Bank 2 Bank 3

Unimplemented data memory locations, read as 0.

Note 1: Not a physical register.

DS40044G-page 18 2009 Microchip Technology Inc.

 PIC16F627A/628A/648A
FIGURE 4-3: DATA MEMORY MAP OF THE PIC16F648A
File
Address

Indirect addr.(1) 00h Indirect addr.(1) 80h Indirect addr.(1) 100h Indirect addr.(1) 180h
TMR0 01h OPTION 81h TMR0 101h OPTION 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h 105h 185h
PORTB 06h TRISB 86h PORTB 106h TRISB 186h
07h 87h 107h 187h
08h 88h 108h 188h
09h 89h 109h 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch 10Ch 18Ch
0Dh 8Dh 10Dh 18Dh
TMR1L 0Eh PCON 8Eh 10Eh 18Eh
TMR1H 0Fh 8Fh 10Fh 18Fh
T1CON 10h 90h
TMR2 11h 91h
T2CON 12h PR2 92h
13h 93h
14h 94h
CCPR1L 15h 95h
CCPR1H 16h 96h
CCP1CON 17h 97h
RCSTA 18h TXSTA 98h
TXREG 19h SPBRG 99h
RCREG 1Ah EEDATA 9Ah
1Bh EEADR 9Bh
1Ch EECON1 9Ch
1Dh EECON2(1) 9Dh
1Eh 9Eh
CMCON 1Fh VRCON 9Fh 11Fh
20h 120h
A0h
General General General
Purpose Purpose Purpose
Register Register Register
80 Bytes 80 Bytes
80 Bytes

6Fh EFh 16Fh 1EFh

70h F0h 170h 1F0h
accesses accesses accesses
16 Bytes
70h-7Fh 70h-7Fh 70h-7Fh
7Fh FFh 17Fh 1FFh
Bank 0 Bank 1 Bank 2 Bank 3

Unimplemented data memory locations, read as 0.

Note 1: Not a physical register.

2009 Microchip Technology Inc. DS40044G-page 19

PIC16F627A/628A/648A
4.2.2 SPECIAL FUNCTION REGISTERS
The SFRs are registers used by the CPU and Periph-
eral functions for controlling the desired operation of
the device (Table 4-3). These registers are static RAM.
The special registers can be classified into two sets
(core and peripheral). The SFRs associated with the
core functions are described in this section. Those
related to the operation of the peripheral features are
described in the section of that peripheral feature.

TABLE 4-3: SPECIAL REGISTERS SUMMARY BANK0

Value on
Details
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR
on Page
Reset(1)

Bank 0
00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 30
01h TMR0 Timer0 Modules Register xxxx xxxx 47
02h PCL Program Counters (PC) Least Significant Byte 0000 0000 30
03h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 24
04h FSR Indirect Data Memory Address Pointer xxxx xxxx 30
05h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx 0000 33
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 38
07h Unimplemented
08h Unimplemented
09h Unimplemented
0Ah PCLATH Write Buffer for upper 5 bits of Program Counter ---0 0000 30
0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 26
0Ch PIR1 EEIF CMIF RCIF TXIF CCP1IF TMR2IF TMR1IF 0000 -000 28
0Dh Unimplemented
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 50
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 50
10h T1CON T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 50
11h TMR2 TMR2 Modules Register 0000 0000 54
12h T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 54
13h Unimplemented
14h Unimplemented
15h CCPR1L Capture/Compare/PWM Register (LSB) xxxx xxxx 57
16h CCPR1H Capture/Compare/PWM Register (MSB) xxxx xxxx 57
17h CCP1CON CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 57
18h RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 000x 74
19h TXREG USART Transmit Data Register 0000 0000 79
1Ah RCREG USART Receive Data Register 0000 0000 82
1Bh Unimplemented
1Ch Unimplemented
1Dh Unimplemented
1Eh Unimplemented
1Fh CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 63
Legend: - = Unimplemented locations read as 0, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: For the initialization condition for registers tables, refer to Table 14-6 and Table 14-7.

DS40044G-page 20 2009 Microchip Technology Inc.

 PIC16F627A/628A/648A
TABLE 4-4: SPECIAL FUNCTION REGISTERS SUMMARY BANK1
Value on
Details
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR
on Page
Reset(1)
Bank 1
80h INDF Addressing this location uses contents of FSR to address data memory (not a physical xxxx xxxx 30
register)
81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 25
82h PCL Program Counters (PC) Least Significant Byte 0000 0000 30
83h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 24
84h FSR Indirect Data Memory Address Pointer xxxx xxxx 30
85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 33
86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 38
87h Unimplemented
88h Unimplemented
89h Unimplemented
8Ah PCLATH Write Buffer for upper 5 bits of Program Counter ---0 0000 30
8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 26
8Ch PIE1 EEIE CMIE RCIE TXIE CCP1IE TMR2IE TMR1IE 0000 -000 27
8Dh Unimplemented
8Eh PCON OSCF POR BOR ---- 1-0x 29
8Fh Unimplemented
90h Unimplemented
91h Unimplemented
92h PR2 Timer2 Period Register 1111 1111 54
93h Unimplemented
94h Unimplemented
95h Unimplemented
96h Unimplemented
97h Unimplemented
98h TXSTA CSRC TX9 TXEN SYNC BRGH TRMT TX9D 0000 -010 73
99h SPBRG Baud Rate Generator Register 0000 0000 75
9Ah EEDATA EEPROM Data Register xxxx xxxx 91
9Bh EEADR EEPROM Address Register xxxx xxxx 92
9Ch EECON1 WRERR WREN WR RD ---- x000 92
9Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- 92
9Eh Unimplemented
9Fh VRCON VREN VROE VRR VR3 VR2 VR1 VR0 000- 0000 69
Legend: - = Unimplemented locations read as 0, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: For the initialization condition for registers tables, refer to Table 14-6 and Table 14-7.

2009 Microchip Technology Inc. DS40044G-page 21

PIC16F627A/628A/648A
TABLE 4-5: SPECIAL FUNCTION REGISTERS SUMMARY BANK2
Value on
Details
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR
on Page
Reset(1)
Bank 2
100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 30

101h TMR0 Timer0 Modules Register xxxx xxxx 47

102h PCL Program Counters (PC) Least Significant Byte 0000 0000 30
103h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 24
104h FSR Indirect Data Memory Address Pointer xxxx xxxx 30
105h Unimplemented
106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 38
107h Unimplemented
108h Unimplemented
109h Unimplemented
10Ah PCLATH Write Buffer for upper 5 bits of Program Counter ---0 0000 30
10Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 26
10Ch Unimplemented
10Dh Unimplemented
10Eh Unimplemented
10Fh Unimplemented
110h Unimplemented
111h Unimplemented
112h Unimplemented
113h Unimplemented
114h Unimplemented
115h Unimplemented
116h Unimplemented
117h Unimplemented
118h Unimplemented
119h Unimplemented
11Ah Unimplemented
11Bh Unimplemented
11Ch Unimplemented
11Dh Unimplemented
11Eh Unimplemented
11Fh Unimplemented
Legend: - = Unimplemented locations read as 0, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented.
Note 1: For the initialization condition for registers tables, refer to Table 14-6 and Table 14-7.

DS40044G-page 22 2009 Microchip Technology Inc.

 PIC16F627A/628A/648A
TABLE 4-6: SPECIAL FUNCTION REGISTERS SUMMARY BANK3
Value on
Details
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR
on Page
Reset(1)
Bank 3
180h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 30
181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 25
182h PCL Program Counters (PC) Least Significant Byte 0000 0000 30
183h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 24
184h FSR Indirect Data Memory Address Pointer xxxx xxxx 30
185h Unimplemented
186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 38
187h Unimplemented
188h Unimplemented
189h Unimplemented
18Ah PCLATH Write Buffer for upper 5 bits of Program Counter ---0 0000 30
18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 26
18Ch Unimplemented
18Dh Unimplemented
18Eh Unimplemented
18Fh Unimplemented
190h Unimplemented
191h Unimplemented
192h Unimplemented
193h Unimplemented
194h Unimplemented
195h Unimplemented
196h Unimplemented
197h Unimplemented
198h Unimplemented
199h Unimplemented
19Ah Unimplemented
19Bh Unimplemented
19Ch Unimplemented
19Dh Unimplemented
19Eh Unimplemented
19Fh Unimplemented
Legend: - = Unimplemented locations read as 0, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: For the initialization condition for registers tables, refer to Table 14-6 and Table 14-7.

2009 Microchip Technology Inc. DS40044G-page 23