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Programming Assignment Solution-Week2

The document provides solutions to 3 programming assignments involving Verilog modules: 1) A 4-bit ripple carry adder module implemented using four 1-bit full adder modules. 2) A 4-bit latch module implemented using four D-type latch modules with a common enable input. 3) A 4-to-1 multiplexer module implemented using logic gates that select one of four inputs according to a 2-bit selection value.

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MADAN Mady
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121 views

Programming Assignment Solution-Week2

The document provides solutions to 3 programming assignments involving Verilog modules: 1) A 4-bit ripple carry adder module implemented using four 1-bit full adder modules. 2) A 4-bit latch module implemented using four D-type latch modules with a common enable input. 3) A 4-to-1 multiplexer module implemented using logic gates that select one of four inputs according to a 2-bit selection value.

Uploaded by

MADAN Mady
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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WEEK-2: PROGRAMMING ASSIGNMENT SOLUTIONS

ASSIGNMENT 1: 4-bit adder

Write a verilog module to implement a 4-bit ripple carry adder. The module will take the
following arguments:
i. Two 4-bit inputs A and B,
ii. 1-bit carry input Cin,
iii. 4-bit output Sum,
iv. 1-bit carry output Cout
Implement the above module by instantiating four 1-bit full adder (A 1-bit full adder
takes as arguments two input bits to add, a carry input bit, one bit sum and one bit
output carry).

//write the verilog modules to implement 4-bit ripple carry adder and
//keep the module name of 4-bit adder "rcadder_4"

module rcadder_4 (A, B, Cin, Sum, Cout);


input [3:0] A, B;
input Cin;
output [3:0] Sum;
output Cout;
wire c1, c2, c3;

fulladder FA0 (A[0], B[0], Cin, Sum[0], c1);


fulladder FA1 (A[1], B[1], c1, Sum[1], c2);
fulladder FA2 (A[2], B[2], c2, Sum[2], c3);
fulladder FA3 (A[3], B[3], c3, Sum[3], Cout);
endmodule

module fulladder (a, b, cin, sum, cout);


input a, b, cin;
output sum, cout;

assign sum = a ^ b ^ cin;


assign cout = (a & b) | (b & cin) | (cin & a);
endmodule

IMPORTANT POINTS:
The order of the arguments was clearly mentioned in the problem statement.
You can of course use any names for the arguments.
The test bench that evaluates the program will apply the inputs in this specific
order.
ASSIGNMENT 2: 4-bit latch

Write verilog modules to implement a 4-bit latch, by instantiating four D-type latch. The
module will take as arguments the following:
i. 4-bit D inputs for all four D-latches
ii. 1-bit latch enable input En
iii. 4-bit Q outputs from all four D-latches
Here all four D-latches activates on a common enable En input line.

//Write the verilog modules for D-latch here and


//keep the name of 4-bit D-latch "dlatch4"

module dlatch4 (D, En, Q);


input [3:0] D;
input En;
output [3:0] Q;

latch L0 (D[0], En, Q[0]);


latch L1 (D[1], En, Q[1]);
latch L2 (D[2], En, Q[2]);
latch L3 (D[3], En, Q[3]);
endmodule

module latch (d, en, q);


input d, en;
output q;
reg q;

always @(d or en)


if (en) q = d;
endmodule

IMPORTANT POINTS:
The order of the arguments was clearly mentioned in the problem statement.
You can of course use any names for the arguments.
The test bench that evaluates the program will apply the inputs in this specific
order.
ASSIGNMENT 3: 4-to-1 Multiplexer

Write verilog module to implement a 4-to-1 multiplexer by using gate level structural
description. The module will take as arguments the following:
i. 4 input bits,
ii. 2 selection bits and
iii. 1 output bit.
Realize the operation of 4-to-1 multiplexer by instantiating required number of different
logical gates and passing appropriate input and output parameters to each such logic
gate.

//Write the verilog modules for 4-to-1 multiplexer here and


//keep the module name of 4-to-1 multiplexer "mux4x1"

module mux4x1 (in, sel, out);


input [3:0] in;
input [1:0] sel;
output out;
wire sel0bar, sel1bar, t0, t1, t2, t3;

not N0 (sel0bar, sel[0]);


not N1 (sel1bar, sel[1]);
and A0 (t0, in[0], sel1bar, sel0bar); // select when sel=00
and A1 (t1, in[1], sel1bar, sel[0]); // select when sel=01
and A2 (t2, in[2], sel[1], sel0bar); // select when sel=10
and A3 (t3, in[3], sel[1], sel[0]); // select when sel=11
or O1 (out, t0, t1, t2, t3);
endmodule

IMPORTANT POINTS:
The order of the arguments was clearly mentioned in the problem statement.
You can of course use any names for the arguments.
The select input has to be applied properly. If sel = 00; in[0] should be selected;
if sel = 01, in[1] should be selected; if sel = 10, in[2] should be selected; if sel =
11, in[3] should be selected.
In the sample test cases the two pass cases has been mentioned as:
For s = 00 and a = 0001, out = 1
For s = 00 and a = 0010, out = 0
This clearly shows that the rightmost bit of a is a[0]. If s = 01, the second bit from
the right should be selected, and so on.

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