Verilog for Sequential circuits

Example of D -LATCH

module dlatch(D, Clk, Q);

input D, clk;
output reg Q;

always @(D, clk)

if (clk )
Q = D;
else
Q = Q;
endmodule 36
 Verilog for Sequential circuits
Example of D Flip flop

can use posedge or module dff(D, clk, Q);

negedge as desired input D, clk;
output reg Q;
sensitivity list cannot
contain both edge- always @(posedge clk)
triggered and level Q=D;
sensitive signals
endmodule

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 D flip-flop with clear/reset
module dff(D, clk, reset, Q);
input D, clk, reset; Asynchronous clear
output reg Q;

always @(posedge clk, negedge reset)

begin
if (!reset)
Q <= 0;
else
Q <= D;
end
endmodule 38
 D flip-flop with synchronous reset
module dff(D, clk, reset, Q);
input D, clk, reset;
output reg Q;

always @(posedge clk)

begin
if (!reset)
Q <= 0;
else
Q <= D;
end
endmodule 39
 D flip-flop with clear/reset
module dff(D, clk, reset, Q);
input D, clk, reset; Asynchronous clear
output reg Q;

always @(posedge clk, negedge reset)

begin
if (!reset)
Q <= 0;
else
Q <= D;
end
endmodule 40
 D flip-flop with synchronous reset
module dff(D, clk, reset, Q);
input D, clk, reset;
output reg Q;

always @(posedge clk)

begin
if (!reset)
Q <= 0;
else
Q <= D;
end
endmodule 41
 Example for blocking and Non-blocking statements

module ex1(x1,x2,x3, clk, module ex1(x1,x2,x3, clk,

f,g); f,g);
input clk, x1, x2, x3; input clk, x1, x2, x3;
output reg g, f; output reg g, f;

always @(posedge clk) always @(posedge clk)

begin begin
f = x1&x2; f <= x1&x2;
g = f | x3; g <= f | x3;
end end
endmodule endmodule
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 Blocking and non-blocking assignments

module dff(D, clk, Q1, Q2); module dff(D, clk, Q1, Q2);
input D, clk; input D, clk;
output reg Q1, Q2; output reg Q1, Q2;

always @(posedge clk) always @(posedge clk)

begin begin
Q1 = D; Q1 <= D;
Q2 = Q1; Q2 <= Q1;
end end
endmodule endmodule

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 4-bit shift register
module shiftreg (D, Load, w, clk, Q);
input [3:0] D;
input Load, w, clk;
0 0 0
output reg [3:0] Q ;

always @(posedge clk)

if(Load)
Q <= D;
else begin
Q[0] <= w;
Q[1] <= Q[0];
Q[2] <= Q[1];
Q[3] <= Q[2];
end
endmodule
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 n-bit shift register
module shiftreg(D, L, w, clk, Q);
parameter n = 16;
input [n-1:0] D;
input L, w, clk;
output reg [n-1:0] Q ;
integer k;
always @(posedge clk)
if(L)
Q <= D;
else
begin
Q[0] <= w;
for (k =0; k<n-1; k=k+1)
Q[k+1] <= Q[k] ;
end
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endmodule
 4-bit UP counter
module up_counter(clk, reset, enable, Q);
input clk, reset, enable;
output reg [3:0] Q;

always @(posedge clk, negedge reset)

if(!reset)
Q <= 0;
else if (enable)
Q <= Q + 1;

endmodule
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 4-bit UP counter with parallel load
module up_counter(D, clk, reset, enable, load, Q);
input [3:0] D;
input clk, reset, enable, load;
output reg [3:0] Q;
always @(posedge clk, negedge reset)
if(!reset)
Q <= 0;
else if (load) Note the sequence!!
Q <= D;
else if (enable)
Q <= Q + 1;
endmodule
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 Four-Valued Logic
Verilog Logic Values
The underlying data representation allows for any bit to have one
of four values
1, 0, x (unknown), z (high impedance)
x one of: 1, 0, z, or in the state of change
z the high impedance output of a tri-state gate.
What basis do these have in reality?
0, 1 no question
z A tri-state gate drives either a zero or one on its outputand if
its not doing that, its output is high impedance (z). Tri-state gates
are real devices and z is a real electrical affect.
x not a real value. There is no real gate that drives an x on to a
wire. x is used as a debugging aid. x means the simulator cant
determine the answer and so maybe you should worry! All values
in a simulation start as x.

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 Four-Valued Logic
Logic with multi-level logic values
Logic with these four values make sense
Nand anything with a 0, and you get a 1. This includes having an x
or z on the other input. Thats the nature of the nand gate
Nand two xs and you get an x makes sense!
Note: z treated as an x on input. Their rows and columns
are the same
If you forget to connect an input it will be seen as an z.
At the start of simulation, everything is an x.
Input B
A
Nand 0 1 x z B
0 1 1 1 1
Input A

1 1 0 x x A 4-valued truth table for a

x 1 x x x Nand gate with two inputs
z 1 x x x
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 Verilog syntax

Modules and signals names must begin with a letter

and can contain letter or number plus _ and $
Verilog is case sensitive
White spaces are ignored
Comments begin with //

But, Gate level (Structural representation) can be tedious!!!

50
 Conditional Operator
module mux2to1 (w0, w1, s, f); module mux2to1 (w0, w1, s, f);
input w0, w1, s;
input w0, w1, s;
output reg f;
output f;
always @(w0, w1, s)
assign f = s? w1 : w0; f = s? w1 : w0;

endmodule
endmodule

Conditional operator can be used both in continuous assignment statements

and procedural statements inside an always block

How do we write a Verilog code for 4x1 multiplexer using

conditional operator? 51
 4 x 1 multiplexer

module mux4to1 (w0, w1, w3, w4, S, f);

input w0, w1, w2, w3;
input [1:0] S;
output f;

assign f = S[1] ? (S[0]? w3 : w2) : (S[0] ? w1: w0);

endmodule

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 4 x 1 multiplexer using if-else
module mux4to1 (w0, w1, w3, w4, S, f);
input [3:0] W;
input [1:0] S;
output reg f;

always @(W, S)
if (S ==0)
f = W[0];
else if (S == 1)
f = W[1] ;
else if (S == 2)
f = W[2] ;
else
f = W[3] ;
endmodule
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 Case statement
module mux4 (S, W, f);
input [1:0] S;
input [3:0] W;
output reg [1:0] f;

always @(S or W)
begin
expression
case (S)
0: f = W[0];
alternatives
1: f = W[1];
2: f = W[2];
3: f = W[3];
endcase
end
endmodule
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 Case statement
module mux4 (S, W, f); module dec2to4(W, Y, En) ;
input [1:0] S; input [1:0] W;
input [3:0] W; input En;
output reg [1:0] f; output reg [0:3] Y;

always @(S or W)
always @(W, Y)
begin
case (S) case ({En, W})
0: f = W[0]; 3b100: Y = 4b1000;
1: f = W[1]; 3b101: Y = 4b0100;
2: f = W[2]; 3b110: Y = 4b0010;
3: f = W[3]; 3b111: Y = 4b0001;
default : f = x; default : Y = 4b0000;
endcase endcase
end endmodule
endmodule
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