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Write A Code For 7 - Segment Display Program

This document contains code for three different digital logic circuits: 1. A code for a 7-segment display that maps 4-bit binary coded decimal (BCD) values to the corresponding 7-segment display output. 2. A code for a 3-8 decoder with active low outputs that decodes a 3-bit input to activate one of 8 outputs. 3. A code for a positive edge triggered D flip-flop with synchronous reset and preset.

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eshwar_world
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42 views

Write A Code For 7 - Segment Display Program

This document contains code for three different digital logic circuits: 1. A code for a 7-segment display that maps 4-bit binary coded decimal (BCD) values to the corresponding 7-segment display output. 2. A code for a 3-8 decoder with active low outputs that decodes a 3-bit input to activate one of 8 outputs. 3. A code for a positive edge triggered D flip-flop with synchronous reset and preset.

Uploaded by

eshwar_world
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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01.

WRITE A CODE FOR 7 SEGMENT DISPLAY


Program:
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity test is
port ( clk : in std_logic;
bcd : in std_logic_vector(3 downto 0);
segment7 : out std_logic_vector(6 downto 0)
);
end test;
architecture segment of test is
begin
process (clk, bcd)
begin
if (clkevent and clk=1) then
case BCD is
when 0000 => segment7 <= 0000001;
when 0001 => segment7 <= 1001111;
when 0010 => segment7 <= 0010010;
when 0011 => segment7 <= 0000110;
when 0100 => segment7 <= 1001100;
when 0101 => segment7 <= 0100100;
when 0110 => segment7 <= 0100000;
when 0111 => segment7 <= 0001111;
when 1000 => segment7 <= 0000000;
when 1001 => segment7 <= 0000100;
when others => segment7 <= 1111111;
end CASE;
end if;
end process;
end segment;

02. 3 * 8 DECODER WITH ACTIVE LOW OUTPUTs


Program:
Library ieee;
Use ieee.std_logic_1164.all;
Entity DEC 3*8 is
Port (G1, G2A_L, G2B_L : in std_logic;
A : in std_logic_vector(2 downto 0);
Y_L : out std_logic_vector(7 downto 0)
);
End DEC 3*8;
Architecture Eshwar of DEC 3*8 is
Signal : y:std_logic_vector (7 downto 0);
Begin
With A select
Y <= 1111 1110 when 000;
1111 1101 when 001;
1111 1011 when 010;
1111 0111 when 011;
1111 1101 when 100;
1111 1101 when 101;
1111 1101 when 110;
1111 1101 when 111;
1111 1101 when others;
Y_l <= Y when (G1 and (not G2A_L) and (not G2B_L))= 1;
Else
1111 1111;
End Eshwar;

03. Positive edge triggered D - ?Flip flop with synchronous reset and preset?
Program:

04.

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