Extensible FPGA Framework (EFW)
For HiTech Global HTG-K800 Kintex-Ultrascale PCIe FPGA Module
Key Framework Features
QUICKEST AND HIGHLY AFFORDABLE 1G, 10G AND 40G
Integrated, hardware verified solutions
for 1G/10G/40G Ethernet development ETHERNET DEVELOPMENT WITH HTG-K800 PCIe MODULE
HTG-K800 module targeted system Extensible FPGA Framework (EFW) empowers FPGA developers with a
building blocks of DMA Controllers, verified set of productivity solutions, including module targeted
Ethernet MAC and PCS, PCIe application physical interface components, device drivers and APIs for the HiTech
interface, AXI4 Interconnect, DDR4 and Global HTG-K800 PCIe module.
Flash Memory controllers
Frameworks save months of development and debug time by enabling
Frameworks bundled with:
developers to skip the tedious and time consuming phase of IP core
o All options: x4/x8 PCIe Gen3 PCIe integration, interface verification and firmware development.
application interface, AXI4-Lite
master/arbiter for memory mapped Framework Type Required FMC
Framework Bundled Content
Base 1G 10G 40G Module
interface, Field Upgradeable (FUp)
Linux Device Drivers and APIs (Source) -
controller for in-system Flash x4/x8 PCIe Gen3 PCIe hard IP based PCIe -
programming and I2C controller application interface and arbiter (Verilog)
o Selected Option Based: Synthesizable AXI4-Lite Master and Arbiter with 32-bit -
binaries and full simulation libraries for control plane for registers accesses (Verilog)
32-bit AXI4-Lite Slave for integrating user -
high performance (up to 64Gbps) multi- blocks (Verilog)
channel DMA controllers paired with G18 Flash controller for in-system field -
GiGE, low latency 10G, ultra-low latency upgrades (FuP) (Netlist)
10G or 40G Ethernet I2C Controllers (Netlist) -
Targeted DDR4 controllers with AXI4 wrapper -
Linux source code device drivers and APIs (Verilog)
for PCIe interface and DMA controller 128-Bit 8-Channel PCIe RapidDMA with x4 -
Unified GUI for the entire EFW with Gen3 PCIe Endpoint (Netlist)
scripting support 256-Bit 8-Channel PCIe RapidDMA with x8 -
Gen3 PCIe Endpoint (Netlist)
Lowest startup cost for developing GiGE MAC with 1000Base-X Interface (Netlist) FMC-X4SFP+
complete 1G, 10G and 40G solutions with Low and Ultra-Low Latency 10G Ethernet, 32- FMC-X4SFP+
Kintex Ultrascale FPGA bit data path (Netlist) Latency optimized for FMC-SFP-OC
financial market applications
Simplified, single-sourced licensing for all 40G Ethernet, 128-bit data path (Netlist) FMC-X2QSFP+
FPGA IP cores and drivers Area optimized for low resource utilization FMC-SFP-OC
HTG-K800 EFW
Productivity Features
PCIe Bus Interface and Management: Complete PCIe solutions for the HTG-K800 x4 Gen3 and x8 Gen3 PCIe interface.
Framework implements up to two application side interfaces, a 32-bit AXI4-Lite compliant register access interface for
Non-DMA (single read/write) operations and 256/128-bit AXI-4 streaming compliant interface for DMA operations.
Parameterized AXI4-Lite Inter-connect: Complete, fully parameterized 32-bit AXI4-Lite inter-connect with Master,
Arbiter and Slave in source (Verilog) code for register access
High Performance PCIe DMA: 256-bit and 128-bit data path @ 250MHz (up to 64Gbps/32Gbps), multi-channel scatter-
gather RapidDMA IP with AXI4 compliant user interface for high performance and low latency data transfers between
host and module. Support for both Legacy and MSI interrupt mechanisms.
Ethernet Solutions from GiGE to 40Gbps: HTG-K800 targeted and fully verified Ethernet interfaces using GiGE, Optimal
Latency 10Gbps and 40Gbps Ethernet solutions. Ethernet interfaces provided through Hitech Global HTG-FMC-X4SFP+,
HTG-FMC-X2QSFP+ and HTG-FMC-SFP-OC FMC modules. Basic L2 packet generators and checkers (netlist) included for
quick interface verification through GUI interface.
BPI Flash Upgrade through PCIe: Program and erase the parallel Flash memory on the HTG-K800 through the PCIe
interface at very high speeds. Integrating the FUp controller allows any user design to be field upgradable through PCIe.
Device Drivers: 64-bit Linux device drivers in source code for DMA, register access and interrupts
APIs: C (source code) language function libraries and example test for DMA, register access and interrupts in source
code
GUI Interface: GUI application (Linux only) for control and configuration of all EFW components
Links to IP Core and Module Resources
40G Ethernet IP http://www.hitechglobal.com/IPCores/40Gig_EthernetMAC.htm
10G Low-Latency Ethernet IP: http://www.hitechglobal.com/IPCores/10GigEMAC.htm
DMA Controller IP:
For more information: Product Ordering Codes
Phone: +1-408-781-8043 Base (No Ethernet/DMA): HTK-EFW-K800-Base
Email:
[email protected] GiGe Ethernet: HTK-EFW-K800-1G
Low Latency 10G Ethernet: HTK-EFW-K800-10G
Ultra-Low Latency 10G: HTK-EFW-K800-10GU
40G Ethernet: HTK-EFW-K800-40G
