Floating & Fixed Point Arithmetic

Two Types of arithmetic

Floating Point Arithmetic

After each arithmetic operation numbers are normalized

Used where precision and dynamic range are important
Most algorithms are developed in FP
Ease of coding
More Cost (Area, Speed, Power)
Fixed Point Arithmetic
Place of decimal is fixed
Simpler HW, low power, less silicon
Converting FP simulation to Fixed-point simulation is time
consuming
Multiplication doubles the number of bits
NxN multiplier produces 2N bits
The code is less readable, need to worry about overflow
and scaling issues
Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 3
System-level Design Flow and Fixed-point Arithmetic
Algorithm
Requirements
exploration and
and
implementation in
Specifications
Floating Point

S/W or H/W
S/W H/W
Partition

Fixed Point
Conversion

Fixed Point
S/W or H/W RTL Verilog Functional
Implementation Co-verification Implementation Verifiction
S/W

Synthesis

Gate Level Net

List

Timing &
Functional
Verification

System
Layout
Integration

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 4
 System Design Flow
The requirements and specifications of the application are captured

The algorithms are then developed in double precision floating point format

Matlab or C/C++

A signal processing system general consists of hybrid target technologies

DSPs, FPGAs, ASICs

For mapping application developed in double precision is partitioned into

hardware & software

Most of signal processing applications are mapped on Fixed-point Digital

Signal Processors or HW in ASICs or FPGAs

The HW and SW components of the application are converted into

Fixed Point format for this mapping
Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 5
 Fixed-point v/s Floating-point Hardware

Algorithms are developed in floating point format

using tools like Matlab
Floating point processors and HW are expensive
Fixed-point processors and HW are used in
embedded systems
After algorithms are designed and tested then they
are converted into fixed-point implementation
The algorithms are ported on Fixed-point processor
or application specific hardware
Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 14
 Digital Signal Processors

Digital Signal
Processors

Floating Fixed Point

Point DSP DSP

Precision is critical. These DSPs Can be 16, 24 or 32-bit

are more expensive
C64x, C54X, C55x
C67x, C3X, C4X. Tiger Shark ADI 2100 series.
ADI 21000 series.
.

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 15
 2s Complement Arithmetic

Numbers

Signed Number Unsigned

Number

Positive Negative
Number Number

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 17
 2s Complement Arithmetic

MSB has negative weight,

Positive number aN-1 = 0

Negative number aN-1 = 1

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 18
 Example

1 0 1 1 (Negative number as MSB = 1)

23 22 21 20

-8 + 2 + 1 = -5

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 19
 Equivalent Representation
Many design tools do not display numbers as 2s complement signed numbers
A signed number is represented as an equivalent unsigned number
Equivalent unsigned value of an N-bit negative number is

2N - |a|

Example
for -5 = 1011

N=4
a=-5
24 - |-5| = 16 5= +11

In binary it is equivalent rep is 1011

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 20
Four-bit representation of twos complement and equivalent unsigned numbers

Decimal Twos complement representation Equivalent unsigned

number number

23 22 21 20

0 0 0 0 0 0

+1 0 0 0 1 1

+2 0 0 1 0 2

+3 0 0 1 1 3

+4 0 1 0 0 4

+5 0 1 0 1 5

+6 0 1 1 0 6

+7 0 1 1 1 7

8 1 0 0 0 8

7 1 0 0 1 9

6 1 0 1 0 10

5 1 0 1 1 11

4 1 1 0 0 12

3 1 1 0 1 13

2 1 1 1 0 14
Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 21
1 1 1 1 1 15
Computing Twos Complement of a Signed Number

Refers to the negative of a number

Computes by inverting all bits and adding 1 to the least
significant bit (LSB) of the number
This is equivalent to inverting all the bits while moving
from LSB to MSB and leaving the least significant 1 as it
is
From the hardware perspective, adding 1 requires an
adder in the HW and is an expensive preposition

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 22
 Scaling and sign extension

Scaling to Avoid Overflows

Overflow adds an error that equals to the
complete dynamic range of the number
To avoid overflow, numbers are scaled down
before mathematical operations
Sign Extension
Numbers may also need to be sign extended

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 23
 Sign Extension

An N bit number is extended to an M bit number M > N,

by replicating M-N sign bits to the most significant bit
positions
Positive number: M-N extended bits are filled with 0s

The number unsigned value remains the same

Negative number: M-N extended bits are filled with

1s,
Signed value remains the same
Equivalent unsigned value is changed

4b1000 2s complement sign number is sign extend

to 8b1111_1000

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 24
 Dropping Redundant Sign bits

When a number has redundant sign bits, these

redundant bits can be dropped
This dropping of bits does not affect the value of the
number
Example
8b1111_1000 = -8
Is same as
4b1000 = -8

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 25
 Floating Point Format

Floating point arithmetic is appropriate for high precision

applications
Applications that deals with number with wider dynamic range
A floating point number is represented as

x ( 1) s 1 m 2 e b

s represents sign of the number

m is a fraction number >1 and < 2
e is a biased exponent, always positive
The bias b is subtracted to get the actual exponent
Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 26
IEEE floating point format for single precision 32-
bit floating point number

s e m

sign 8 bit 23 bit

0 denotes + true exponent = e -127 mantissa
1 denotes -

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 27
 Example Floating Point Representation

32-bit IEEE Floating point number is

0_10000010_11010000_00000000_0000000

Sign bit Exponent Mantissa

0 10000010 11010000_00000000_0000000

(1)0 2(130-127) (1 . 1 1 0 1)2

1 2(3) (1 + 0.5 + .25 + 0 + 0.0625)10

(+1) 2(3) (1.8125)10

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 28
 Floating-point Arithmetic Addition

S0: Append the implied 1 of the mantissa

S1: Shift the mantissa from S0 with smaller exponent es to the right by
el es,
where el is the larger of the two exponents
S2: For negative operand take twos complement and then add the two
mantissas.
If the result is negative, again takes twos complement of the result
for storing in IEEE format
S3: Normalize the sum back to IEEE format by adjusting the mantissa

and appropriately changing the value of the exponent el

S4: Round or truncate the resultant mantissa to fit in IEEE format

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 29
 Example: Floating-point Addition

Add two floating point numbers in 10-bit precision

4 bits for exponent and 5 bits for the mantissa and 1 bit for the sign, bias
value is 7.
0_1010_00101
0_1001_00101
Taking the bias +7 off from the exponents and appending the implied 1, the
numbers are
1.00101b 23 and 1.00101b 22
S0: Align two exponents by shifting the mantissa of the number with smaller
exponent accordingly
1.00101b 23 => 1.001010b 23
1.00101b 22 => 0.100101b 23
S1: Add the mantissas
1.001010b + 0.100101b = 1.101111b
S2: Drop the guard bit 1.10111b 23
S3: The final answer is 1.10111b 23 which in 10-bit format of the operands is
0_1010_10111

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 30
 Floating-point Multiplication

S0: Add the two exponents e1 and e2 and subtract the bias
once

S1: Multiply the mantissas as unsigned numbers to get the

product, and XOR the two sign bits to get the sign of
the product

S2: Normalize the product if required

S3: Round or truncate the mantissa

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 31
Fixed-point format
Algorithms in double precision Floating-
point format are converted into Fixed-Point
format for mapping on low cost DSPs and
Application Specific HW designs

32
 Qn.m Format for Fixed-point Arithmetic

Qn.m format is a fixed positional number system

for representing floating-point numbers

A Qn.m format N-bit binary number assumes n bits

to the left and m bits to the right of the binary point

-21 20 . 2-1 2-2 2-3 2-4 2-5 2-6 2-7

Sign Bit
Fraction Bits
Integer Bit

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 33
 Qn.m Positive Number

The MSB is the sign bit

For a positive fixed-point number, MSB is 0
b 0bn 2 b1b0 .b 1b 2 b m

Equivalent floating point value of the positive

number is
b bn 2 2 n 2
b1 21 b0 b 12 1
b 22 2
b m 2 m

For Negative numbers, MSB has negative

weight and equivalent value is
b bn 1 2 n 1
bn 2 2 n 2
b1 21 b0 b 1 2 1
b 22 2
b m 2 m

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 34
 Conversion to Qn.m

1. Define the total number. of bits to represent a Qn.m number

(assume 10 bits)

2. Fix location of decimal based on the value of the number

-21 20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8
(assume 2 bits for the integer part)

The decimal point is implied

Fractional bits
Sign bit

Integer bit

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 35
 Example
-21 20 . 2-1 2-2 2-3 2-4 2-5 2-6 2-7

01 1101 0000 Sign Bit

Fraction Bits
Integer Bit
In Q2.8 format, the number is :

1 + 1/2 + 1/22 + 1/24 = 1.8125

Equivalent fixed-point integer value is

0x1D0

2 bits for the integer and remaining 8 bits keeps the

fraction part
A 10 bit Q2.8 signed number covers -2 to +1. 9922.
Increasing the fractional bits increases the precision.
Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 36
In Qn.m format,
n entirely depends upon the range of integer
m defines the precision of the fractional part

Q2.10

2 bits are reserved for 10 bits are reserved for the

the integer part fractional part

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 37
 Fixed-point numbers in COTS DSPs
Commercially available off the shelf processors usually
have16 bits to represent a number
In C, a programmer can define 8, 16 or 32 bit numbers as
char, short and int/long respectively
In case a variable requires different precision than what can
be defined in C, the number is defined in higher precision
For example an 18-bit number should be defined as a 32-bits
integer
High precision arithmetic is performed using low precision
arithmetic operations
32-bit addition requires two 16-bit addition
32-bit multiplication requires four 16-bit multiplications

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 38
 Floating Point to Fixed Point Conversion
Serialize the floating-point code to separate all atomic computations
and assignments to variables
Insert range directives after each serial floating-point computation
Runs the serialized implementation with range directives for all set
of possible inputs
Convert all floating point varilables to fixed point format using the
maximum and minimum values for each variable
The integer part for vari is defined as

ni log 2 (max max_ vali , min_ vali ) ) 1

The fractional part m requires detail analysis of Signal to
Quantization Noise analysis
Active area of research
Model based, exhaustive search based or optimization based
techniques
Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 39
 R&S

Floating-Point Algorithm

Range Estimation
Integer part determination

SQNR Analysis for Optimal fractional part

determination

Fixed-Point Algorithm

HW-SW Implementation

Target System
Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 40
 Range Determination for Qn.m Format

Run simulations for all set of inputs

Algorithms

Observe ranges of values for all variable

Ranges
Note Min and Max values each
variable takes for Qn.m format
determination
MIN MAX

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 41
 Floating-point to Fixed-point Conversion
Shift left m fractional bits to the integer part and truncate or round the
results
In Matlab, the conversion is done as

num_fixed = fix(num_float * 2m) or

num_fixed = round(num_float * 2m)

Saturate if number is greater than the maximum

positive number or less than the minimum negative
number.

if (num_fixed > 2N-1 1)

num_fixed = 2N-1 1
else if (num_fixed < -2N-1)
num_fixed = -2N-1
Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 42
Matlab Support for Fixed-Point Arithmetic

>> PI = fi(pi, 1, 3+5, 5);

>> bin(PI)
01100101
>> double(PI)
3.1563

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 43
 Matlab Supports Fixed Point Arithmetic
All the attributes of fixed point variable can be
set for fixed point arithmetic
These attributes are shown here
PI =
3.1563
DataType: Fixed
Scaling: Binary Point Data
Signed: true
WordLength: 8 Numeric Type

FractionLength: 5
RoundMode: round
OverflowMode: saturate
ProductMode: Full Precision Fixed-point math
MaxProductWordLength: 128
SumMode: Full Precision
MaxSumWordLength: 128
CastBeforeSum: true

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 44
 Arithmetic: Addition in Q Format
Addition of two fixed-point numbers a and b of Qn1.m1 and
Qn2.m2 formats, respectively, results in a Qn.m format
number, where n is the larger of n1 and n2 and m is the
larger of m1 and m2.

Example
implied decimal

Qn1.m1 1 1 1 1 1 0 = Q4.2 = -2+1+0.5 = -0.5

Qn2.m2 0 1 1 1 0 1 1 0 = Q4.4 = 1+2+4+025+0.125 = 7.375

Qn.m 0 1 1 0 1 1 1 0 = Q4.4 = 2+4+0.5+0.25+0.125 =6.875

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 48
 Multiplication in Q Format

Multiplications of two numbers in Qn1.m1 and Qn2.m2

formats generates product in
Q(n1 + n2).(m1 + m2) format
For signed x signed multiplication the MSB is a
redundant sign bit
First Drop this bit by shifting the result to the left
Then Drop less precision bits to bring the number
back to less number of bits

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 49
 Multiplication in Q-Format

Q n1.m1 X Q n2.m2 = Q (n1+n2) . (m1+m2)

Four types of Fractional Multiplication:

Unsigned Unsigned
Unsigned Signed
Signed Unsigned
Signed Signed Signed x Signed multiplication, results in a redundant sign bit

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 50
 Unsigned by Unsigned

The partial products are added without any sign extension

logic

1 1 0 1 = 11.01 in Q2.2 = 3.25

1 0 1 1 = 10.11 in Q2.2 = 2.75
1 1 0 1
1 1 0 1 X
0 0 0 0 X X
1 1 0 1 X X X
1 0 0 0 1 1 1 1= 1000.1111 in Q4.4 i.e.8.9375

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 51
 Signed by Unsigned

Sign extension of each partial product is necessary in

signed-unsigned multiplication.
The partial products are first sign-extended and then
added

1 1 0 1 = 11.01 in Q2.2 = -0.75

0 1 0 1 = 01.01 in Q2.2 = 1.25
1 1 1 1 1 1 0 1 extended sign bits shown in bold
0 0 0 0 0 0 0 X
1 1 1 1 0 1 X X
0 0 0 0 0 X X X
1 1 1 1 0 0 0 1 = 1111.0001 in Q4.4 i.e.-0.9375

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 52
 Unsigned by Signed
The unsigned multiplicand is changed to a signed positive
number

its 2s complement is computed if the signed number is

negative

The last product is a signed number

1 0 0 1 = 10.01 in Q2.2 = 2.25 (unsigned)

1 1 0 1 = 11.01 in Q2.2 = -0.75 (signed)
1 0 0 1
0 0 0 0 X
1 0 0 1 X X
1 0 1 1 1 X X X 2s compliment of the positive multiplicand 01001
1 1 1 0 0 1 0 1 = 1110.0101 in Q4.4 i.e.-1.6875

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 53
 Signed by Signed
Sign extend all partial products
Takes 2s complement of the last partial product if multiplier is a
negative number.
The MSB of the product is a redundant sign bit
Removed the bit by shifting the product to left, the product is in

Q( n1 + n2 1) . ( m1 + m2 + 1 )

1 1 0 = Q1.2 = -0.5 (signed)

0 1 0 = Q1.2 = 0.5 (signed)
0 0 0 0 0 0
1 1 1 1 0 X
0 0 0 0 X X
1 1 1 1 0 0 = Q1.5 format 1_11000=-0.25
Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 54
 Example: Signed x Signed

1 1. 0 1 = 0.75 in Q2.2 format

1. 1 0 1 = 0.375 in Q1.3 format
1 1 1 1 1 1 0 1
0 0 0 0 0 0 0 X
1 1 1 1 0 1 X X
0 0 0 1 1 X X X
0 0 0 0 1 0 0 1 = shifting left by one 00.010010 in Q2.6 format is 0.2815

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 55
 Corner Case:
Signed-Signed Fractional Multiplication

-1x-1 = -1 in Q fractional format is a corner case, it

should be checked and result should be saturated
as max positive number
1 0 0 = Q1.2 = -1

1 0 0 = Q1.2 = -1

0 0 0 0 0 0

0 0 0 0 0 X

0 1 0 0 X X 2s Compliment

0 1 0 0 0 0 Dropping redundant sign bit

results 1000000 = -1 in Q1.5

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 56
 Fixed Point Multiplication

Word32 L_mult(Word16 var1,Word16 var2)

{
Word32 L_var_out;

L_var_out = (Word32)var1 * (Word32)var2;

if (L_var_out != (Word32)0x40000000L) // 0x8000 x 0x8000 =
0x40000000
{
L_var_out *= 2; //remove the redundant bit
}
else
{
Overflow = 1;
L_var_out = 0x7fffffff; //if overflow then clamp to max +ve value

return(L_var_out);
}
Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 57
Fractional and Integer Arithmetic and truncation

4-bit Integer Arithmetic Q1.3 Fractional Arithmetic

1001 = -710 1.001 = -0.87510
0111 = +710 0.111 = 0.87510
11111001 11.111001
1111001X 11.11001X
111001XX 11.1001XX
11001111 = -4910 11.001111 = -0.76562510

11001111 1111 11.001111 Q1.3 format

-1(overflow) 1.001 = -0.87510

4x4 bit multiplication can easily trimmed to get in 4 bit precision for
fractional multiplication but for integer it may cause overflow

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 58
 Unified Multiplier

a b
The multiplier 0
a[15]
0
b[15]

supports integer
and fractional Signed/
Mux Mux
Signed/
multiplication Unsigned
Op1
Unsigned
1 16 Op2 1 16
All types of
operands 17 17
Unsigned 0

SxS, SxU, UxS, 17 * 17 Multiplier Signed 1

Integer 0
34 P Fractional 1
UxU
P[31:0] P[30:0],1'b0
Checks the corner Mux AND
Integer/Fractional
Signed/Unsigned Op1
case of fractional 32 Signed/Unsigned Op2

multiplication

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 59
 Bit Growth in Fixed-point Arithmetic

Bit growth is one of the most critical issues in fixed-point

arithmetic.

Multiplication of an N-bit number with an M-bit number

results in an (N+M)-bit number

In recursive system each iteration increases the width

y[n ]= ay[n-1]+x[n]

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 60
 Bit Growth in Q-format arithmetic

Multiplication of two N1 and N2 bit numbers in Qn1.m1 and Qn2.m2

results in N1+N2 bit number
Q(n1+n2-1).(m1+m2+1) for SxS and Q(n1+n2).(m1+m2) for the
rest
Where as addition results is
Qn.m= Q max(n1,n2).max(m1.m2)

For LTI system Schwarzs inequality is used for estimating the bit
growth

yn h2 n x2 n
n n

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 61
 Truncation
In multiplication of two Q format numbers as the number
of bits in the product increases
We sacrifice precision by throwing some low precision
bits of the product
Qn1.m1 is truncated to Qn1.m2 where m2 < m1

Let the product is

8b01110110 (Q4.4)
4 + 2 + 1 + 0.25 + 0.125 = 7.375
Truncate it to Q4.2 results
6b011101 = 7.25
Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 62
 Rounding with Truncation

Sometimes we truncate with rounding

Example
3.726 can be rounded off to 3.73
We do similar things in Digital Design that is First Round off then
Truncate
Before rounding add 1 to the right side of the truncation point and
then truncate

truncation point
0 1 1 1_0 1 1 1 in Q4.4 is 7.4375
1
add 1 for rounding
0 1 1 1_1 0 0 1
0 1 1 1_1 0 = 7.5 Q4.2 format

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 63
 Equivalent Q formats
In many cases Q format of a number is to be
changed

Convert Qn1.m1 to Qn2.m2

If n2>n1, we simply append sign bits=n2-n1

to the MSB location of n1
If m2>m1 we simply append zeros to the
LSB locations of the Fractional part of m1

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 64
 Example

Let a=11.101 ( Q2.3 )

is supposed to be added to a number b of Q7.7 format.
So extending a will result in:
1111111.1010000 ( Q7.7 )

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 65
Overflow introduces an error equal to the dynamic range of
the number
Q(x)

overflow
overflow 3 011

2 010

1 001
000 x

-4 -3 -2 -1 1 2 3 4 5 6 7

111 111
-1
110 110
-2
101 101
-3
100 100

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 66
Saturation clamps the value to a maximum positive or
minimum negative level
Q(x)

011
3
2 010
saturation
1 001
000 x

-4 -3 -2 -1 1 2 3

111
-1
110
-2
101
-3
100
saturation
Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 67
 Summary
Capturing Requirements & Specifications is the first step in system design
A digital system usually consists of hybrid technologies and uses GPP,
DSPs, FPGAs and ASICs
The algorithms are developed in double precision floating point format
Floating point HW and DSPs are expensive, for DSP applications Fixed
point arithmetic is preferred
The floating point code is converted to fixed point format and all variables
are defined as Qn.m format numbers
The fixed point arithmetic results in bit growth, the results from arithmetic
computations are rounded and truncated
In IIR filter implementation 2nd order and Parallel forms minimizes
coefficient quantization
Implementation of LP FIR should use symmetry and anti-symmetry of
coefficients
Block floating point can improve the precision for block processing of data

Digital Design of Signal Processing Systems, John Wiley & Sons by Dr. Shoab A. Khan 88