2017 4th International Conference on Signal Processing, Communications and Networking (ICSCN -2017), March 16 – 18, 2017, Chennai,

INDIA

DESIGN AND IMPLEMENTATION OF PAL AND

PLA USING REVERSIBLE LOGIC ON FPGA
SPARTAN 3E
Gopi Chand Naguboina, Mtech Student K.Anusudha, Assistant Professor
Dept. of Electronics Engineering Dept. of Electronics Engineering
Pondicherry University Pondicherry University
Pondicherry, India Pondicherry, India
[email protected] [email protected]

Abstract—Reversible logic is the emerging field for research circuits. Reversible Logic finds its own application in
in present era. The aim of this paper is to design and synthesize Quantum computing, Nano- technology, Optical computing,
a Programmable array Logic (PAL) and Programmable Logic Computer graphics and Low Power VLSI. Ralf Launduer
array (PLA) using reversible logic with minimum quantum [1] told that heat dissipation in irreversible circuits is not
cost. The PAL is a Programmable Logic device which consists because of the process involved in the operation, but it is
of programmable AND Gates and fixed OR gates array. The
due to the bits that were erased during the logical
PLA is the PLD which contains programmable AND array and
programmable OR array. The PLDs are the combinational computation process. He demonstrated Launder’s principle
circuits mainly used to realize Boolean functions on our which describes the lower theoretical limit of heat
interest. An n input and k output Boolean function f (a1, a2, dissipation in logical computation. Launder’s principle
a3, …., an) (referred as (n, k)) is said to be logically reversible states that losing a single information bit in the circuit
if and only if, the number of inputs are equal to the number of causes the smallest amount of heat in the computation which
outputs i.e., ‘n’ equals ‘k’ and the input pattern maps uniquely is equal to KTln2 joules where K is Boltzmann constant
maps the output pattern. The reversible logic must run both (approximately 1.38×10-23 J/K), T is Temperature and ln2 is
forward and backward in such a way that the inputs can also natural algorithm of 2 (approximately 0.69315). The amount
be retrieved from outputs. There are many reversible logic
of heat dissipated in simple circuits is very small but it
gates in literature like NOT gate, Feynman Gate (CNOT gate),
Double Feynman Gate, Peres Gate, TR gate, Seynman Gate becomes large in the complex circuits. It is necessary to
and many more. Fan-out and Feed-back are not allowed in notice that there is a direct relationship between the number
Logical Reversibility. To overcome the Fan out limitation, the of information bits erased to the amount of heat dissipated
signals from required output lines are duplicated to desired in the circuit. Later in 1973 C. H. Bennett [2] described that
lines using additional reversible combinational circuits. the Power dissipation due to the bit loss can be overcome if
Reversible Logic owns its applications in various fields which each and every computation in circuit was carried out in
include Quantum Computing, Optical Computing, Nano- reversible manner. Quantum networks are designed of
technology, Computer Graphics, low power VLSI etc., quantum logic gates. As each gate perform a unitary
Reversible logic is gaining its own importance in recent years
operation, KTln2 Joules energy dissipation wouldn’t occur
largely due to its property of low power consumption and low
heat dissipation. In this paper, the design of PAL and PLA if the computation is carried out in reversible manner. He
which has less heat dissipation and low power consumption is argued that for zero heat dissipation, the computation must
proposed. The designed circuits are analyzed in terms of be done in reversible manner. But if reversible logic is
quantum cost, garbage outputs and number of gates. The utilized to do logical computation, the heat dissipation will
Circuit has been designed and simulated using Xilinx software be less than KTln2 for one information bit in contrast to
and implemented on FPGA SPARTAN – 3E. Launder. Thus computation done in reversible manner
doesn’t require erasing of bits.
KEYWORDS: PAL, PLA, PLDS, Quantum Cost, Reversible Gates,
Garbage Outputs, Number of gates.
II.CONCEPT

I.INTRODUCTION The Reversible Logic involves the use of Reversible

Gates which consists of the same number of inputs and
In present VLSI Technology, Power Consumption has outputs i.e., there should be one to one mapping between
become a very important factor for consideration. By using input vector lines and output vector lines. In reversible
Reversible logic, power consumption and heat dissipation computation [2], the reversible gates are made to run both
can be minimized. Power consumption is very less in forward and backward directions. If the device obeys above
reversible logic circuits when compared to irreversible logic two conditions, it satisfies the second law of

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2017 4th International Conference on Signal Processing, Communications and Networking (ICSCN -2017), March 16 – 18, 2017, Chennai, INDIA

thermodynamics which preserves the information bits 1. NOT GATE: The NOT GATE is the simple Reversible
without getting erased and guarantees that no heat is Logic gate. It is 1×1 Reversible Logic Gate with the quantum
dissipated. Certain limitations are to be considered when cost zero. The Not gate simply shifts the complementary of the
designing circuits based on reversible logic (i) Fan out is not input to output as shown in the figure2. It is the basic primitive
permitted in reversible logic and (ii) Feedback is also not gate which may involve in construction of reversible logic
permitted in reversible logic. In Reversible logic using gate, thus owing its own importance in determining the
outputs we can obtain full knowledge of inputs. To quantum cost of designed Reversible logic gate.
overcome the Fan-out limitation, by using additional
reversible combinational circuits, the output lines are
duplicated into required number of lines that are required to
drive the inputs of consecutive device. Similarly for Feed-
back limitation delay elements are used. Reversible logic Fig. 2 NOT Gate and its Truth Table
conserves information. 2. FEYNMAN GATE (FG): Feynman gate [4] is a 2×2
Some cost metrics [5][4] like Garbage outputs, Number reversible gate as shown in below figure3. The Feynman gate
of gates, Quantum cost, constant inputs are used to estimate is also called as CNOT gate i.e., controlled NOT gate. The
the performance of reversible circuits. Garbage outputs are Feynman gate is used to duplicate of the required outputs since
the extra outputs which help to make inputs and outputs Fan-out is not allowed in reversible logic gates. The Quantum
equal in order to maintain reversibility. They are kept alone Cost of FG is 1. This is also the primitive gate owing its
without performing any operations. Number of gates count importance in determining quantum cost metric.
is not a good metric since more number of gates can be
taken together to form a new gate. Quantum Cost is the
number of elementary or primitive gates needed to
implement a reversible logic gate. It is nothing but the
number of reversible gates (1×1 or 2×2) required to
construct the circuit. The quantum cost plays an important
role in logical reversibility. If the quantum cost is more, Fig. 3 Feynman Gate and its Truth Table
then the area of the circuit increases, thereby increasing the 3. DOUBLE FEYNMAN GATE (F2G): Double Feynman Gate
propagation delay. But quantum cost doesn’t impact heat [4] is a 3×3 reversible gate. The outputs P, Q, R are defined as
dissipation. Delay is one of the important cost metrics. A the functions of inputs as shown in the figure4. The quantum
Reversible circuit design can be modeled as a sequence of cost of F2G is 2. This gate can also be used for duplicating
discrete time slices and depth is summation of total time outputs.
slices. In Digital Electronics the binary decoder is a
combinational logic circuit that converts the binary integer
value to the associated output pattern. Various proposals are
given to design of combinational and sequential circuits in
the undergoing research.
In this paper the design of Programmable Array Logic
(PAL) and Programmable Logic array (PLA) using
reversible logic with minimum Quantum cost is proposed
and these circuits are implemented on FPGA SPARTAN – Fig.4 Double Feynman Gate and its Truth Table
3E. 4. TOFFOLI GATE (TG): Toffoli Gate [8] is 3×3 reversible
gate. The outputs P, Q, R are defined as the functions of inputs
III. REVERSIBLE LOGIC GATES as shown in the below figure5. The Quantum Cost of TG is 4.
The reversible logic gate consists of same number of
inputs and outputs as shown in the figure1. The basic
Reversible Logic Gates present in the literature are briefed
below. The gates that are suitable for the design with optimum
quantum cost can be selected.

Fig.5 Toffoli Gate and its Truth Table

5. FREDKIN GATE (FRG): Fredkin Gate [12] is a 3×3

reversible gate. The outputs P, Q, R are defined as functions of
inputs as shown in the below figure6. The Quantum Cost of
FRG is 5. This paper mainly surrounds around Fredkin gate.

Fig.1 Simple reversible logic gate

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2017 4th International Conference on Signal Processing, Communications and Networking (ICSCN -2017), March 16 – 18, 2017, Chennai, INDIA

Cost when compared to the other reversible Logic gates. The

number of gates required to design 4x16 decoder are 18 in
which there are 12 fredkin gates, one peres gate, one TR gate,
one NOT gate and 3 CNOT gates. The sum of all the quantum
costs of each gate gives total quantum cost of 4x16 decoder.
The sum of all the quantum costs of each gate used to design
total circuit gives the quantum cost of total circuit.
Fig.6 Fredkin Gate and its Truth Table
VI.PROPOSED METHOD
6. PERES GATE (PG): Peres Gate [5] is a 3×3 reversible gate.
The Programmable Array Logic (PAL), Programmable
The outputs P, Q, R are defined as functions of inputs as shown
Logic array (PLA) is realized using reversible Fredkin gate and
in the below figure7. The Quantum Cost of PG is 4.
Feynman gate as shown in the figure11 and figure12
respectively. The concept of duplicating a single output to
required number of outputs using Feynman gate is introduced
where Fan-out was not allowed in reversible computation. The
standard irreversible conventional PLDs can be programmed
only once. The irreversible PLDs consist of a series of fuses
which can be burned to program the device. By burning the
fuses the chip can be programmed which is an irreversible
Fig.7 Peres Gate and its Truth Table
process.

7. TR GATE: TR Gate [5] is a 3×3 reversible gate. The outputs In reversible PLDs structure, the fuses are replaced with a
P, Q, R are defined as functions of inputs as shown in the reversible fuse which is made of reversible Feynman gate and
below figure8. The quantum cost of TRG gate is given by 4. fredkin gate as shown in the below figure10 (a). The Feynman
reversible gate acts as a duplicating circuit. It duplicates the
output line into two output lines out of which one output line
drives the next circuit and the other drives the second input of
2×1 reversible multiplexer. The first input of reversible
multiplexer is grounded so that when the enable signal ‘E’ is
low it acts as an ‘off’ switch. The reversible multiplexer is
made of Fredkin gate as shown in the below figure10 (b).

Fig.8 TR Gate and its Truth Table

IV. BASIC GATES USING REVERSIBLE GATES

Considering our circuit requirements we need to design
AND gate and OR gate using reversible gates. Here fredkin
gate is used to design AND and OR gates as shown in figure9. Fig.10 (a) Reversible Fuse Fig.10 (b) Reversible MUX
Importance is given to fredkin gate because it gives optimistic
performance at less Quantum Cost for designing AND and OR The fixed connections are replaced by CNOT gates in
gates. which the second input is set to ‘0’ always. The CNOT gates
give solution for two remedies. It overcomes the feedback
limitation and it acts as a fixed connection. The Design of
PAL made of reversible logic which is programmed to perform
the operation of the below Boolean algebraic equations is
shown in the below figure11. The PAL consists of fixed OR
gates array and programmable AND gate array.
Fig.9 AND Gate using fredkin and OR Gate using fredkin
F1 = I[1]I[2] + I[1]I[3]’ + I[1]’I[2]’I[3] ……………… Eqn (1)
V.EXISTING METHOD
F2 = I[1]I[2] + I[1]’I[2]’I[3] + I[1]I[3] ………………..Eqn (2)
The Design of Combinational circuits [6][9][16] and
Sequential Circuits [10][11] using reversible logic has been F3 = I[1]I[3]’ + I[1]I[2]I[3] ………………………… Eqn (3)
ongoing in research. Various proposals are given for the design Contemporary to irreversible PAL, the fuses are replaced
of combinational circuits like adders, subtractors, multiplexers, with programmable reversible fuses and the fixed connections
decoders etc., in the existing method the author has given a are replaced with the CNOT gates as shown in the figure11.
novel design of 4x16 decoder [15] whose Quantum Cost is less The ‘P’ output of fuse drives the subsequent fuse and the ‘Q’
than the previous design. Replacing fredkin gates for designing output of fuse drives the input of AND gate as shown in
2×4 decoder with reversible gates like Peres gate, TR gate, figure13. The output of AND gate drives the fixed connections
NOT gate and CNOT gate are used. The whole design is done i.e., CNOT gate. The ‘P’ output of CNOT gate drives the next
using Fredkin, CNOT, Peres gates which give better Quantum

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2017 4th International Conference on Signal Processing, Communications and Networking (ICSCN -2017), March 16 – 18, 2017, Chennai, INDIA

fixed connection and the ‘Q’ output of CNOT drives the input impedance value is not driven to OR gate which effects the
of OR gate. operation of OR gate. The fuses left without programming
drives the value zero to the reversible OR gate which doesn’t
affect the operation of OR gate. Contrast to OR gate, for AND
gate the left out inputs are driven with HIGH signal so that the
operation of AND gate is not affected.
The circuit diagram of a Programmable Logic Array
constructed using reversible logic to program Boolean
equations Eqn (1), Eqn (2), Eqn (3) is shown in the above
figure12. In PLA both the AND gate array and OR gate arrays
are programmable. Hence reversible fuses are used to program
the AND gate array and OR gate array of the device as shown
in the figure12.
Similarly the circuit diagram of a Generic Array Logic
constructed using reversible logic to program Boolean
equations Eqn(1), Eqn(2), Eqn(3) is shown in the below
figure13. In GAL the outputs are also programmable along
with the AND gate array and OR gate array. Hence it differs
from PLA. Therefore reversible fuses are used to program the
device as shown in the figure13.

Fig.11 Circuit diagram of Reversible PAL to perform Boolean algebraic

equations operation.

Fig.13 Circuit diagram of Reversible GAL to perform Boolean Algebraic

equations operation.

VII. SIMULATION RESULTS OF PROPOSED CIRCUITS

Fig.12 Circuit diagram of Reversible 3-5-3 PLA to perform Boolean

Algebraic equations operation.
1. REVESIBLE PROGRAMMABLE ARRAY LOGIC

The OR Gates and AND gates used in PLDs are made of The equations Eqn 1 to Eqn 3 are implemented using
Reversible logic. The ‘n’ input OR gate consists of ‘n’ number reversible PAL. The RTL schematic and simulated output for
of inputs. If any inputs are kept ideal without use they are to be Eqn1 to Eqn3 implemented using reversible PLA is shown in
driven with ground (binary value ‘0’) so that the high the figure14 and figure17 respectively.

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2017 4th International Conference on Signal Processing, Communications and Networking (ICSCN -2017), March 16 – 18, 2017, Chennai, INDIA

4. REVERSIBLE GENERIC ARRAY LOGIC

The equations Eqn 1 to Eqn 3 are implemented using

reversible GAL. The RTL schematic and simulated output for
Eqn1 to Eqn3 implemented using GAL is shown in the
figure16 and figure17 respectively.

Fig.14 RTL Schematic of PAL implementing Boolean algebraic equations

Eqn (1) to Eqn (3)

3. REVERSIBLE PROGRAMMABLE LOGIC ARRAY

The equations Eqn 1 to Eqn 3 are implemented using

reversible PLA. The RTL schematic and simulated output for
Eqn1 to Eqn3 implemented using reversible PLA is shown in
the figure15 and figure17 respectively.

Fig.16 RTL schematic of reversible GAL implementing Boolean algebraic

equations Eqn(1) to Eqn(2)

Fig.17 Simulated outputs for implementing Boolean algebraic equations

Eqn(1) to Eqn(2) using PAL, PLA and GAL

The simulated output will be same for all the three devices,
which gives clear assistance that the circuits are operating with
genuine performance.
Fig 15 RTL Schematic of PLA implementing Boolean algebraic equations
Eqn(1) to Eqn(3)

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2017 4th International Conference on Signal Processing, Communications and Networking (ICSCN -2017), March 16 – 18, 2017, Chennai, INDIA

VIII. ANALYSIS the number of programmable reversible fuses and Feynman

The Reversible circuit elements used in designing PLDs gates (fixed connectors) increases with increase in length of
are analyzed in terms of Quantum cost and Garbage outputs. Boolean function. If quantum cost increases, the time delay
also increases. The reversible PAL, GAL finds more
CIRCUIT
QUANTUM GARBAGE advantages when compared to the reversible PAL and PROM,
COST OUTPUTS since both OR array and AND array are programmable.
FEYNMAN_GATE 1 0 Because of using reversible decoder in PROM the quantum
FREDKIN_GATE 5 1 cost becomes less when compared to the remaining PLDs. The
AND GATE 5 2
propagation delay can be reduced if the quantum cost of the
circuit is reduced further more. This can be termed as future
OR GATE 5 2 scope for this paper.
FUSE 6 2
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