EE-231 Electronics I

Engr. Dr. Hadeed Ahmed Sher

Ghulam Ishaq Khan Institute of Engineering Sciences and Technology, TOPI 23460
[email protected]

April 9, 2018

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 11 Resources April 9, 2018 1 / 31
 1 Bias Stabilization
Determination of S(ICo )
Determination of S(VBE )
Determination of S(β)

2 BJT AC analysis

3 The re transistor model

Common Emitter configuration
Common base configuration
Common collector configuration

4 Use of re model in transistor circuits

Common emitter fixed bias configuration
Common emitter voltage divider configuration
Common base configuration

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 11 Resources April 9, 2018 2 / 31
 Bias Stabilization

Stability of a system is measure of a network to variations in its

parameters.
IN BJT circuits the collector current is sensitive to
β— It increases with rise in temperature
VBE — It decreases 2.5mV per degree Celsius rise
ICO —This reverse saturation current doubles every 10 degree Celsius
rise

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 11 Resources April 9, 2018 3 / 31
 Bias Stabilization

Below is the variations of a typical BJT at various temperatures.

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 11 Resources April 9, 2018 4 / 31
 Bias Stabilization

Stabilization factor (S) for each parameter explained in slide 3 is given as.

S(ICO )
∆IC
S(ICO ) = (1)
∆ICo

S(VBE )
∆IC
S(VBE ) = (2)
∆VBE

S(β)
∆IC
S(β) = (3)
∆β

Lower the value of S, more is the stability.

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 11 Resources April 9, 2018 5 / 31
 Bias Stabilization Determination of S(ICo )

Determination of S(ICo )
β+1
S= dIB
(8)
The derivation of expression for 1 − β( dI C
)
S(ICo ) requires calculus. To solve for the unknown ( dIdIB
),
C
Starting the procedure, consider the circuit below which is
actually a voltage divider biasing
IC = ICm ajority + ICm inority (4)
circuit with thevenin equivalent in
IC = βIB + (1 + β)ICO (5) place.
Derivating it w.r.t. IC .
dIB dICO
1=β + (1 + β) (6)
dIC dIC

dIB (1 + β)
1=β + (7)
dIC S

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 11 Resources April 9, 2018 6 / 31
 Bias Stabilization Determination of S(ICo )

Determination of S(ICo )
Applying the KVL on the input loop yields

Vth = IB Rth − VBE − IE RE (9)

Vth = IB Rth − VBE − (IB + IC )RE (10)

Differentiating wrt IC .
dIB dIB
0 = Rth + (1 + )RE (11)
dIC dIC
dIB −RE
= (12)
dIC Rth + RE
Inserting (12) into (8)
Rth
1+ RE
SICO = (β + 1) Rth
(13)
(β + 1) + RE

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 11 Resources April 9, 2018 7 / 31
 Bias Stabilization Determination of S(ICo )

Determination of S(ICo )
RB
From (15) if the RE >>β then the expression can be simplified as
SICO ≈ β (14)
RB
For RE <<1 the expression is
SICO ≈ 1 (15)

Stability is improved if RE is large.

However, the good designs have RB
larger than RE . This requires a
tradeoff between the two.

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 11 Resources April 9, 2018 8 / 31
 Bias Stabilization Determination of S(ICo )

Determination of S(ICo )
For other configurations the SICO can be calculated as
Fixed biased configuration

SICO ≈ β (16)

Emitter biased configuration

RB
1+ RE
SICO ≈ (β + 1) RB
(17)
(β + 1) + RE

Feedback bias configuration

RB
1+ RE
SICO ≈ (β + 1) RB
(18)
(β + 1) + RE

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 11 Resources April 9, 2018 9 / 31
 Bias Stabilization Determination of S(ICo )

Example 4.35
Calculate the stability factor and
the change in IC from 25◦ C to
100◦ C for the transistor defined
by Fig.4 for the following
emitter-bias arrangements:.
The change in IC is given in (1), and the
RB
RE = 250 change is ICO is calculated using Fig.4
RB
RE = 10 ∆IC = (41.83)(19.9nA) = 0.83µA (20)
RB
RE = 0.01
Similarly the value of SICO for the other
Using the expression in (17) for two cases can be calculated
the first arrangement

50(1 + 250
SICO = = 41.38
50 + 250
(19)
Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 11 Resources April 9, 2018 10 / 31
 Bias Stabilization Determination of S(VBE )

Determination of S(VBE )

Fixed biased configuration

−β
SVBE ≈ (21)
RB

Emitter biased configuration

−β
RE
SVBE ≈ (22)
β + RRBE

Voltage divider configuration

−β
RE
SVBE ≈ (23)
β + RRthE

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 11 Resources April 9, 2018 11 / 31
 Bias Stabilization Determination of S(VBE )

Determination of S(VBE )

Feedback bias configuration

−β
RC
SVBE = RB
(24)
β +R C

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 11 Resources April 9, 2018 12 / 31
 Bias Stabilization Determination of S(β)

Determination of S(β)

Fixed biased configuration

IC1
S(β) = (25)
β1

Emitter biased configuration

∆IC IC1 (1 + RRBE )

S(β) = = (26)
∆β β1 (β2 + RRBE )

Voltage divider configuration

∆IC IC1 (1 + RRthE )

S(β) = = (27)
∆β β1 (β2 + RRthE )

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 11 Resources April 9, 2018 13 / 31
 Bias Stabilization Determination of S(β)

Determination of S(β)

Feedback bias configuration

IC1 (RB + RC )
S(β) = (28)
β1 (RB + β2 RC

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 11 Resources April 9, 2018 14 / 31
 BJT AC analysis

BJT AC analysis

Small signal modeling of BJT is the focus.

It is assumed that the currents and the voltages have the polarities as
shown below.

The AC analysis follows a simple procedure. Kill all the DC sources,

replacing capacitors with a short circuit and redrawing the circuit.

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 11 Resources April 9, 2018 15 / 31
 BJT AC analysis

BJT AC analysis

Killing the DC sources (grounding) and replacing the capacitors with a

short circuit.

Figure: Circuit under examination Figure: Simplified circuit for AC analysis

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 11 Resources April 9, 2018 16 / 31
 BJT AC analysis

BJT AC analysis

The circuit can be rearranged as shown below.

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 11 Resources April 9, 2018 17 / 31
 The re transistor model Common Emitter configuration

Common Emitter configuration

For a common emitter configuration the input is applied on the BE

junction and the output is taken across the CE junction.
Recall that a forward biased junction in a BJT can be replaced with a
diode and the collector current can be expressed as a controlled current
source as shown below.

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 11 Resources April 9, 2018 18 / 31
 The re transistor model Common Emitter configuration

Common Emitter configuration

The diode can be expressed as a resistance re which is the resistance

offered by the diode in forward biased condition.

Where,
VT 26mV
re = = (29)
ID IE
The controlled current source represents the collector current.

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 11 Resources April 9, 2018 19 / 31
 The re transistor model Common Emitter configuration

Common Emitter configuration

The resistance re can be reflected to the input side. Let Zi be the
impedance seen by the input side.
Vi Vbe
Zi = = (30)
Ib Ib
Vbe = Ie re = (Ic + Ib )re = (βIb + Ib )re = (β + 1)Ib re (31)
Vbe ((β + 1)Ib re
Zi = = = (β + 1)re ≈ βre (32)
Ib Ib
The equivalent circuit then looks like

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 11 Resources April 9, 2018 20 / 31
 The re transistor model Common Emitter configuration

Common Emitter configuration

The impedance seen by the load resistance can be calculated using the
output characteristics of common emitter amplifier.
The inverse of the slope provides the output resistance ro . Note that the
slope of all the lines if extended touch the x axis at a single point. It is
called Early Voltage (VA ). Early voltage is lager than the VCE therefore,
(VA ) can also be used to calculate the ro .

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 11 Resources April 9, 2018 21 / 31
 The re transistor model Common Emitter configuration

Common Emitter configuration

After incorporating the output resistance the circuit can be modeled as

shown below.

Typically β is between 50-200. The βre is usually between 6k to 7k ohm.

The typical value of output resistance is in the range of 40k to 50k ohm.

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 11 Resources April 9, 2018 22 / 31
 The re transistor model Common base configuration

Common base (CB) configuration

The model of the CB configuration is based on the same steps as CE

configuration. The difference however is on two aspects. First, because
the emitter is input therefore its resistance is not reflected to base.
Secondly, the input current (Ie ) and output current (Ic ) is related by α.
The output characteristics of CB reveal that the ro is very high. There is
no phase shift in CB configuration.

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 11 Resources April 9, 2018 23 / 31
 The re transistor model Common collector configuration

Common collector (CC) configuration

For CC configuration, normally the model defined for CE is used.

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 11 Resources April 9, 2018 24 / 31
 Use of re model in transistor circuits Common emitter fixed bias configuration

Common emitter fixed bias configuration

The CE fixed bias configuration is first arranged for the AC analysis as

shown below.

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 11 Resources April 9, 2018 25 / 31
 Use of re model in transistor circuits Common emitter fixed bias configuration

Common emitter fixed bias configuration

Inserting the re model of transistor.

Here the value of re is obtained from DC analysis. β and ro values are

typically give in the datasheet.

Zi = RB ||βre ≈ βre (33)

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 11 Resources April 9, 2018 26 / 31
 Use of re model in transistor circuits Common emitter fixed bias configuration

Common emitter fixed bias configuration

The output impedance Zo is given as.

Zo = RC ||ro ≈ RC (34)
The gain Av is given as

Vo −βIb (RC ||ro )

Av = = (35)
Vi Vi
Vi Vi
Ib = =⇒ Vo = −β( )(Rc ||ro ) (36)
βre βre
(35) is then equal to

Vo −(RC ||ro ) −Rc

Av = = ≈ (37)
Vi re re

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 11 Resources April 9, 2018 27 / 31
 Use of re model in transistor circuits Common emitter fixed bias configuration

Common emitter fixed bias configuration

The negative sign represents a phase shift of 180◦ .

Example 5.1 provides procedure to mathematically treat a given problem.

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 11 Resources April 9, 2018 28 / 31
 Use of re model in transistor circuits Common emitter voltage divider configuration

Common emitter voltage divider configuration

The CE voltage divider bias configuration is arranged for the AC analysis
as shown below.

R1 R2
R 0 = R1 ||R2 = (38)
R1 + R2
Zi = R 0 ||βre (39)

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 11 Resources April 9, 2018 29 / 31
 Use of re model in transistor circuits Common emitter voltage divider configuration

Common emitter voltage divider configuration

The output impedance Zo is given as

Zo = RC ||ro ≈ RC (40)

The voltage gain Av is given as

Vo −Rc ||ro −RC

Av = = ≈ (41)
Vi re re
This shows that the gain is independent of the biasing configuration.

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 11 Resources April 9, 2018 30 / 31
 Use of re model in transistor circuits Common base configuration

Example 5.2
In order to solve for the circuit first
For the network shown find a)re b)Zi
determine if βRE >>10R2 . Because
c)Zo (ro = ∞Ω) and d)Av (ro = ∞Ω)
this condition is true therefore,
VCC R2
VB = = 2.81V (42)
R1 + R2
VE = VB −VBE = 2.81−0.7 = 2.11V
(43)
VE
IE = = 1.41mA (44)
RE
26mV
re = = 18.44Ω (45)
IE
Using (39) and (40) the Zi =1.35kΩ
and Zo =6.8kΩ. Gain Av is
calculated as -386.76 using (41).
Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 11 Resources April 9, 2018 31 / 31