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/ 53
\ y Programming, Interfacing,
~
~atoe Applications
Walter A. Triebel | Avtar Singh
Software, Hardware and
N of this edition outside of these terrtories is UNAUTH Authorized adaptation from the United States edition, entitled The 8088 and 8086
Microprocessors: Programming, Interfacing, Software, Hardware, and Applications, 4th
Edition, ISBN: 9780130930811 by Triebel, Walter A., published by Pearson Education Ltd,
Copyright © 2002
Indian Subcontinent Adaptation
Copyright © 2007 Dorling Kindersley (India) Pvt. Ltd.
This book is sold subject to the condition that it shall not, by way of trade or otherwise, be
lent, resold, hired out or otherwise circulated without the publisher's prior written consent in
any form of binding or cover other than that in which it is published without a similar
condition including this condition being imposed on subsequent purchaser and without
limiting the rights under copyright reserved above, no part of this publication may be
reproduced, stored in or introduced into a retrieval system, or transmitted in any form or by
any means (electronic, mechanical, photocopying, recording or otherwise), without the prior
written permission of both the copyright owner and above-mentioned publisher of this book.
ISBN978- 81-7758-481-3
First Impression, 2007
Second Impression, 2008
Third Impression, 2009
This edition is manufactured in India and is authorized for sale only in India,
Bangladesh, Bhutan, Pakistan, Nepal, Sri Lanka and the Maldives.
Published by Dorling Kindersley (India) Pvt. Ltd., licensees of Pearson Education in
‘South Asia.
Head Office: 482 F.LE., Patparganj, Delhi 110 092, India,
Registered Office: 14 Local Shopping Centre, Panchsheel Park, New Delhi 110 017, India.
Printed in India at Swan Press. Contents
AND MICROCOMPUTERS _1
L1_General Architecture of a Microcomputer System, 2
1.2 Evolution of the Intel Microprocessor Architecture, 4
“Microprocessor Performance: MIPS and iCOMP. 6
Transistor Density, 6
Reprogrammable and Embedded Microprocessors, 7
MICROPROCESSORS 13,
2.1 Microarchitecture of the 8088/8086 Microprocessor, 14
2.2, Software Model of the 8088/8086 Microprocessor, 16
2.3__ Memory Address Space and Data Organization, 16
2.4 Data Types, 20 :
2.5 Segment Registers and Memory Segmentation, 24
2.6 Dedicated, Reserved, and General-Use Memory, 26
‘2.7_Instruction Pointer. 27
2.8 Data Registers, 28.
xi
Copyrighted material 2.9 Pointer and Index Registers, 29
2.10 Status Register. 3000
Generating a Memory Address, 31
2.12 The Stack 34
213 | Input/Output Address Space, 38
& 3 ASSEMBLY LANGUAGE PROGRAMMING _ 42
3.1 Software: The Microcomputer Program, 42
3.2 _ Assembly Language Program Development on the PC, 48
‘Describing the Problem, 48
Planning the Solution, 50
Coding the Solution with Assembly Language, 51
Creating the Source Program, 54
Assembling the Source Program into an Object Module, 54
Producing a Run Module, 54
ei 1g the Solution, 55°
Fi
33 to ananated ss)
3.4__The MOV Instruction, 56.
3.5__Addressing Modes, 62
“Register Operand Addressing Mode, 62
Immediate Operand Addressing Mode, 66
‘Memory Operand Addressing Modes, 67
4.1_Converting Assembly Language Instructions to Machine Code, 83
42 Encoding a Complete Program in Machine Code, 93 :
43 The PC and its DEBUG Program, 96
4.4 Examining and Modifying the Contents of Memory, 103
DUMP Command, 103
‘ENTER Con 06
FILL Command, 108
MOVE Command, 109
COMPARE Command, 11
SEARCH Command, 112
4.5 _Input and Output of Data, 113
46 Hexadecimal Addition and Subtraction, 114
4.7 Loading, Verifying, and Saving | Machine Language Programs. 115
4.8 Assembling Instructions with the Assemble Command, 121
49 _ Executing Instructions and Programs with the Trace and
‘Go Commands, 124
4.10 Debugging a Program, 129
Copyrighted material 5.1 Data Transfer Instructions, 137
_ The MOV Instruction, 137
‘The XCHG Instruction, 141
The XLAT Instruction, 146
LEA, LDS, and LES Instructions, 148
5.2: Arithmetic Instructions, 153
Addition of Binary Numbers, 153
Addition Instructions: ADD, ADC, INC, AAA, and DAA, 155°
-32-Bit Binary Addition Program, 164
‘ac
32-Bit Binary Subtraction Proen am, 172
Multiplication and Division Instructions: MUL, DIV,
(MUL, DIV... Ww. CWI 1
5.3. Logic Instructions. 179
AND, OR, XOR, and NOT Instructions, 180
‘$4 Shift Instructions, 185 -
"SHL, SHR. SAL, and SAR Instructions, 185
Jsolating the Value of'a Bit in an Operand, 189
5.5 Rotate Instructions, 189
ROL, ROR, RCL, and RCR Instructions, 189
Alignment of Data in Operands, 193
AND PROGRAM STRUCTURES 200
6.1 _Flag-Control Instructions, 200
6.2 Compare Instruction, 206
6.3 Control Flow and the Jump Instructions, 210
‘Unconditional and Conditional Jump, 210
Unconditional Jump instruction, 212
Conditional Jump Instruction, 216
Branch Program Structure—IF-THEN-ELSE, 218 ;
The Loop Program Structure—REPEAT-UNTIL and WHILE-DO, 219
ications Using the Loop and Branch Software Structures, 223
6.4 Subroutines and Subroutine-Handling Instructions, 229
CALL and RET Instructions, 231
PUSH and POP Instructions, 236
6.5 Loops and Loop-Handling Instructions, 244
6.6 Strings and String-Handling Instructions, 252
Move String—MOVSB, MOYSW, 252
Compare String and Scan String—CMPSB/CMPSW and SCASB/SCASW, 253
Copyrighted material Load and Store String—LODSB/LODSW and STOSBIS' TOSW, 254
"Repeat String—REP, 254 0
Autoindexing for String Instructions, 255
WITH MASM 266
7.1 _ Statement Syntax for a Source Program, 267
Assembly Language Statement Syntax, 267
Directive Statement Syntax, 270
Con: wants: ina statement, 70
‘Operand Expressions Using the Arithmetic, Relational, and Logical Operators, 272
Value-Returning and Attribute Operators, 275
7.2._Assembler Directives, 276
‘The Directive, 276
Data Directives, 276
Segment-Control Directives, 279
Modular Programming Directives, 281
Directives far Memory Usage Control,
The End-of- Program Directive, 284
Directive for Program Listing Control, 28
Example of a Source Program Using Directives, 285
7.3 Creating a Source File with an Editor, 286
7.4 Assembling and Linking Programs, 289
Source Listing, 289-
Object Module, 291 ;
‘The Link Program and Modular Programming, 291
Initiating the Assembly and linking Processes, 293
7.5__Loading and Executing a Run Module, 295
1.6 Macro, 297
Concatenation, 299
Macro Locals, 300
Global Identifier, 300 _
Nested Macros, 301
Controlled Expansion (or Conditional Assembly), 303
Using Conditional Statements in Macros, 304
REPEAT statement in a Macro, 304
Advantages of Macro over Subroutines, 307
‘The INCLUDE Directive, 308
Reais
8.1 8088 and 8086 Microprocessors, 316.
8.2 | Minimum-Mode and Maximum-Mode Systems, 316
8.3 Minimum-Mode Interface Signals, 319
Copyrighted material Contents x
Address/Data Bus, 319
Status Signals, 320
Control Signals, 321
Interrupt Signals, 321
DMA Imerface Signals, 322
8.4 Maximum-Mode Interface Signals, 322
8288 Bus Controller: Bus Commands and Control Signals, 322
Lock Signal, 324
Queue Status Signals, 325
Local Bus Control Signals, 325
8.5 Electrical Characteristics, 326
8.6 System Clock, 327
8.7__Bus Cycle and Time States. 329
8.8 Hardware Organization of the Memory Address Space, 330
8.9 Address Bus Status Codes, 334
8.10 Memory Control Signals, 334
Minimum-Mode Memory Control Signals, 334
Maximum-Mode Memory Control Signals, 335
8.11 Read and Write Bus Cycles, 337
Read Cycle, 337
Write Cycle, 338
8.12 Memory Interface Circuits, 340
Address Bus Latches and Buffers, 344
Bank Write and Bank Read Control Logic, 345
Data Bus Transceivers, 346
Address Decoders, 347
8.13 Programmable Logic Arrays, 351
PLAs, GALs, and EPLDs, 351
Block Diagram of a PLA, 351
Architecture of a PLA, 352
8.14 Types of InpuvOutput, 354
Isolated Input/Output, 355
Memory-Mapped Input/Output, 355
8.15 Isolated Input/Output Interface, 357
Minimum-Made Interface, 357
Maximum-Mode Interface, 358
8.16 Input/Output Data Transfers, 360
8.17 Input/Output Instructions, 361
8.18 Input/Output Bus Cycles, 363
MEMORY DEVICES, CIRCUITS, AND SUBSYSTEM
DESIGN 372
9.1 Program and Data Storage Memory, 372
9.2 Read-Only Memory, 374
ROM, PROM, and EPROM, 374
Block Diagram of a Read-Only Memory, 376 Contents
Read Operation, 377
Standard EPROM ICs, 377
Expanding EPROM Word Length and Word Capacity, 381
9.3 Random Access Read/Write Memories, 383
Static and Dynamic RAMs, 384
Block Diagram of a Static RAM, 386
A Static RAM System, 386
Standard Static RAM ICs, 388
SRAM Read and Write Cycle Operation, 389
Standard Dynamic RAM ICs, 392
Battery Backup for the RAM Subsystem, 395
9.4 Parity the Parity Bit, and Parity-Checker/Generator Circuit, 395
9.5 Flash Memory, 400
Block Diagram of a FLASH Memory, 400
Bulk-Erase, Boot Block, and FlashFile FLASH Memories, 401
Standard Bulk-Erase FLASH Memories, 402
Standard Boot Block FLASH Memories, 405
Standard FLASHFile FLASH Memories, 410
9.6 Wait-State Circuitry, 413
9.7 8088/8086 Microcomputer System Memory Circuitry, 414
Program Storage Memory, 418
Data Storage Memory, 419
Solution, 423
INPUT/OUTPUT INTERFACE CIRCUITS AND LSI
PERIPHERAL DEVICES 425
10.1 Core and Special-Purpose V/O Interfaces, 426
10.2. Byte-Wide Output Ports Using Isolated /O, 427
Time-Delay Loop and Blinking an LED at an Output Port, 433
10.3 Byte-Wide Input Ports Using Isolated VO, 433
Polling the Setting of a Switch, 437
10.4 Input/Output Handshaking and a Parallel Printer Interface, 437
10.5 82CSSA Programmable Peripheral Interface, 442
10.6 82C55A Implementation of Parallel Input/Output Ports, 457
10.7 Memory-Mapped Input/output Ports, 460
10.8 82C54 Programmable Interval Timer, 464
Block Diagram of the 82C54, 468
Architecture of the 82C54, 469
Operating Modes of 82C54 Counters, 475
10.9 82C37A Programmable Direct Memory Access Controller, 479
Microprocessor Interface of the 82C37A, 481
DMA Interface of the 82C37A, 483
Internal Architecture of the 82C37A, 485
DMA Interface for the 8088-Based Microcomputer Using the 82C37A, 494
10.10 Serial Communications Interface, 494 Contents xvii
Synchronous and Asynchronous Data Communications, 496
Simplex, Half-Duplex, and Full-Duplex Communication Links, 497
Baud Rate and the Baud-Rate Generator, 498
The RS-232C Interface, 499
10.11 Programmable Communication Interface Controllers, 499
825/4 USART, 501
8250/16450 UART, 510
10.12 Keyboard and Display Interface, 513
10.13 8279 Programmable Keyboard/Display Controller, 516
INTERRUPT INTERFACE OF THE 8088 AND 8086
MICROPROCESSORS 530
11.1 Interrupt Mechanism, Types, and Priority, 530
11.2 Interrupt Vector Table, 532
11.3 Interrupt Instructions, $34
11.4 Enabling/Disabling of Interrupts, 535
11.5 External Hardware-Interrupt Interface Signals, 536
Minimum-Mode Interrupt Interface, 538
Maximum-Mode Interrupt Interface, 539
11.6 External Hardware-Interrupt Sequence, 537
11.7 82CS9A Programmable Interrupt Controller, 545
Block Diagram of the 82C594, 547
Internal Architecture of the 82C59A, 549
Programming the 82C594, 551
Initialization Command Words, 552
Operational Command Words, 556
11.8 Interrupt Interface Circuits Using the 82C59A, 558
11.9. Software Interrupts, 565
11,10 Nonmaskable Interrupt, 566
ILIL Reset, 567
11.12 Internal Interrupt Functions, 569
Divide Error, 572
Overflow Error, 572
Single Step, 373
Breakpoint Interrupt, 573
REAL-MODE SOFTWARE AND HARDWARE ARCHITECTURE
OF THE 80286 MICROPROCESSOR 574
12.1 80286 Microprocessor, 575
12.2 Internal Architecture, 575
12.3 Real-Mode Software Model, 577
12.4 Real-Mode Extended Instruction Set, 579
Push-All and Pop-All Instruction USHA and POPA, 582 xviii
Contents
Stack Frame Instructions—ENTER and LEAVE, 583
Input String and Output String Instructions-INS and OUTS, 587
Check Array Index against Bounds Instruction—BOUND, 588
12.5 Interfaces of the 80286, 586
Memory/IO Interface, 589
Interrupt Interface, $92
DMA Interface, 592
Processor Extension Interface, 593
12.6 82C288 Bus Controller, 591
12.7 System Clock, 594
12.8 Bus Cycle and Bus States, 594
12.9 Memory Interface, 598
Memory Interface Circuit, 601
Hardware Organization of the Memory Address Space, 602
Read Cycle Timing, 603
Write Cycle Timing, 606
Wait States in the Memory Bus Cycle, 608
12.10 Input/Output Interface, 606
WO Interface Circuit, 609
Input and Output Bus Cycle Timing, 611
12.11 Interrupt and Exception Processing, 611
Interrupt Vector and Interrupt Descriptor Tables, 613
External Hardware Interrupt Interface Circuit, 615
Internal Interrupt and Exception Functions, 617
THE 80386, 80486, AND PENTIUM PROCESSOR FAMILIES:
SOFTWARE ARCHITECTURE 621
13.1 80386 Microprocessor Family, 622
13.2 Internal Architecture of the 80386DX Microprocessor, 622
13.3. Real-Address-Mode Software Model of the 80386DX, 625
13.4 Real-Address-Mode Instruction Set of the 80386DX, 628
80386 Specific Instruction Set, 631
Sign-Extend and Zero-Extend Move Instructions: MOVSX and MOVZX, 631
Load Full Pointer Instructions: LSS, LFS, and LGS, 633
Bit Test and Bit Sean Instructions: BT, BTR, BTS, BTC, BSF, and BSR, 633
Byte Set on Condition: SETec, 635
13.5 Protected-Address-Mode Software Architecture of the 80386DX, 634
Protected-Mode Register Model, 636
Protected-Mode Memory Management and Address Translation, 646
13.6 Descriptor and Page Table Entries of the 80386DX, 653
13.7. Protected-Mode System-Control Instruction Set of the 80386DX, 659
13.8 Multitasking and Protection, 662
Protection and the Protection Model, 665
Accessing Code and Data through the Protection Model, 668
Task Switching and the Task State Segment Table, 673 Contents xix
13.9 Virtual 8086 Mode, 674
13.10 80486 Microprocessor Family, 675
Internal Architecture of the 80486, 678
Real-Mode Software Model and Instruction Set of the 80486SX, 679
Protected-Mode Software Architecture of the 80486SX, 684
13.11 80486DX Floating-Point Architecture and Instructions, 685
Organization of Floating-Point Data, 688
Floating-Point Register Stack, 690
Floating-Point Instructions, 691
13.12 Pentium Processor Family, 694
Internal Architecture, 697
Sofiware Architecture of the Pentium Processor, 698
13.13 Multimedia Architecture and Instructions, 702
Organization of SIMD Data, 704
Multimedia Register File, 705
Multimedia Instruction Set, 706
THE 80386, 80486, AND PENTIUM PROCESSOR FAMILIES:
HARDWARE ARCHITECTURE 715
14.1 80386 Microprocessor Family, 716
14.2 Signal Interfaces of the 80386DX, 718
Memory/IO Interface, 721
Interrupt Interface, 727
DMA Interface, 727
Coprocessor Interface, 728
14.3. System Clock of the 80386DX, 726
14.4 80386dx Bus States and Pipelined and Nonpipelined Bus Cycles, 727
Nonpipelined and Pipelined Bus Cycles, 729
Nonpipelined Read Cycle Timing, 732
Nonpipelined Write Cycle Timing, 732
Wait States in a Nonpipelined Memory Bus Cycle, 735
Pipelined Read/Write Cycle Timing, 735
14.5 Memory Organization and Interface Circuits, 734
Hardware Organization of the Memory Address Space, 736
Memory Interface Circuitry, 742
14.6 Input/output Interface Circuits and Bus Cyeles, 742
Inpul/Output Interface and 1/O Address Space, 744
Input and Output Bus Cycle Timing, 747
Protected-Mode Input/Output, 750
14.7 Interrupt and Exception Processing, 750
Interrupt Vector and Interrupt Descriptor Tables, 753
External Hardware-Interrupt Interface, 756
External Hardware-Interrupt Sequence, 758
Internal Interrupt and Exception Functions, 760
14.8 80486DX and 80486DX Microprocessors, 762
Signal Interfaces of the 80486SX MPU, 766 a5
14.9
14.10
14.11
14.12
14.13
Contents
Memory Interface That Employs Dynamic Bus Sizing, 770
Nonburst and Burst Bus Cycles, 771
Cache Memory, 772
Internal Exceptions, 781
Other 80486 Family Microprocessors—80486DX2 and 80486DX4, 779
Pentium Processor Family, 783
Signal Interfaces of the Pentium Processor, 785
Bus Cycles: Nonpipelined, Pipelined, and Burst, 789
Cache Memory of the Pentium Processor, 795
Interrupts and Internal Exceptions of the Pentium Processor, 797
Pentium Pro Processor and Pentium Processor with MMX
Technology, 796
Pentium II Processor, Celeron Processor, and Pentium I Xeon
Processor, 799
Pentium III Processor and Pentium TV Processor, 802
CONNECTING ASSEMBLY LANGUAGE TO C808
15.1
15.2
In-line Assembly Language, 808
Defining Data in In-Line Assembly Language, 811
Parameter Passing, 813
Linking Assembly Language Modules Into Program, 813
Linking C into Assembly Language, 818
APPENDIX 821
INDEX 829 Introduction to
Microprocessors and
Microcomputers
& INTRODUCTION
In the past two decades, most of the important advances in computer system technology have been closely
related to the development of high-performance 16-bit, 32-bit, and 64-bit microprocessor architectures
and the microcomputer systems built with them. During this period, there has been a major change in the
direction of businesses from using larger, expensive minicomputers to smaller, lower-cost microcomputers.
The /BM personal computer (the PC, as it has become known), introduced in mid-1981, was one of the
earliest microcomputers that used a 16-bit microprocessor, the 8088, as its processing unit. A few years
later it was followed by another IBM personal computer, the PC/AT (personal computer advanced tech-
nology). This system was implemented using the more powerful 80286 microprocessor.
The PC and PC/AT quickly became cornerstones of the evolutionary process from minicomputer
to microcomputer. In 1985 an even more powerful microprocessor, the 80386DX, was introduced. The
80386DX was Intel Corporation's first 32-bit member of the 8086 family of microprocessors.
Availability of the 80386DX quickly lead to a new generation of high-performance PC/ATs. In the years
that followed, Intel expanded its 32-bit architecture offering with the 80486 and Pentium processor
families. These processors brought new levels of performance and capabilities to the personal computer
marketplace. Today, Pentium IV processor-based PC/AT microcomputers represent the industry standard
computer platform for the personal computer industry.
‘Since the introduction of the original IBM PC, the microprocessor market has matured significantly.
Today, several complete families of 16- and 32-bit microprocessors are available. They all include sup-
port products such as very Jarge-scale integrated (VLSI) peripheral devices, emulators, and high-level 2 The 8088 and 8086 Microprocessors
software languages. Over the same period of time, these higher-performance microprocessors have
become more widely used in the design of new electronic equipment and computers. This book presents
a detailed study of the software and hardware architectures of Intel Corporation's 8088 and 8086 micro-
processors. An introduction to the 80286, 80386, 80486, and Pentium processors is also included.
In this chapter we begin our study with an introduction to microprocessors and microcomputers,
The following topics are discussed:
1.1 General Architecture of a Microcomputer System
1.2 Evolution of the Intel Microprocessor Architecture
1.1 GENERAL ARCHITECTURE OF A MICROCOMPUTER SYSTEM
The hardware of a microcomputer system can be divided into four functional sections: the input unit,
microprocessing unit, memory unit, and the output unit. The block diagram in Fig. I-1 shows this gen-
eral microcomputer architecture. Each of these units has a special function in terms of overall system
operation. Next we will look at each of these sections in detail.
The heart of a microcomputer is its microprocessing unit (MPU). The MPU of a microcomputer is
implemented with a VLSI device known as a microprocessor, or just processor for short. A
microprocessor is a general-purpose processing unit built into a single integrated circuit (IC). The micro-
processor used in the original IBM PC is Intel Corporation's 8088, shown in Fig. 1-2.
Earlier we indicated that the 8088 is a 16-bit microprocessor. To be more accurate, it is the 8-bit
external bus version in Intel's 8086 family of 16-bit microprocessors. Even though the 8088 has an 8-bit
external bus, its internal architecture is 16 bits in width and it can directly process 16-bit-wide data. For
this reason, the 8088 is considered a 16-bit microprocessor,
The 8088 MPU is the part of the microcomputer that executes instructions of the program and
processes data. It is responsible for performing all arithmetic operations and making the logical decisions ini-
tiated by the computer’s program. In addition to arithmetic and logic functions, the MPU controls overall
system operation.
The input and output units are the means by which the MPU communicates with the outside world,
Input unit such as the keyboard on the IBM PC, allow the user to input information or commands to the
MPU; for instance, a programmer could key in the lines of a BASIC program from the keyboard. Many
other input devices are available for the PC; two examples include a mouse, for implementing a user-
friendlier input interface, and a scanner, for reading in documents.
Primary storage memory
Program
storage
‘memory
Figure 1-1 General architecture of « microcomputer system. Introduction to Microprocessors and Microcomputers 3
Figure 1-2 Intel Corporation's $088 microprocessor. (Courtesy of Intel Corp.)
‘The most widely used output devices of a PC are the monitor and the printer. The output unit in a
microcomputer is used to give the user feedback and to produce documented results. For example, key
‘entries from the keyboard are echoed back to the monitor—that is, by looking at the information
displayed on the monitor, the user can confirm that the correct entry was made. Moreover, the results
produced by the MPU’s processing can be cither displayed or printed. For our earlier example of a
BASIC program, once it is entered and corrected, a listing of the statements could be printed. Alternate
‘output devices are also available for the microcomputer; for instance, many modern PCs are equipped
with an advanced audio processing and speaker system,
‘The memory unit in a microcomputer is used to store information, such as number or character data.
By “store” we mean that memory has the ability to hold this information for processing or for outputting at
a later time. Programs that define how the computer is to operate and process data also reside in memory.
In the microcomputer system, memory can be divided into two different types: primary storage memory
and secondary storage memory. Secondary storage memory is used for long-term storage of information that
is not currently being used. For example, it can hold programs, files of data, and files of information. In the
original IBM PC, the floppy disk drives represented the secondary storage memory subsystems. It had two
5V/inch drives that used double-sided, double-density floppy~diskette storage media that could each store up
to 360Kbytes (360,000 bytes) of data. This floppy diskette is an example of a removable media—that is, to
use the diskette it is inserted into the drive and locked in place. If either the diskette is full or one with a
different file or program is needed, the diskette is simply unlocked, removed, and another diskette installed.
‘The IBM PCXT also employed a second type of secondary storage device called a hard disk drive.
Modern bard disk drive sizes are SGbytes (3000 million bytes), 10Gbytes, 20Gbytes, 40Gbytes, 60Gbytes,
and 80Gbytes. The hard disk drive differs from the floppy disk drive in that the media is fixed, which means
that the media cannot be removed. However, being fixed is not a problem because the storage capacity of
the media is so much larger. Today, desktop PCs are equipped with a hard disk drive in the 20Gbyte to
‘80Gbyte range.
‘Both the floppy diskette and hard disk arc examples of read/write media—that is, a file of data can
be read in from or written out to the storage media in the drive. Another secondary storage device that
is very popular in personal computers today is a CD drive. Here a removable compact disk (CD) is used
as the storage media. This media has very large storage capacity, more than 600Kbytes, but is read-only.
This means you cannot write information onto a CD for storage. For this reason, it is normally used to
store large programs or files of data that are not to be changed. Recently, a recordable CD (CD-R) has
become available, and CD-R drives allow the PC to both read from and write to this media, 4 The 8088 and 8086 Microprocessors
Primary storage memory is normally smaller in size and is used for the temporary storage of active
information, such as the operating system of the microcomputer, the program that is currently being run,
and the data that it is processing. In Fig, I-1 we see that primary storage memory is further subdivided
into program-storage memory and data-storage memory. The program section of memory is used to
store instructions of the operating system and application programs. The data section normally contains
data that are to be processed by the programs as they are executed (¢.g., text files for a word-processor
program or a database for a database-management program). However, programs can also be loaded into
data memory for execution.
‘Typically, primary storage memory is implemented with both read-only memory (ROM) and
random-access read/write memory (RAM) integrated circuits. The original IBM PC had 48Kbytes of
ROM and could be configured with 256Kbytes of RAM without adding a memory-expansion board.
Modern PC/ATs made with the Pentium IV processors are typically equipped with 128Mbytes of RAM.
Data, whether they represent numbers, characters, or instructions of a program, can be stored in either
ROM or RAM. In the original IBM PC, a small part of the operating system and BASIC language are
resident to the computer because they are supplied in ROM. By using ROM, this information is made
nonvolatite—that is, the information is not lost if power is tumed off. This type of memory can only be read
from; it cannot be written into. On the other hand, data that are to be processed and information that
frequently changes must be stored in a type of primary storage memory from which they can be read by the
microprocessor, modified through processing, and written back for storage. This requires a type of memory
that can be both read from and written into. For this reason, such data are stored in RAM instead of ROM.
Earlier we pointed out that the instructions of a program could also be stored in RAM. In fact, to
run the PC operating system such as Windows 98°, it must be loaded into the RAM of the microcom-
puter. Normally the operating system, supplied on CDs, is first read from the CDs and written onto the
hard disk. This is called copying of the operating system onto the hard disk. Once it is copied, the CD
version of Windows 98 may not be used again. The PC is set up so that when it is turned on, Windows
98 is automatically read from the hard disk, written into the RAM, and then run.
RAM is an example of a volatile memory—that is, when power is turned off, the data that it holds
are lost. This is why Windows 98 must be reloaded from the hard disk each time the PC is turned on.
1.2 EVOLUTION OF THE INTEL MICROPROCESSOR ARCHITECTURE
Generally, microprocessors and microcomputers are categorized in terms of the maximum number of
binary bits in the data they process—that is, their word length. Over time, five standard data widths have
evolved for microprocessors and microcomputers: 4-bit, 8-bit, 16-bit, 32-bit, and 64-bit.
Figure 1-3 illustrates the evolution of Intel's microprocessors since their introduction in 1972. The
first microprocessor, the 4004, was designed to process data arranged as 4-bit words. This organization
is also referred to as a nibble of data
The 4004 implemented a very low performance microcomputer by today’s standards. This low
performance and limited system capability restricted its use to simpler, special-purpose applications. It
was commonly used in electronic calculators.
Beginning in 1974, a second generation of microprocessors was introduced. These devices, the
8008, 8080, and 8085, were 8-bit microprocessors and were designed to process 8-bit (1-byte-wide) data
instead of 4-bit data. The 8080, identified in Fig. 1-3, was introduced in 1975.
These newer 8-bit microprocessors were characterized by higher-performance operation, larger
system capabilities, and greater ease of programming. They were able to provide the system requirements
for many applications that could not be satisfied with the earlier 4-bit microprocessors. These extended Introduction to Microprocessors and Microcomputers 5
4
Performance (MPS) Pentium®t processor
Pentium®Pro processor
200
Pentium® processor
v4
+" so3e6ex
1971 1973 1975 1977 1979 1981 1983 1985 1987 1989 1991 1993 1995 1997 1999 Year
Figure 1-3 Evolution of the Intel microprocessor architecture.
capabilities led to widespread acceptance of 8-bit microcomputers for special-purpose system designs.
Examples of these dedicated applications are electronic instruments, cash registers, and printers.
In the mid-1970s, many of the leading semiconductor manufacturers announced plans for develo-
pment of third-generation 16-bit microprocessors. Looking at Fig. 1-3, we see that Intel's first 16-bit
microprocessor, the 8086, became available in 1979 and was followed the next year by its 8-bit bus
version, the 8088. This was the birth of Intel’s 8086 family architecture. Other family members such as.
the 80286, 80186, and 80188 were introduced in the years that followed.
These 16-bit microprocessors provided higher performance and had the ability to satisfy a broad
scope of special-purpose and general-purpose microcomputer applications. They all have the ability to 6 The 8088 and 8086 Microprocessors
handle 8-bit, 16-bit, and special-purpose data types, and their powerful instruction sets are more in line
with those provided by a minicomputer.
In 1985, Intel Corporation introduced its first 32-bit microprocessor, the 80386DX, which brought
true minicomputer-level performance to the microcomputer system. This device was followed by a
16-bit external bus version, the 80386SX, in 1988. Intel’s second generation of 32-bit microprocessors,
called the 80486DX and 80486SX, became available in 1989 and 1990, respectively. They were
followed by a yet higher-performance family, the Pentium processors, in 1993. Today, its fourth gener-
ation member—the Pentium® IV processor, represents this family.
Microprocessor Performance: MIPS and iCOMP
Figure 1-3 illustrates the 8086 microprocessor families relative to their performance. Here
performance is measured in what are called MIPS—that is, how many million instructions they can
execute per second. Today, the number of MIPS provided by a microprocessor is the standard most
frequently used to compare performance. Notice that performance has vastly increased with each new
generation of microprocessor. For instance, the performance identified for the 80386 corresponds to an
80386DX device operating at 33 MHz and equals approximately 11 MIPS. With the introduction of the
80486, the level of performance capability of the architecture was raised to approximately 27 MIPS. This
shows that performance of the 8086 architecture was more than doubled with the introduction of the
33-MHz 80486DX microprocessor.
The MIPS used in this chart are known as Drystone V1.1 MIPS—that is, they are measured by
running a test program called the Drystone program, and the resulting performance measurements are
normalized to those of a VAX 1,1 computer (VAX 1,1 was a minicomputer manufactured by Digital
Equipment Corporation). Therefore, we say that the 80486DX is capable of delivering up to 27 VAX
MIPS of performance.
Intel Corporation provides another method, the iCOMP index, for comparison of the performance
of its 32-bit microprocessors in a personal computer environment. In the iCOMP index chart shown in
Fig. 1-4, a bar is used to represent a measure of the performance for each of Intel's MPUs. Instead of
being related to the performance of a test program, such as the Dystone program, the iCOMP rating of
an MPU is based on a variety of 16-bit and 32-bit MPU performance components important to the
personal computer—that is, the iCOMP rating encompasses performance components that represent
integer mathematics, floating-point mathematics, graphics, and video. The contribution by each of these
categories is also weighted based on an estimate of their normal occurrence in widely used software
applications. For this reason, iCOMP is a more broad-based rating of MPU performance for the personal
computer applications.
The higher the iCOMP rating, the higher the performance offered by the MPU. Notice that the
members of the 80386 family offer low performance when compared to the newer 80486 and Pentium
processor families. In fact, the slowest 80386SX MPU shown in Fig. 1-4, the —20, has a performance
rating of 32, whereas the fastest 80386DX, the -33, is rated at 68. Therefore, a wide range of system-
performance levels can be achieved by selecting among the various members of the 80386, 80486, and
Pentium processor families.
Transistor Density
The evolution of microprocessors was made possible by advances in semiconductor process
technology. Semiconductor-device geometry decreased from about 5 microns in the early 1970s to 8 The 8088 and 8086 Microprocessors
4 Transistors per device (1000s)
8000-
7000-4
6000-|
Pentium’ Pro processor,
5000
Pentium® processor
30005
2000+
10004
300°F
250 E
200
150
50 F
4004 80088080 8085 ons
0 4% -
1970 1972 1974 1976 1978 1980 1982 1964 1990 1992 1994 1996 1998 Year
Figure 1-S Device complexity.
as the 8080 were most widely used as special-purpose microcomputers—a system that has been tailored
to meet the needs of a specific application. These special-purpose microcomputers were used in
embedded control applications—applications in which the microcomputer performs a dedicated control
function.
Embedded control applications are further divided into those that involve primarily event control
and those that require data control. An example of an embedded control application that is primarily
event control is a microcomputer used for industrial process control. Here the program of the micro-
processor is used to initiate a timed. sequence of events. On the other hand, an application that focuses Introduction to Microprocessors and Microcomputers 9
086/ Pentiunt™
|—-| eo2e6 | —-| soaee | —-1 ao4a6 | —-| J...
Reprogrammable 088 processor
microprocessors
SHUM ULL TO nae
micopecessos | eoeo |—-| 8048] [ore5] _f socroex | __[ anssgex]—
0st sores [ "| socteext
Figure 1-6 Processors for embedded control and reprogrammable applications.
more on data control than event control is a hard disk controller interface. In this case, a block of data
that is to be processed—for example, a file of data—must be quickly transferred from secondary stor-
age memory to primary storage memory.
The spectrum of embedded control applications requires a variety of system features and
performance levels. Devices developed specifically for the needs of this marketplace have stressed low
cost and high integration. In Fig. 1-6, we see that highly integrated 8-bit, single-chip microcomputer
devices such as the 8048 and 8051 initially replaced the carlier multichip 8080 solutions. These devices
were tailored to work best as event controllers. For instance, the 8051 offers one-order-of-magnitude-
higher performance than the 8080, a more powerful instruction set, and special on-chip functions such
as ROM, RAM, an interval/event timer, a universal asynchronous receiver/transmitter (UART), and
programmable parallel input/output ports. Today, this type of embedded control device is called a
microcontroller.
Later, devices such as the 80C186XL, 80C188XL, and 80386EX were designed to meet the needs
of data-control applications. They are highly integrated and have additional features such as string
instructions and direct-memory access channels, which handle the movement of data better. They are
known as embedded microprocessors.
The category of reprogrammable microprocessors represents the class of applications in which a
microprocessor is used to implement a general-purpose microcomputer. Unlike a special-purpose
microcomputer, a general-purpose microcomputer is intended to run a variety of software applications —
that is, while it is in use it can be easily reprogrammed to run a different application. Two examples of
reprogrammable microcomputers are the personal computer and file server. Figure 1-6 shows that the
Figure 1-7 Code and system-level compatibility: ‘MW 2p 20) uoddns payduieg —g—1 aunty
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>yureutg Introduction to Microprocessors and Microcomputers n
8086, 8088, 80286, 80386, 80486, and Pentium processor are the Intel microprocessors intended for use
in this type of application,
Architectural compatibility is a critical need of microprocessors developed for use in reprogram-
mable applications. As shown in Fig. 1-7, each new member of the 8086/8088 family provides a superset
of the earlier device’s architecture—that is, the features offered by the 80386 microprocessor are a
superset of the 80286 architecture, and those of the 80286 are a superset of the original 8086/8088
architecture,
Actually, the 80286, 80386, 80486, and Pentium processors can operate in either of two modes:
the real-address mode or protected-address made. When in real mode, they operate like a high-
performance 8086/8088. They can execute what is called the base instruction set, which is abject code
compatible with the 8086/8088. For this reason, operating systems and application programs written for
the 8086 and 8088 run on the 80286, 80386, 80486, and Pentium processor architectures without
modification. Further, a number of new instructions have been added in the instruction sets of the 80286,
80386, 80486, and Pentium processors to enhance their performance and functionality. We say that
object code is upward compatible within the 8086 architecture. This means that 8086/8088 code will run
on the 80286, 80386, 80486, and Pentium processors, but the reverse is not true if any of the new
instructions are in use.
Microprocessors designed for implementing general-purpose microcomputers must offer more
advanced system features than those of a microcontroller; for example, they need to support and manage
a large memory subsystem. The 80286 is capable of managing a 1Gbyte (gigabytes) address space, and
the 80386 supports 64Tbytes (64 terabytes) of memory. Morcover, a reprogrammable microcomputer,
such as a personal computer, normally runs an operating system. The architectures of the 80286, 80386,
80486, and Pentium processors have been enhanced with on-chip support for operating system functions
such as memory management, protection, and multitasking. These new features become active only
when the MPU is operated in the protected mode. The 80386, 80486, and Pentium processors also have
a special mode of operation known as virtual 8086 mode that permits 8086/8088 code to be run in the
protected mode.
Reprogrammable microcomputers, such as those based on the 8086 family, require a variety of
input/output resources. Figure 1-8 shows the kinds of interfaces that are typically implemented in a
personal computer or a microcomputer system. A large family of VLSI peripheral ICs (examples are
floppy disk controllers, hard disk controllers, local area network controllers, and communication
controllers) is needed to support a reprogrammable microprocessor such as the 8086, 80286, 80386,
80486, and Pentium processor. For this reason, these processors are designed to implement a multi-
chip microcomputer system, which can easily be configured with the appropriate set of input/output
interfaces.
REVIEW PROBLEMS
Section 1.1
1. What are the four building blocks of a microcomputer system?
2. What is the heart of the microcomputer system called?
3. Is the 8088 an 8-bit or a 16-bit microprocessor? Explain.
4, What is the primary input unit of the PC? Give two other examples of input units available for the PC.
5. What are the primary output devices of the PC?
6. Into what two sections is the memory ofa PC partitioned?
7. What is the storage capacity of the standard 5'/,-inch floppy diskette of the original PC? What is the
storage capacity of the standard hard disk drive of the original PCXT? wz The 8088. and 8086 Microprocessors.
8. What do ROM and RAM stand for?
9, How much ROM was provided in the original PC’s processor board? What was the maximum amount
of RAM that could be implemented on this processor board?
10. Why must Windows 98 be reloaded from the hard disk each time power is turned on?
Section 1.2
11. What are the standard data word lengths for which microprocessors have been developed?
12. What was the first 4-bit microprocessor introduced by Intel Corporation? Also name 8-bit, 16-bit and
32-bit microprocessors introduced.
13. Name five 16-bit members of the 8086 family architecture.
14, What does MIPS stand for?
15. Approximately how many MIPS are delivered by the 33 MHz 80486DX?
16. What is the name of the program that is used to run the MIPS measurement test for the data in
Fig, 1-3?
17. What is the iCOMP rating of an 80386SX-25 MPU? An 80386DX-25 MPU?
18. Approximately how many transistors are used to implement the 8088 microprocessor, the 80286
microprocessor, the 80386DX microprocessor, the 80486DX microprocessor and the Pentium processor?
19. What is an embedded microcontroller?
20. Name the two groups into which embedded processors are categorized based on applications.
21. What is the difference between a multichip microcomputer and a single-chip microcomputer?
22, Name six 8086 family microprocessors intended for use in reprogrammable microcomputer applications,
23, List the two modes of operation for 80386,
24, What is meant by upward software compatibility relative to 8086 architecture microprocessors?
25, List three advanced architectural features provided by the 80386DX microprocessor,
26. Give three types of VLSI peripheral support devices needed in a reprogrammable microcomputer
system. Software Architecture
of the 8088 and 8086
Microprocessors
A INTRODUCTION
In this chapter we shall study in detail the 8088 and 8086 microprocessors and their assembly language
programming. To program either the 8088 or 8086 using assembly language, we must understand how
the microprocessor and its memory and input/output subsystems operate from a software point of view.
For this reason, in this chapter, we will examine the sofiware architecture of the 8088 and 8086 micro-
processors. The description that follows frequently refers only to the 8088 microprocessor, but every-
thing that is described for the 8088 also applies to the 8086. This is because the software architecture of
the 8086 is identical to that of the 8088, The following topics are covered he
2.1 Microarchitecture of the 8088/8086 Microprocessor
2.2 Software Model of the 8088/8086 Microprocessor
2.3 Memory Address Space and Data Organization
2.4 Data Types
2.5 Segment Registers and Memory Segment
2.6 Dedicated, Reserved, and General-Use Memory
2.7. Instruction Pointer
2.8 Data Registers
2.9 Pointer and Index Registers
2.10 Status Register 14 The 8088 and 8086 Microprocessors
2.11 Generating a Memory Address
2.12 The Stack
2.13 Input/Output Address Space
2.1 MICROARCHITECTURE OF THE 8088/8086 MICROPROCESSOR
The microarchitecture of a processor is its internal architecture—that is, the circuit building blocks that
implement the software and hardware architectures of the 8088/8086 microprocessors. Due to the
requirement of additional features and higher performance, the microarchitecture of a microprocessor
family evolves over time. In fact, a new microarchitecture is introduced for Intel’s 8086 family every
few years, Each new generation of processors (the 8088/8086, 80286, 80386, 80846, and Pentium
processors) represents significant changes in the microarchitecture of the 8086.
The microarchitectures of the 8088 and 8086 microprocessors are similar. They both employ
parallel processing—that is, they are implemented with several simultaneously operating processing
units. Figure 2-1 (a) illustrates the internal architecture of the 8088 and 8086 microprocessors. They
contain two processing units: the bus interface unit (BIU) and the execution unit (EU). Each unit has
dedicated functions and both operate at the same time. In essence, this parallel processing effectively
makes the fetch and execution of instructions independent operations. This results in efficient use of the
system bus and higher performance for 8088/3086 microcomputer systems.
The bus interface unit is the 8088/8086’s connection to the outside world. By interface, we
mean the path by which it connects to external devices, The BIU is responsible for performing all
external bus operations, such as instruction fetching, reading and writing of data operands for mem-
ory, and inputting or outputting data for input/output peripherals. These information transfers take
place over the system bus. This bus includes an 8-bit bidirectional data bus for the 8088 (16 bits for
the 8086), a 20-bit address bus, and the signals needed to control transfers over the bus. The BIU is
not only responsible for performing bus operations, it also performs other functions related to
instruction and data acquisition. For instance, it is responsible for instruction queuing and address
generation.
To implement these functions, the BIU contains the segment registers, the instruction pointer, the
address generation adder, bus control logic, and an instruction queue. Figure 2-1(b) shows the bus inter-
face unit of the 8088/8086 in detail. The BIU uses a mechanism known as an instruction queue to imple-
ment a pipelined architecture. This queue permits the 8088 to prefetch up to 4 bytes (6 bytes for the 8086)
of instruction code. Whenever the queue is not full—that is, it has room for atleast 2 more bytes, and, at
the same time, the execution unit is not asking it to read or write data from memory—the BIU is free to
look ahead in the program by prefetching the next sequential instructions. Prefetched instructions are held
in the first-in first-out (FIFO) queue. Whenever a byte is loaded at the input end of the queue, it is auto-
matically shifted up through the FIFO to the empty location nearest the output. Here the code is held until
the execution unit is ready to accept it. Since instructions are normally waiting in the queue, the time
needed to fetch many instructions of the microcomputer’s program is climinated, If the queue is full and
the EU is not requesting access to data in memory, the BIU does not need to perform any bus operations.
These intervals of no bus activity, which occur between bus operations are known as idle states.
The execution unit is responsible for decoding and executing instructions. Notice in Fig. 2~1(b)
that it consists of the avichmetic logic unit (ALU), status and control flags, general-purpose registers, and
temporary-operand registers. The EU accesses instructions from the output end of the instruction queue
and data from the general-purpose registers or memory. It reads one instruction byte after the other from
the output of the queue, decodes them, generates data addresses if necessary, passes them to the BIU and
requests it to perform the read or write operations to memory or 1/O, and performs the operation Software Architecture of the 8088 and 8086 Microprocessors 6
Bus
EXECUTION (INSTRUCTION | | reRFace
UNIT PIPELINE UNIT
SYSTEM BUS
fa)
EXECUTION UNIT BUS INTERFACE UNIT
(EU) (Blu)
—ts > 6
TDDRESS LMULTIPLEXED BUS
GENERATION
‘AND BUS
‘CONTROL
(OPERANDS
INSTRUCTION:
QUEUE
6 BYTES (8086)
4 BYTES (8088)
tb)
Figure 2-1 (a) Pipelined architecture of the 8088/8086 microprocessors. (Reprinted with permission of Intel Corporation, Copyright/Intel
Corp. 1981) (b) Execution and bus interface units. (Reprinted with permission of Intel Corp., Copyright/Intel Corp. 1981) 16 ‘The 8088 and 8086 Micrapracessors
specified by the instruction, The ALU performs the arithmetic, logic, and shift operations required by an
instruction. During execution of the instruction, the EU may test the status and control flags, and updates
these flags based on the results of executing the instruction. If the queue is empty, the EU waits for the
next instruction byte to be fetched and shifted to the top of the queue.
& 2.2 SOFTWARE MODEL OF THE 8088/8086 MICROPROCESSOR
‘The purpose of developing a software model is to aid the programmer in understanding the operation of
the microcomputer system from a software point of view. To be able to program a microprocessor, one
does not need to know all of its hardware architectural features. For instance, we do not necessarily need
to know the function of the signals at its various pins, their electrical connections, or their electrical
switching characteristics. Also the function, interconnection, and operation of the internal circuits of the
microprocessor need not be considered. What is important to the programmer is to know the various reg-
isters within the device and to understand their purpose, functions, operating capabilities, and limita-
tions. Furthermore, it is essential that the programmer know show external memory and input/output
peripherals are organized, how information is arranged in registers, memory, and input/output, and how
memory and I/O are addressed to obtain instructions and data. This information represents the software
architecture of the processor. Unlike the microarchitecture, the software architecture changes only slightly
from generation to generation of processor.
The software model in Fig. 2~2 illustrates the software architecture of the 8088 microprocessor.
Looking at this diagram, we see that it includes 13 16-bit intemal registers: the instruction pointer (IP), four
data registers (AX, BX, CX, and DX), ove pointer registers (BP and SP), nwo index registers (SI and Dl),
and four segment registers (CS, DS, SS, and ES). In addition, there is another register called the status reg-
ister (SR), with nine of its bits implemented as status and control flags.
Figure 2-2 shows that the 8088 architecture implements independent memory and input/output
address spaces, Notice that the memory address space is 1,048,576 bytes (1 Mbyte) in length and the /O
address space is 65,536 bytes (64 Kbytes) in length. Our concem here is what can be done with this software
architecture and how to do it through software. For this purpose, we will now begin a detailed study of the
elements of the model and their relationship to software.
4 2.3 MEMORY ADDRESS SPACE AND DATA ORGANIZATION
Now that we have introduced the idea of a software model, let us look at how information such as numbers,
characters, and instructions are stored in memory. As shown in Fig. 2-3, the 8088 microcomputer supports
1 Mbyte of extemal memory. This memory space is organized from a software point of view as individual
bytes of data stored at consecutive addresses over the address range 00000, , to FFFFF ,,. Therefore, memory
in an 8088-based microcomputer is actually organized as 8-bit bytes, not as 16-bit words,
The 8088 can access any two consecutive bytes as a word of data. In this case, the lower-addressed
byte is the least significant byte of the word, and the higher-addressed byte is its most significant byte. Figure
2-4(a) shows how a word of data is stored in memory. Notice that the storage location at the lower address,
00724, contains the value 00000010, = 02,¢,The contents of the next-higher-addressed storage location,
00725, ¢, are 01010101, = 55,¢. These two bytes represent the word 0101010100000010, = 5502, ,.
To permit efficient use of memory, words of data can be stored at what are called even- or odd-
addressed word boundaries. The least significant bit of the address determines the type of word
boundary. If this bit is 0, the word is at an even-address boundary—that is, a word at an even-address
‘boundary corresponds to two consecutive bytes, with the least significant byte located at an even Software Architecture of the 8088 and 8086 Microprocessors 7
Memory space
000005,
External memory
address space
Code segment
(64Kbytes)
Ld
0000; 6
Data segment
(64Kbytes)
$5
cs
Input/output
address space
Stack segment
(64 Kbytes)
FFFFAG
Extra segment
(64Kbytes)
FFFFF 6
Figure 2-2 Software model of the 8088/8086 microprocessor,
FFFFE,
FFF
FFFFC
it
Figure 2-3 Memory address space of the 8088/8086 microprocessor. 18 The 8088 and 8086 Microprocessors
address. For example, the word in Fig. 2~4(a) has its least significant byte at address 0072445.
Therefore, it is stored at an even-address boundary.
‘A word of data stored at an even-address boundary, such as 00000,,, 00002; 4, 00004,., and so on, is
said to be an aligned word—that is, all aligned words are located at an address that is a multiple of 2. On the
other hand, a word of data stored at an odd-address boundary, such as 00001 ¢, 00003 j, or 00005,, and so
on, is called a misaligned word. Figure 2-5 shows some aligned and misaligned words of data. Here words
0, 2, 4, and 6 are examples of aligned-data words, while words | and 5 are misaligned words. Notice that
misaligned word | consists of byte 1 from aligned word 0 and byte 2 from aligned word 2.
When expressing addresses and data in hexadecimal form, it is common to use the letter H to
specify the base. For instance, the number 00AB,¢ can also be written as 00ABH.
EXAMPLE 2.1
‘What is the data word shown in Fig. 2-4(b)? Express the result in hexadecimal form. Is it stored at an
even- or odd-addressed word boundary? Is it an aligned or misaligned word of data?
Solution
The most significant byte of the word is stored at address 0072C,, and equals
11111101) = FD = FDH
Its least significant byte is stored at address 0072B,, and is
10101010, = AA,,=AAH
Together the two bytes give the word
1111110110101010, = FDAA,, = FDAAH
Expressing the address of the least significant byte in binary form gives
0072BH = 0072B,, — 00000000011100101011,
Because the rightmost bit (LSB) is logic 1, the word is stored at an odd-address boundary in memory;
therefore, it is a misaligned word of data.
The double word is another data form that can be processed by the 8088 microcomputer. A double
word corresponds to four consecutive bytes of data stored in memory; an example of double-word data
is a pointer. A pointer is a two-word address element that is used to access data or code in memory. The
Address = Memory Memory Address Memory
(binary) (hexadecimal) (binary)
00725460101 0101] | 55 0072046] 11111101
00724460000 0010} = 0072B4g | 19101010
(a) (b
Figure 2-4 (a) Storing a word of data in memory. (b) An example. Software Architecture of the 8088 and 8086 Microprocessors
Physical
memory
bytes
Byte?
Bytes
Byte 5
Byte a
Byte3
Byte 2
Byte 1
Byteo
Aligned
words:
Word
2
4 Word
1
Word __]
0
J Misatigned
words
Figure 2~5 Examples of aligned and misaligned data words,
word of this pointer that is stored at the higher address is called the segment base address, and the word
at the lower address is called the offset.
Just like for words, a double word of data can be aligned or misaligned. An aligned double word
is located at an address that is a multiple of 4 (¢.g., 00000, ,, 00004,,, and 00008,,). A number of aligned
and misaligned double words of data are shown in Fig. 2-6. Of these six examples, only double words
0 and 4 are aligned double words.
Address
o0008H
00007H
0006H
00005H
00004H
00003
00002H
00001
(00000
Physical
memory | Aligned
double
Bytes | words
Bre? Double
word —
Bytes | Double 5
word
Bytes 4 “| Double
—_ word
Bye 4 Souee 3
pyte3 Dowie
byte 2 Dobie "|=
Byte 1 = |
0 Misaligned
2m double words
Figure 2-6 Examples of aligned and misaligned double words of data. 20 The 8088 and 8086 Microprocessors
An example showing the storage of a pointer in memory is given in Fig, 2~7(a). Here the higher-
addressed word, which represents the segment base address, is stored starting at even-address boundary
00006,,. The most significant byte of this word is at address 00007, and equals 00111011, = 3B,,, Its
least sij icant byte is at address 00006, and equals 01001100, = 4C,,. Combining these two values,
we get the segment base address, which equals 0011101101001100, = 3B4C 6.
The offset part of the pointer is the lower-addressed word. Its least significant byte is stored at
address 00004,,; this location contains 01100101, = 65,4. The most significant byte is at address
00005,,. which contains 00000000, = 00,,. The remulting offset is 0000000001100101, = 0065,,. The
complete double word is 3B4C0063,,. Since this double word starts at address 00004,,, it is an exam-
ple of an aligned double word of data.
Address Memory Memory Address Memory
(binary) (hexadecimal) (hexadecimal)
0000716 }oo11 38 0000816 AO
10000616 4c oo00Ayg| __00
0000546 ao 0000946 55
0000416 ss 0008;¢ |_FF
(a) (o)
Figure 2-7 (a) Storing a 32-bit pointer in memory. (b) An example.
EXAMPLE 2.2
How should the pointer with segment base address equal to A000,, and offset address 55FF,, be stored
at an even-address boundary starting at 00008 ,,? Is the double word aligned or misaligned?
Solution
Storage of the two-word pointer requires four consecutive byte locations in memory, starting at address
00008,,. The least-significant byte of the offset is stored at address 00008,, and is shown as FF, in
Fig. 2-7(b). The most significant byte of the offset, 55, is stored at address 00009,,. These two bytes
are followed by the least significant byte of the segment base address, 00,,, at address 0000A,,, and its
most significant byte, AOj,, at address 0000B,,. Since the double word is stored in memory starting at
address 00008,,. it is aligned.
2.4 DATA TYPES
‘The preceding section identified the fundamental data formats of the 8088 as the byte (8 bits), word (16 bits),
and double word (32 bits). It also showed how each of these elements is stored in memory. The next step is,
to examine the types of data that can be coded into these formats for processing.
The 8088 microprocessor directly processes data expressed in a number of different data types. Let us
begin with the anfeger data type. The 8088 can process data as either unsigned or signed integer numbers;
cach type of integer can be either byte-wide or word-wide. Figure 2-8(a) represents an unsigned byte integer;
this data type can be used to represent decimal numbers in the range 0 through 255. The unsigned word inte-
ger is shown in Fig. 2-8(b): it ean be used to represent decimal numbers in the range 0 through 65,535. Software Architecture of the 8088 and 8086 Microprocessors 2
MsB ise
oT LT TTT Fe
@
(er
Figure 2-8 (a) Unsigned byte integer. (b) Unsigned word integer,
EXAMPLE 2.3
‘What value does the unsigned word integer 1000,, represent?
Solution
First, the hexadecimal integer is converted to binary form:
1000, , = 0001000000000000,
Next, we find the value for the binary number: ‘
000 1000000000000, = 2
= 4096
The signed byte integer and signed word integer in Figs. 2~9(a) and (b) are similar to the unsigned
integer data types just introduced; however, here the most significant bit is a sign bit. A zero in this bit position
identifies a positive number. For this reason, the signed integer byte can represent decimal numbers in the range
+127 to-128, and the signed integer word permits numbers in the range +32,767 to 32,768, respectively. For
example, the number +3 expressed as a signed integer byte is 00000011, (03). On the other hand, the 8088
always expresses negative numbers in 2’s-complement notation. Therefore, ~3 is coded as 11111101, (FD,,).
MsB LSB
oT TTT TT
Sign bit
@)
Sign bit
)
Figure 2-9 (a) Signed byte integer. (b) Signed word integer. 22 The 8088 and 8086 Microprocessors
EXAMPLE 2.4
Assigned word integer equals FEFF js. What decimal number does it represent?
Solution
Expressing the hexadecimal number in binary form gives
FEFFy¢ = LINMIMOIILIII 15
Since the most significant bit is 1, the number is negative and is in 2's complement form. Converting to
its binary equivalent by subtracting 1 from the least significant bit and then complementing all bits gives
FEFF ;, = -0000000100000001,
27
‘The 8088 can also process data that is coded as binary-coded decimal (BCD) numbers. Figure 2-10(a)
lists the BCD values for decimal numbers 0 through 9. BCD data can be stored in either unpacked or
packed form. For instance, the unpacked BCD byte in Fig. 2~10(b) shows that a single BCD digit is
stored in the four least significant bits, and the upper four bits are set to 0. Figure 2-10(c) shows a byte
with packed BCD digits. Here two BCD numbers are stored in a byte, The upper four bits represent the
most significant digit of a two-digit BCD number.
MsB ise
LLTT Ted Do
BCD Digit
(b)
MSB LsB
of T Tee[ T Tee
oo
BCD Digit 1 BCD Digit 0
©
Figure 2-10 (a) BCD numbers. (b) An Unpacked BCD digit. (c) Packed BCD digits. Software Architecture of the 8088 and 8086 Microprocessors 23
EXAMPLE 2.5
The packed BCD data stored at byte address 01000, equal 100100015, What is the two-digit decimal
number?
Solution
Writing the value 10010001, as separate BCD digits gives
100100015 = 1001 ye7,0001 gen = 910
Information expressed in ASCII (American Standard Code for Information Interchange) can also
be directly processed by the 8088 microprocessor. The chart in Fig. 211 (a) shows how numbers, letters,
and control characters are coded in ASCII. For instance, the number 5 is coded as
HyHy = 0110101, = 35H
where H denotes that the ASCII-coded number is in hexadecimal form. As shown in Fig. 2-11(b), ASCII
data are stored as one character per byte.
0 0 4 1 1 1
1 1 o 1 1
ofi}fo]fi]fo}.s
2 3 4 5 6 7
DET sP|o|l@ [P Pp
pei}: [afala
pc2 ® 2 B R
s{4fo|tT t
% 5 —E U u
& 6 F v v
-[7 [sc [wl so Tw
wt pe be pe | |
“[: [s/z/i fz
i K t k }
»t
