The MATRICs RF-FPGA in 180nm SiGe-on-SOI BiCMOS

Lawrence J. Kushner, Kevin W. Sliech, Gregory M. Flewelling, Joseph D. Cali, Curtis M. Grens,
Steven E. Turner, Douglas S. Jansen, Joseph L. Wood, and Gary M. Madison1
BAE Systems, Nashua, NH
1
BAE Systems, Lexington, MA
Abstract—MATRICs (Microwave Array Technology for fabrication costs due primarily to the fine-geometry
Reconfigurable Integrated Circuits) is a DC-to-20 GHz CMOS mask expense.
general purpose reconfigurable array of RF circuits In contrast, many military systems require ASIC size
embedded in a flexible switch fabric. Fabricated in a and weight, but do not require a large number of units and
commercial SiGe-on-SOI BiCMOS process, the MATRICs
therefore cannot amortize the expense of custom ICs in
IC employs SiGe HBTs for high-linearity (> + 10 dBm IIP3)
amplification and low phase-noise frequency generation, and fine-geometry CMOS. Still, raw performance is critical,
SOI FETs for low-loss switching. It achieves high on-chip RF as military systems must operate in hostile RF
isolation (>80 dB at 16 GHz) due to the high-resistivity SOI environments, so linearity, spectral purity, and
substrate, differential signalling, and chip-scale flip-chip interference rejection are of utmost importance. The
bump packaging. MATRICs will allow fixed-function RF MATRICs RF-FPGA IC described in this paper,
systems to have the size, weight, and power benefits of a fabricated in a commercial 180nm SiGe-on-SOI process
custom RF ASIC without the associated long development [1], seeks to address these demanding requirements across
cycle and high NRE, and enable future RF subsystems to be a wide range of applications while minimizing non-
dynamically reconfigured on-the-fly, adapting to changing
recurring engineering (NRE) expense.
environments.
Index Terms— RF-FPGA, reconfigurable, switch matrix,
II. MATRICS RF-FPGA ARCHITECTURE
N-path filter, SiGe-on-SOI BiCMOS, PLL.
Analogous to a digital FPGA, the MATRICs RF-FPGA
I. INTRODUCTION contains an array of reconfigurable RF blocks embedded
Much of the commercial RFIC industry is driven by in a flexible switch fabric (Fig. 1). Amplification, filtering,
high-volume applications such as mobile phones and frequency conversion, and frequency generation are all
portable computing, where low per-unit cost and low dc included on the MATRICs IC, along with on-chip digital
power consumption are achieved by developing full- control and state memory. Unused blocks can be
custom system-on-chips (SoCs) in advanced CMOS powered off and bypassed. Individual blocks have many
process nodes. These SoC development efforts require (50 to 100) bits of fine-grained control, allowing gain, BW,
large engineering teams, and have multi-million dollar linearity, center frequency, etc. to be adjusted statically,
Baseband RF Microwave RF Microwave RF Baseband
(IN) (IN/OUT) (OUT) (IN/OUT) (OUT) (IN/OUT) (OUT)
I Q I Q
Baseband
TIA (Out)
Baseband
TIA (Out)

LO B
8b DAC
Skew
Adjustment
Synch ron izatio n

÷4
BB I/ Q
Currents
(IN)
BB I/ Q
Current s
(OUT)
RF / Baseband
Block
MW
(OUT)
MW
(OUT)
RF / Baseband
Block
BB I/ Q
Cu rrent s
( OUT)
BB I/ Q
Currents
(IN)
Synch ron izatio n

÷4
Skew
Adju stment DAC 8b LOA
LO B
÷ 4 |÷ 8 ÷ 4 |÷ 8

MW
LO A LO A
M IXORAMP
Selection

Selection

2 nd Order LPF A A 2nd Order LPF

MW
N-Phase LO N- Phase LO
LO
LO

Generator B B Generator
Q
Q
BB Q (OUT)

BB Q (OUT)

N ot ch N ot ch
0.2-2GHz BW 0.2- 2GHz BW
5 –1000 MHz BW, 15dB Gain 5 –1000 MHz BW, 15 dB Gain
LNA Q LO
Q
H PF
0.2- 2GH z 2
nd
Order LPF BB RF RF (OUT) RF (OUT) LO
RF BB
2nd O rder LPF
LNA
HPF
0.2- 2GHz

RF BW 0-15dB
Q
RF RF Q 0-1 5dB
RF
gm

BW
gm

SW
LO LO

RF
LNA RF BB

I
TIA
RF SW (IN) SW D ar
(IN)
SW RF
TIA
I
BB RF LNA
RF

(IN) (IN/OUT)
gm

lin
gm

(IN) LO (OUT) LO
Down D (OUT) (IN)
BB RF Ca gt RF BB
D Down
scod on
D AC

Conv ert er C Converter

DAC

C
I I
BB I (OUT)

BB I (OUT)

8b B
Up M IXORAM P e B 8b
Up
Input Stage Slice A Convert ers 2 nd Order LPF 2nd Order LPF Slice A Input Stag e
Dar scod

Conv ert ers

1.8V
Ca
lin e

LDO
I
I

gto

...
...
From BB
...
CM Feed back From BB CM Feedback
n

f or gm st ages Interconn ect Int erconn ect for gm st ag es

Baseband
TIA (Out)
Baseband

SPI 1.8V
TIA (Out)

1.8V
SPI
RF/BB SPI SPI
...

RF/BB
LDO LDO
MW
MW

(IN)
(IN)

BB I/ Q
Current s
BB I/ Q
Current s
Microwave Microwave BB I/ Q BB I/ Q
Cu rrent s Current s
(IN) (OUT)
Block Block ( OUT) (IN)

Microwave
1 to 20 GHz
CFG
Configurable Configurable

CFG Configurable
Frequency
Generator
1.8V SPI SPI 1.8V
Frequency
4b VCO 1b Tuning 7b Tuni ng
LDO & State & State LDO
Generator
2b VCO 1b Tuning 4b VCO
Select
Coarse
Tuning
Voltage
Check
Voltage M emory M emory
7b Tuning
Voltage Vol tage Coarse
2b VCO
Select

Frequency
Check Tuning
DAC

... ...
DAC

10 .0 – 1 3.0 GHz

-
+
Reference +
-
1 0.0 – 13.0 GHz

(IN)
Generator
Out put Tunable Tunable
1 2.6 – 15.2 GHz Tunable Tunable Out put
Buff er Loop N otch 12.6 – 15 .2 GHz
K= 0,1,…,9 (f REF) Reference N otch Loop Buff er
RF Filter Filt er Referen ce (f REF) Filter Filt er K=0,1,…,9 RF
Phase
LOB
(IN)

LOA
(OUT)
÷2
K (IN) Phase K (OUT)
Detector ÷2
÷2 | ÷4 | ÷8 Detector
14.8 – 17 .9 G Hz

÷2 | ÷4 | ÷8
14.8 – 17.9 GHz

M SB

1
9
1 7.4 – 2 1.6 GHz
Divided
Frequency
( fDIV)
Divided
Frequency
(f DIV)
1 7.4 – 2 1.6 GHz
9

1
M SB 1 MHz to 20 GHz
VCO
VCO
Bank
÷ Integer N Phase Phase
Bank CM OS

CMOS
12
Retime 12
S
4
Coherent S? 4 12
Retime 12 ÷ Integer N Counter

Counter
(EM M D) Word Coherent S? S
M odulator Word (EM M D) 11
11 9 M odulator
12 12
FDC Word
20
20
FDC Word Int eger Divide Word Fractional Divide Word
Fract ional Divide W ord In teger Divide Word

Microwave SW SW Microwave
(IN/OUT) (IN/OUT)

BB I/ Q
BB I/ Q
MW
BB I/ Q RF / Baseband
RF / Baseband
BB I/ Q
Current s
Current s
(IN)
Syn ch ro nization Skew
Ad ju st men t DAC 8b MW 8b DAC
Skew
A djustment
Synchr on izatio n Currents
(IN)
Currents
(OUT) Block
(OUT)
÷4 ÷4
Block LO B (OUT) (OUT) LO B

÷ 4 |÷ 8

MW
÷ 4 |÷ 8

MW
LO A LO A

Baseband
MIXORAMP
Selection

Selectio n

2 nd Order LPF A 2 nd Order LPF

A N-Phase LO
N -Phase LO
Baseband
LO

LO

Generator B Generator
B
TIA (Out) I I
TIA (Out)
BB Q (OUT)
BB Q (OUT)

Not ch N ot ch
0.2-2GH z BW 0.2-2GH z BW

5 – 1000 MHz BW, 15dB Gain 5 – 1000 MHz BW , 15dB Gain

LO Q LN A LN A Q LO

2 nd Order LPF
H PF
RF (OUT) RF (OUT) H PF nd BB RF

RF 2 Order LPF
RF BB 0.2-2 GHz
Q 0-15dB
0.2-2GH z
BW
RF RF
BW 0- 15dB Q RF
gm
gm

LO LO

TIA BB RF LN A
SW SW SW LN A RF BB TIA SW
(OUT) RF
I RF Da (IN) (IN)
RF
I RF
(IN/OUT)
gm

gm

(OUT) LO (IN) rli ( IN) LO (OUT)

RF BB
D Down
Ca ngt Dow n D
BB RF
scod on
DAC

Converter Conve rt er
DAC

C C
I I
BB I ( OUT)
BB I (OUT)

Up B 8b M IXORAM P e 8b B Up
2 nd Order LPF Sli ce A Input Stage Input Stage Slice A 2 nd Order LPF
Converters Convert ers
Baseband
Dar scod

Baseband 1.8V
Ca

Q Q
lin e

LDO
g to

TIA (Out)
... ...
TIA (Out ) From BB
Int erconnect
CM Feedback ... CM Feedb ack From BB
Interconnect
n

f or gm st ages f or gm st ages

1.8V
SPI SPI 1.8V

RF/BB SPI SPI

RF/BB
...

LD O LDO
MW

MW
(IN)
(IN)

BB I/ Q
Current s
BB I/ Q
Current s
Microwave M icrowave BB I/ Q
Current s
BB I/ Q
Currents
(OUT) (IN)
Block Block (IN) (OUT)

RF/Baseband
DC to 6 GHz I Q I Q
LOB
Baseband RF Microwave RF Microwave RF Baseband
(OUT) (IN/OUT) (IN) (IN/OUT) (IN) (IN/OUT) (IN)

Fig. 1. MATRIC V2 Architecture

PREPRESS PROOF FILE 1 CAUSAL PRODUCTIONS

 Tunable notch
CFG 1 RF / BB RF / BB
Microwave Amp

MW MW
CFG 2
Baseline CFG
Microwave Block
RF/BB Front-end Experimental CFG CFG CFG
Cal standards
RF / BB RF / BB
RF/BB
Microwave Switches

MW MW

a. Test V1 (5x5mm2) b. MATRICs V1 (5x5mm2) c. Test V2 (5x5mm ) 2

d. MATRICs V2 (8x10mm2)
Fig. 2. First- and second-generation MATRICs RF-FPGA ICs.
after power-up, or dynamically, for on-the-fly 0.01-to-20 GHz Configurable Frequency Generator (CFG)
reconfiguration. Similarly, the switch fabric blocks. Most RF and baseband signals are differentially
interconnecting the blocks is also controlled by local, per- routed on chip, with the higher-frequency signals
block, SPI and state memory. distributed by differential 100Ω grounded CPW
Two generations of MATRICs RF-FPGAs have been transmission lines. Local Oscillator (LO) signals
developed along with additional test chips containing generated by the CFGs employ open-collector CML gates
individual block break-outs (Fig. ). The full-up MATRICs with load-side-only terminations (to save DC power while
ICs contain four 1-to-20 GHz Microwave blocks (MW), maximizing signal swing). Wherever signals cross,
four DC-to-6 GHz RF/Baseband blocks (RF/BB), and two shielded RF cross-unders are employed to maintain
isolation, with greater than 80 dB of isolation
demonstrated at 16 GHz (in the MATRICs V1 chip).
While the test chips are designed for wafer-probe, the
MATRICs die are bumped and flip-chip mounted,
providing low-impedance power supplies, low-parasitic
RF connections, and superior RF isolation.

III. BLOCK DESIGN AND PERFORMANCE

Design and performance of the Microwave and
RF/Baseband blocks are included in this section. The
Configurable Frequency Generator has been submitted
separately for publication [2] and is not discussed here.
A. Microwave Block (MW)
The MATRICs V2 chip (and Test V2 chip) includes a
multi-function 1-to-20 GHz Microwave block (Fig. 3). In
addition to amplification and frequency conversion, the
Microwave block acts as an active 4-way switch, routing
signals between adjacent blocks. The MW block has two
inputs and two outputs: DC-to-6 GHz input and output,
designed to interface with adjacent RF/Baseband blocks,
and 1-to-20 GHz microwave input and output, designed to
interface with other MW blocks or off-chip signals. The
input stages of the MW block employ a Darlington
feedback configuration for wideband, linear operation.
The outputs of these input stages converge at a common-
node in the center of the MW block, before exiting the
MW block through one of two MIXORAMP output stages.
As the name implies, the MIXORAMP stages can be
configure as amplifiers or up/down conversion mixers.
At any given time, only one input stage and one output
stage are powered up, with the off stages acting as active
Fig. 3. Microwave block (Test V2 IC) isolators. The “vertical” microwave path has a minimum

2
 40
dB (depending upon the frequencies at the 3 ports), with a
20
noise figure between 12 and 13 dB.
0 ON
-20 > 70 dB B. RF/Baseband Block (RF/BB)
-40 The DC-to-6GHz RF/Baseband block (Fig. 5) performs
Gain (dB)

OFF
-60 RF amplification and filtering, down-conversion,
ON - measured
-80 ON - simulated baseband gain and filtering, upconversion, and signal
OFF - measured
-100 OFF - simulated routing. The input stage of the RF/BB is reconfigurable,
-120 with switchable gain and RF filtering, and can be
-140 bypassed for high-linearity mixer-first operation.
-160
0 5 10 15 20 25 30
The middle stage of the RF/BB block can be configured
Frequency (GHz)
for 4-path I/Q or 8-path harmonic-reject downconversion,
a. MW-to-MW gain and isolation or bypassed entirely. Its SiGe HBT CML-based N-phase
30
ON - measured LO generator allows the RF/BB block to achieve
20 ON
outstanding 3rd- and 5th-harmonic rejection in 8-path mode
ON - simulated
OFF - measured
10

0
OFF - simulated
(Fig. 6), at the expense of DC power. For narrow-band
applications, or operation above 3 GHz, 4-path mode can
Gain (dB)

-10 > 40 dB
be used, reducing the DC power significantly.
-20
The RF/BB block performs filtering both at RF and
-30
OFF baseband. As a direct-downconversion receiver, the
-40
RF/BB block’s N-path filtering tracks the LO frequency
-50
and can therefore be tuned precisely by tuning the LO.
-60
0 5 10 15
Frequency (GHz)
20 25 30 The output stage of the RF/BB block provides further
b. RF-to-RF gain and isolation gain and filtering, and can also be configured to perform
I/Q upconversion. Multiple RF/BB blocks may be
Fig. 4. Microwave block as amplifier or switch.
MW: 1 to 20 GHz; RF: DC to 6 GHz cascaded either at RF or at baseband to achieve additional
gain and filtering.
of 70 dB on/off ratio to 15 GHz (Fig. 4a), while the Table I compares the RF/Baseband block (in
“horizontal” RF path has better than 40 dB of on/off ratio downconversion mode) to recent research results of
out to 6 GHz (Fig. 4b). These ON/OFF ratios compare similar N-path or harmonic-reject receivers. The
quite favorably to most passive switch designs. MATRICs chips reported here operate over a much wider
Signals may also enter the (left) RF input and exit range of instantaneous bandwidths and achieve superior
through the (top) MW output, or enter the (bottom) MW in-band (IB) and out-of-band (OOB) linearity. This level
input and exit the (right) RF output. Noise figure remains of performance was achieved primarily by employing
under 9 dB in any of these amplifier configurations. As a SiGe HBTs, which results in significantly higher power
mixer, the MW block conversion gain is between 8 to 15 consumption compared with the other research results.

Fig. 5. DC-to-6 GHz RF/Baseband Block (MATRICs V2)

3
 0
REFERENCES
1x1 Measured
-20 desired
Modeled
[1] E. Priesler, J. Zheng, S. Chaudhry, Z. Yan, M. Qamar, and
M. Racanelli, “Adaptability of a 280GHz SiGe BiCMOS
7x7
Harmonic Power (dBc)

-40
Receiver Process for High Frequency Commercial Applications,”
tuned to 3x3 Proc. CSICS 2012
-60 1 GHz 5x5
[2] J. Cali, et. al., “20-GHz PLL-based Configurable
-80
Frequency Generator in 180nm SiGe-on-SOI BiCMOS,”
-100
submitted to RFIC 2015.
[3] C. Andrews and A. Molnar, “A passive mixer-first receiver
-120 with digitally controlled and widely tunable RF interface,”
IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2696–
-140
0 1 2 3 4 5 6 7 8 2708, Dec. 2010.
RF Frequency (GHz)
[4] C.-Y. Yu, I. Lu, Y.-H. Chen, L.-C. Cho, C. Sun, C.-C.
Fig. 6. RF/Baseband block harmonic rejection in 8-path mode, Tang, H.-H. Chang,W.-C. Lee, S.-J. Huang, T.-H. Wu, C.-
with on-chip pre-filter set to ~ 2 GHz. Measured in Test V1 IC. S. Chiu, and G. Chien, “A SAW-less GSM/GPRS/EDGE
receiver embedded in 65-nm SoC,”IEEE J. Solid-State
ACKNOWLEDGMENT Circuits, vol. 46, no. 12, pp. 3047–3060, Dec. 2011.
This research was developed with funding from the [5] D. Murphy, H. Darabi, A. Abidi, A. A. Hafez, A. Mirzaei,
Defense Advanced Research Projects Agency (DARPA), M. Mikhemar, M.-C. Frank Chang, "A Blocker-Tolerant,
under the guidance of Drs. Roy Olsson and William Noise-Cancelling Receiver Suitable for Wideband
Wireless Applications," IEEE J. Solid-State Circuits, vol.
Chappell, and Chris Lesniak of AFRL. The views,
47, no. 12, pp. 2943-2963, Dec. 2012.
opinions, and findings contained in this paper are those of [6] J. Borremans , G. Mandal , V. Giannini , B. Debaillie , M.
the authors and should not be interpreted as representing Ingels , T. Sano , B. Verbruggen and J. Craninckx, “A 40
the official views or policies of the Department of Defense nm CMOS 0.4–6 GHz Receiver Resilient to Out-of-Band
or the U.S. Government. Approved for Public Release on Blockers,” IEEE J. Solid-StateCircuits, vol. 46, no. 7, pp.
1/8/15, Distribution Unlimited. “Non-Technical Data” - 1659-1670, July 2011.
Releasable to Foreign Persons. [7] R. Chenand H. Hashemi, “A 0.5-to-3 GHz Software-
The authors would like to acknowledge Michael Scott , Defined Radio Receiver Using Discrete-Time RF Signal
Scott Jordan, Edward Preisler, and the TowerJazz team for Processing,” IEEE J. Solid-StateCircuits, vol. 49, no. 5, pp.
1097-1111, May 2014.
developing the SBC18H3B SiGe-on-SOI process, and
[8] I. Fabiano, M. Sosio, A. Liscidini, R. Castello, “SAW-Less
thank them for their continued support. Analog Front-End Receivers for TDD and FDD,” IEEE J.
Solid-StateCircuits, vol. 48, no. 12, pp. 3067-3079, Dec.
2013.
TABLE I
COMPARISON OF RF/BASEBAND BLOCK IN N-PATH DOWNCONVERSION MODE TO RECENT RESEARCH.
[3] [4] [5] [6] [7] [8] This work This work
MATRICs V11 MATRICs V22
Technology 65nm CMOS 65nm CMOS 40nm CMOS 40nm CMOS 65nm CMOS 40nm CMOS SiGe-on-180nm SOI CMOS

Frequency (MHz) 100 - 2400 850, 900, 1800, 1900 80 - 2700 400 - 6000 500 - 3000 1800 - 2400 20 - 6000

Instantaneous BW (MHz) 1 4 2 1.5 to 20 8 to 57 (?) 1 20 - 1500 10 - 2000

3rd/5th Harmonic Reject. (dB) 35-43 (<500MHz) 44/? 42/45 none 46/51 54 / 65 60/70 (8-path, with on-chip tunable
pre-filter, <3 GHz)

Image Rejection (dB) - - - - - - > 48 dB over 20 MHz BW

(un-calibrated) > 40 dB over 1 GHz BW

Max Gain (dB) 70 60 72 70 35 45 45 dB per RF/BB

NF (dB) 7 2.9 2 - 12 3-9, LNA 1st 5.5 – 8.8 2 – 3.5 10 - 12.5, LNA 1st
7-15, mix 1st 15 to 21, mix 1st

IB IIP3 (dBm) < -40 0 < -20 +6 -12 - -5 , LNA-1st +6, LNA-1st
+5, mix-1st +16, mix-1st

OOB IIP3 (dBm) +25 - +13.5 +10 +11 +18 +12 , LNA-1st +20, LNA-1st
+28, mix-1st +35, mix-1st

OOB IIP2 (dBm) +56 +50 +54 +30 un-cal’d +46, un- +64 +40 un-calibrated
+70 cal’d cal’d

Pblocker_OOB for CP-1dB (dBm) - +1 -2 -8 -1 0 -10 to + 7 TBD

Power Consumption (mW) 37-70 240 35-78 55 250 - 600 32 1000 to 1500 800 to 2000

Supply Voltages 1.2, 2.5 2.5 1.3 1.1, 2.5 1.2, 2.5 1.2, 1.8 1.8, 3.3

Active Area (mm2) 2 1.4 1.2 2 5.9 0.74 2.2 4.1

1 2
Measured Simulated