NAND/NOR Networks

J. Robert Jump
Department of Electrical and Computer Engineering
Rice University
Houston, TX 77251

The most common basic logic circuits in use today are the NAND gate and NOR gate.
This is because they can be realized by less complex electronic circuits than AND or OR gates
and because either one is a functionally complete gate type. That is, any logical function as
specified by a truth table or logical expression can be realized by a network composed only of
NAND gates or only of NOR gates. There are several useful design techniques based on the
theory of Boolean algebra if the basic logic circuits are AND gates, OR gates, and INVERTERS
(e.g., Karnaugh map minimization). Although an algebra could be developed for the NAND and
NOR operations, ↑ and ¬, it would not be very useful because these operators are not
associative. Moreover, it is usually much easier to formulate a Boolean expression involving
only the AND, OR, and NOT operations, because these correspond to the fundamental logical
connectives used in everyday speech. Therefore, one effective approach to designing with
NAND and NOR gates is to first design the network using AND gates, OR gates, and
INVERTERS, taking advantage of the design techniques derived from the theory of Boolean
algebra. Then, transform this network into one using only NAND gates or NOR gates.

A
A A
A•B A•B A•B
B B
B
A
A A
A∨ B A∨ B A∨ B
B B
B

Fig. 3.45. NAND and NOR Equivalents of AND and OR Gates.

To see that an arbitrary network composed of AND gates, OR gates and INVERTERS can
be transformed into one containing only NAND gates (or only NOR gates), observe that a single
AND gate or OR gate can be realized by connecting together NAND gates (or NOR gates) as
shown in Fig. 3.45. An INVERTER can be viewed as either a one-input NAND or a one-input
NOR gate. Thus every gate in the network to be transformed could simply be replaced by its
NAND or NOR equivalent of Fig. 3.45. This is illustrated for two examples in Fig. 3.46 and
3.47. Note that any time two INVERTERS are cascaded in a network, they can both be
removed. Thus the resulting NAND or NOR network can frequently be simplified.
 A A
4
C C
2
B B
5
D 1 Z D Z
A A
3
D D
a. AND-OR Network. c. Simplified NAND Network.

C
4
2
B
Z
D
5
1
A
D 3
b. NAND Network.

Fig. 3.46. Examples of NAND Network Construction.

A A
B Z B Z
C C
D D
E E
a. AND-OR Network. c. Simplified NOR Network.

A
B 3 Z
C 1
D 4
E
2

b. NOR Network.

Fig. 3.47. Example of NOR Network Construction.

A A
A•B A∨ B
B B
A A
A∨ B A•B
B B

Fig. 3.48. NAND and NOR Equivalent Symbols.

This transformation technique can be simplified somewhat if the alternate NAND and NOR
symbols shown in Fig. 3.48 are used. Note that the justification for these alternate symbols is
based on the two statements of DeMorgan's laws (theorems T16 and T17). Algorithms for
constructing a network containing only NAND gates or a network containing only NOR gates
from an arbitrary combinational network composed of AND, OR, NAND, and NOR gates and
INVERTERS can now be stated. Let N1 denote the original network and N2 be the network to
be constructed.

Algorithm 1: (N2 contains only NAND Gates)

Step 1.
a) Replace each AND gate symbol in the diagram of N1 by the symbol for a
NAND gate.
b) Replace each OR gate or NOR gate symbol in the diagram of N1 by the
symbol for a NAND gate.
c) Replace all INVERTERS in the diagram of N1 by a direct connection.

Step 2.
Consider each connection (1) from a gate output to a gate input, (2) from a network
input terminal to a gate input, or (3) from a gate output terminal to a network output
terminal, in the network produced by Step 1. Insert enough INVERTERS in each of
these connecting paths so that the number of inversion bubbles on gate inputs or
outputs has the same parity (i.e., odd or even) as the corresponding path in the
original network N1

Algorithm 2: (N2 contains only NOR Gates)

Step 1.
a) Replace each OR gate symbol in the diagram of N1 by the symbol for a
NOR gate.
b) Replace each AND gate or NAND gate symbol in the diagram of N1 by the
symbol for a NOR gate.
c) Replace all INVERTERS in the diagram of N1 by a direct connection.

Step 2.
Same as for Algorithm 1.

The first steps of these algorithms can be easily combined to get an algorithm that produces
a network containing both NAND and NOR gates. Replace AND and NAND gate symbols by
the symbol and OR and NOR gate symbols by the symbol in order to use NAND
Gates. To use NOR gates, replace AND and NAND gate symbols by the symbol and OR
and NOR gate symbols by the symbol.
 A
1

3
4
6 Z
2
B
5
C

a. Original Network N1.

x 3
y z
4
6 Z
2
B
5
C w
c. NAND Network N2.

Fig. 3.49. Example of Transformation to a NAND Network.

The transformation algorithm is illustrated for the network in Fig. 3.49a. Fig. 3.49b gives
the network produced by step 1 for NAND gates. Step 2 is illustrated by the network in Fig.
3.49c. Note that the network in Fig. 3.49b represents an intermediate step in the algorithm and it
is not equivalent to the networks in Fig. 3.49a and 3.49c. INVERTER x is added in step 2
because the path from input terminal B to gate 1 contained an odd number of inversion bubbles
(the one on the INVERTER). Similarly, INVERTER y is added in step 2. No inverters were
added to the path from gate 1 to gate 3 (or from gate 2 to gate 3) in Fig. 3.49b since the number
of inversion bubbles is even (2) on this path and also even (0) on the corresponding path of N1.
INVERTER z was added in Step 2 because the path from gate 3 to gate 4 in N 1 contained an odd
number of inversion bubbles (the one on the output of gate 3). However, the number of
inversion bubbles on the path from gate 3 to gate 5 must be even so that none are added in Step
2.

This algorithm is illustrated again by first constructing a NAND network, and then a NOR
network for the Boolean expression.
Z ⇐ (A•B ∨ C•D)•(A∨B)•(C∨D)

Fig. 3.50a gives the AND/OR network realization, Fig. 3.50b the NAND network, and Fig. 3.50c
the NOR network realizations. Instead of inserting INVERTERS between input terminals and
gates, the complemented input variables were used.
A A
B B
A A
B B
Z Z
C C
D D
C C
D D
a. Original Network N1. c. NOR Network N2.

A
B
A
B
Z
C
D
C
D
b. NAND Network N2.

Fig. 3.50. Example of Transformation to a NAND and a NOR Network.