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COMPREHENSIVE SOLDER FATIGUE AND THERMAL CHARACTERIZATION

OF A SILICON BASED MULTI-CHIP MODULE PACKAGE
UTILIZING FINITE ELEMENT ANALYSIS METHODOLOGIES

Bret A. Zahn

Director, Design & Characterization

ChipPAC, Inc.
2775 North Arizona Avenue
Chandler, Arizona 85225
Voice: 480.632.3721 Fax: 480.632.0650
[email protected]

ABSTRACT simulation software tool and the corresponding results

for the solder bump/ball fatigue and steady-state
Viscoplastic finite-element simulation thermal analyses. Some ANSYS parametric design
methodologies were utilized to predict ball and bump language is included for the benefit of those readers
solder joint reliability for a silicon based five-chip who are familiar with the software tool.
multi-chip module package under accelerated
temperature cycling conditions (0C to +100C, 5min Index Terms – microelectronic package
ramp/5min dwell). The analyses utilized the ANSYS characterization, solder fatigue analysis, viscoplastic
sub-modeling methodology by which global model strain energy density, thermal analysis, finite element
simulation results were applied as boundary conditions modeling.
in localized sub-models of the solder balls and bumps.
Multiple ball and bump configurations consisting of 1. INTRODUCTION
both 63Sn/37Pb eutectic and 90Pb/10Sn high
temperature solder materials were investigated. The The integrity of ball and bump solder joints is a
solder structures accommodate the bulk of the plastic major reliability concern in modern microelectronic
strain which is generated during accelerated packages. Temperature fluctuations caused by either
temperature cycling due to the thermal expansion power transients or environmental changes, along with
mismatch between the various stack-up materials in the the resulting thermal expansion mismatch between the
silicon based package. Since plastic strain is a various package materials, results in time and
dominant parameter that influences low-cycle fatigue, temperature dependent creep deformation of solder.
it was used as a basis for evaluation of solder structural This deformation accumulates with repeated cycling
integrity. and ultimately causes solder joint cracking and
The finite element analysis was extended to interconnect failure. To minimize development costs
evaluate the steady-state thermal performance of the and maximize reliability performance, advanced
multi-chip module system. A full-symmetry, three- analysis is a necessity during the design and
dimensional finite element model was required due to development phase of a microelectronic package. This
the non-symmetric nature of the five-chip multi-chip requires the utilization of a life prediction
module package. The finite element analysis methodology that is based on the damage mechanisms
methodology utilized temperature dependent surface experienced in a field operation environment.
coefficients to account for the combined non-linear Several finite element based analysis
effects of natural convection and radiation heat methodologies have been proposed which predict
transfer. Multiple analyses were executed in order to solder joint fatigue life (e.g. Engelmaier [1]; Shine and
quantify the required case-to-ambient thermal Fox [2]; Wong et al [3]; Yamada [4]; Subrahmanyan et
resistance (θca) necessary to properly cool the package al. [5]; Dasgupta et al. [6]; Pao [7]; Clech et al. [8];
with a heat sink or heat pipe apparatus. Syed [9]; Darveaux et al. [10]; and Darveaux [11]).
The paper discusses the evaluation methodologies Of all these methodologies, Darveaux’s seems to be
as implemented in the ANSYS finite element the most popular due to the ease in its implementation.
Darveaux’s methodology links laboratory When performing package level thermal analysis
measurements of low-cycle fatigue crack initiation and using solid model finite element simulation tools, the
crack growth rates to the inelastic work of the solder. convective surface loads which control the cooling of
It is a strain energy based approach, where the work the electronics package are typically applied using heat
term consists of time-dependent creep and time- transfer coefficients derived from suitable correlations.
independent plasticity. This inelastic behavior is These correlations may assume convection from a flat
captured in ANSYS using Anand’s constituitive model plate situated either horizontally or vertically, and
[12]. The modeling methodology utilizes finite experiencing either laminar or turbulent flow across
element analysis to calculate the viscoplastic strain the surface. Furthermore, many of these correlations
energy density accumulated per cycle during thermal assume either a constant surface temperature
or power cycling. The strain energy density is then (isothermal) or a constant surface heat flux (isoflux).
utilized with crack growth data to calculate the number Although computational fluid dynamics (CFD) codes
of cycles to initiate a crack, and the number of cycles are rapidly replacing the practice of estimating surface
for the crack to propagate across a solder joint. The convection coefficients, the use of CFD models has
methodology has been previously presented in the been found to provide minimal improvement over
successful analysis of various electronic assemblies. solid model simulations when performing simple
Amagai [13] generated lifetime predictions for a chip package level thermal analysis as discussed by Zahn et
scale package on an organic printed circuit board. al. [26]. A study by Sarvar et al. [27] concluded that
Fusaro and Darveaux [14] used the viscoplastic although it is not generally correct to assume a single
properties of eutectic solder to analyze the reliability convective heat transfer coefficient across heated and
of a copper baseplate attachment for a power module. unheated surfaces, the use of more than one coefficient
Dougherty et al. [15] analyzed a micro-miniature can be satisfactory, and that complex convection
electronic package. Recently, Johnson [16] utilized coefficient variations are not always necessary for a
the methodology to predict board-level solder joint simple package level thermal analysis. The
reliability of multiple ball grid array packages. methodology utilized in this study to establish model
Unfortunately, there is a material limitation boundary surface convection coefficients has been
inherent to all of these methodologies since they reported by Zahn and Stout [28] and implemented
assume the utilization of eutectic 63Sn/37Pb solder or successfully in multiple package level thermal
some similar combination of solder materials (i.e. analyses.
62Sn/36Pb/2Ag). Life prediction methodologies for
high temperature solder (90Pb/10Sn, 95Pb/5Sn, etc.) 2. SILICON BASED MULTI-CHIP MODULE
or future non-lead based interconnect materials, are PACKAGE
almost non-existent due to their low volume use in
today’s microelectronics packaging industry. A 40x40mm, 697-ball (1.00mm pitch), five-chip
Therefore, for the sake of analytical uniformity, the silicon based multi-chip module (MCM) package was
average amount of viscoplastic strain energy density modeled using full three-dimensional symmetry as
accumulated per thermal cycle for the interface shown in Fig. 1. The basic structure of the MCM
elements which make up the +Z and -Z interconnect package consists of a “microboard” with etched drop-
joints was instead used as a basis for the evaluation of in through holes for the integrated circuit (IC) chips.
the eutectic 63Sn/37Pb and high temperature Each IC chip is partnered with a corresponding
90Pb/10Sn solder materials investigated herein. “micropallet” utilized for connection continuity to the
Thermal simulations of individual microelectronic microboard where signals are routed between MCM
packages using finite element or finite difference based IC’s using copper traces. The IC/micropallet and
software tools allow package designers to minimize micropallet/microboard solder bump connections are
prototype revisions and reduce overall turnaround time secured using standard underfill material. A layer of
from design to production. For these reasons, the benzocyclobutene (BCB) between the silicon and
finite element analysis of the five-chip multi-chip solder balls and bumps acts to redistribute the package
module was extended to include a free-convection, stress on the solder materials due to coefficient of
steady-state thermal evaluation. Numerous studies thermal expansion mismatches in the package profile
investigating multi-chip module package thermal stackup. A simplified profile of the MCM package
performance have been reported in the literature (e.g. geometry is shown in Fig. 2.
Bar-Cohen [17]; Sullhan et al. [18]; Kromann [19];
Aghazadeh and Jain [20]; Stout [21]; Lall et al. [22]; 3. SOLDER BALL AND BUMP FATIGUE
Sofia [23]; Zahn [24-25]). In the case of the package FINITE ELEMENT MODEL
evaluated for this study, two slightly different power
configurations were evaluated in an attempt to Viscoplastic finite-element simulation
determine the necessary cooling system (i.e. heat pipe, methodologies were utilized to predict ball and bump
heat sink, etc.) for optimal operation in a laptop solder joint reliability of the silicon based five-chip
computer environment. MCM package under accelerated temperature cycling
conditions. Due to the non-symmetric nature of the

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MCM package geometry, a full symmetry three- Table 2. Local Fatigue Model Material Properties
dimensional “global” model was created. The global Material Young’s Poissons CTE
model simulation results were utilized to locate Modulus Ratio (1/K)
“worst-case” geometrical locations for the solder balls (MPa)
and solder bumps. These locations were further Silicon 162716.27 0.278 C0=-5.9E-06
evaluated using detailed “local models” whereby the C1=6.3E-08
global model simulation results were applied as local C2=-1.6E-10
model boundary conditions using the built-in ANSYS C3=1.51E-13
submodeling methodology [29]. Copper 128931.96 0.344 C0=13.8E-06
C1=9.4E-09
Fatigue Model Basic Assumptions BCB 2900.00 0.340 52.00E-06
63/37 C0=75842.33 0.350 24.50E-06
A total of four global fatigue models were created C1=-151.68
to evaluate the multiple package profiles caused by 90/10 C0=23713.00 0.350 C0=24.5E-06
two proposed solder ball and two proposed solder C1=-47.23 C1=1.5E-08
bump configurations (e.g. ball1/bump1, ball1/bump2, Underfill 3447.38 0.350 25.00e-06
ball2/bump1, ball2/bump2). Linear elastic, time and
FR4 XY XZ/YZ X/Y
temperature independent properties were assumed for
C0=27923.77 0.390 14.50E-06
all materials in the global models. The global models
C1=-37.16 XY Z
treated the underfill and solder bumps as a single
Z 0.110 67.20E-06
composite layer with volumetrically smeared material
C0=12203.72
properties. Global model material properties are
C1=-16.20
displayed in Table 1.
Property=C0+C1(Temp)+C2(Temp)^2+C3(Temp)^3
Where: Temp=Nodal Temperature in Kelvin
Table 1. Global Fatigue Model Material Properties
Material Young’s Poissons CTE
Table 3. Recommended Anand Constants
Modulus Ratio (1/K)
Constant 63Sn/37Pb 90Pb/10Sn Units
(MPa)
C1 12.41 1.00 MPa
Silicon 162716.27 0.278 2.56E-06
C2 9400 7416 1/K
Copper 128931.96 0.344 16.61E-06
C3 4.0E+06 2000 1/sec
BCB 2900.00 0.340 52.00E-06
C4 1.50 6.0E-04
63/37 30641.69 0.350 24.50E-06
C5 0.303 0.303
90/10 9638.46 0.350 28.96E-06
C6 1378.95 1.0E-09 MPa
Underfill 3447.38 0.350 25.00e-06
C7 13.79 1.00 MPa
FR4 XY XZ/YZ X/Y
C8 0.07 1.0E-09
16850.09 0.390 14.50E-06
Z XY Z C9 1.30 1.00
7375.40 0.110 67.20E-06
Fatigue Model Computational Domain
A total of six local models were created to predict
solder fatigue conditions in the MCM package. Two The focus of this study was to predict the solder
of these local models were for the proposed ball ball and bump fatigue for a select group of
configurations as shown in Fig’s 3 and 4. Two local interconnections. Global and local models were
models were analyzed for the proposed bump developed using the ANSYS Parametric Design
configurations as shown in Fig’s 5 and 6. Finally, two Language (APDL). Due to the non-symmetric nature
local models were created specifically to evaluate the of the problem, full-symmetry three-dimensional
microboard/micropallet and IC/micropallet global models were created. Global models were
interconnect bumps associated with the MPU chip as approximately 110455 nodes and 99800 elements in
displayed in Fig. 7. Note that the local models utilized size. Local models detailed the geometry’s of only
non-linear, viscoplastic, time and temperature one solder ball or bump interconnect. The global
dependent material properties for the 63Sn/37Pb and models utilized ANSYS Solid45 structural elements
90Pb/10Sn solder materials. Local model non-solder whereas the local models incorporated the use of
material properties were input as non-linear and Visco107 elements for the solder materials, and
temperature dependent in nature. Local model Solid45 elements for all other structures.
material properties used in the analysis are displayed
in Table 2. ANSYS captures the inelastic behavior of Fatigue Model Boundary Conditions
the solder materials using Anand’s mathematical
relations [12]. The recommended Anand constants for In the global model the nodes located at three
63Sn/37Pb [11] and 90Pb/10Sn are given in Table 3. bottom corners of the FR4 printed circuit board upon
which the five-chip MCM package was mounted were

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constrained as shown in Fig. 8 using the ANSYS D allsel ! select everything
command. A uniform temperature was applied to all /input,local,cb ! apply boundary constraint
global model elements using the ANSYS BFE
command and the linear global model was executed Finally, the global model simulation results are applied
for a steady-state structural analysis over 1 degree as boundary conditions (or constraints) in the local
Kelvin of temperature change using the default frontal model. The above sequence of commands first
solver. This provided global model results in the form resumes the local model, the preprocessor is then
of displacements per degree Kelvin as shown in Fig. 9. entered, all geometry’s including nodes and elements
From the global model simulation results, the locations are selected, and the global model simulation results
for worst-case solder ball and solder bump are applied as boundary constraints. Note again that
interconnect locations was determined (see Fig. 10) only those local model silicon nodes which were
based on the von Mises nodal stress and strain values. written to the “local.nd” file during the first grouped
Local ball and bump models were created at the pre- sequence of commands are applied with boundary
determined worst-case locations and the ANSYS constraints.
submodeling capability was utilized to interpret and Since the boundary constraints applied to the local
apply displacement boundary constraints. Local ball model are XYZ displacements for the 1 degree Kelvin
models applied displacement constraints to the FR4 temperature change which the linear global model was
test board and silicon materials. Local bump models executed, they may be easily scaled in the thermal
applied constraints to only the silicon materials as cycling of the local model depending on the
displayed in Fig. 11. temperature range to be evaluated using the ANSYS
The sequence of APDL commands required to DSCALE command. The solder fatigue analysis used
obtain the boundary constraints from the global model the following ANSYS solution setup commands:
and apply them to a local model starts by writing a file
which contains the local model nodes in which the user eqslv,pcg,1.0e-08 ! set solver and tolerance
wants global model boundary constraints to be applied. antype,static,new ! set analysis type
Note that the user must save both the global and local nlgeom,on ! turn on lrg def and strain
models using the ANSYS SAVE command so their nropt,auto,,off ! set newton-raphson soln
respective database (db) files can be resumed during
the command sequencing. hightemp=100+273 ! high cycle temp (K)
highramp=300 ! low to high ramp (sec)
/prep7 ! enter preprocessor highdwel=300 ! high dwell (sec)
esel,s,mat,,sili ! select silicon elem
nsle ! select nodes of elem’s lowtemp=0+273 ! low cycle temp (K)
nwrite,local,nd ! write node file lowramp=300 ! high to low ramp (sec)
lowdwel=300 ! low dwell (sec)
The above sequence of commands writes a file named
“local.nd” which consists of the local model silicon delta=hightemp-lowtemp ! delta cycle temp (K)
node numbers and their locations in the global rampstep=delta/10 ! ramp substeps
cartesian coordinate system. Next, the global model is
resumed and boundary conditions are automatically Note that the analysis will use one substep for every 10
interpolated from the global model simulation results degree temperature change in a thermal ramp
based on the local model node locations. Note that (rampstep=delta/10) as suggested by Darveaux [11].
this requires the local model to be generated at the The following sequence of commands were used to
same XYZ coordinates as the user would like to obtain execute the first simulated thermal cycle:
results data from the global model simulation.
tref,hightemp ! set 0 strain at hightemp
resume,global,db ! resume global model
/post1 ! enter postprocessor ! RAMP LOW
allsel ! select everything autots,off ! turn off auto time step
cbdof,local,nd,,local,cb ! write cut boundary nsubst,rampstep ! set substeps for load step
bfe,all,temp,,lowtemp ! apply temp to nodes
The above sequence of commands first resumes the dscale,delta ! scale boundary const
global model, the postprocessor is then entered, all kbc,0 ! linearly ramp temps
geometry’s including nodes and elements are selected, time,lowramp ! set time at end of step
and finally the local.nd file is used to locate and solve ! solve load step
interpolate global model simulation results which are save ! save data
then stored in a file named “local.cb”.
! DWELL LOW
resume,local,db ! resume local model autots,on ! turn on auto time step
/prep7 ! enter preprocessor

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nsubst,10,100,5 ! set time step size smult,vpt,vt,pt ! create volu x work table
bfe,all,temp,,lowtemp ! apply temp to nodes ssum ! sum vt’s, pt’s, and vpt’s
kbc,1 ! maintain temps *get,svpt,ssum,,item,vpt ! get summed vpt’s value
time,lowramp+lowdwel ! set time at end of step *get,svt,ssum,,item,vt ! get summed vt’s value
solve ! solve load step wavg%i%=svpt/svt ! calc wavg for load step
save ! save data *enddo

! RAMP HIGH deltaw=wavg12-wavg8 ! calc delta work

autots,off ! turn off auto time step
nsubst,rampstep ! set substeps for load step After the appropriate interface layer of elements was
bfe,all,temp,,hightemp ! apply temp to nodes selected for the +Z or -Z interconnect joint, the above
dscale,1/delta ! scale boundary const sequence of ANSYS APDL commands was executed
kbc,0 ! linearly ramp temps to calculate the average viscoplastic strain energy
time,lowramp+lowdwel+highramp density accumulated per thermal cycle. Note that 8
solve ! solve load step was the final load step executed as part of thermal
save ! save data cycle 2, and 12 was the final load step executed as part
of thermal cycle 3. This stabilized solder joint
! DWELL HIGH viscoplastic strain energy density accumulated per
autots,on ! turn on auto time step thermal cycle was used to evaluate the fatigue
nsubst,10,100,5 ! set time step size resistance of the ball and bump interconnects and is
bfe,all,temp,,hightemp ! apply temp to nodes presented in Section 5, “Fatigue Model Simulation
kbc,1 ! maintain temps Results”.
time,lowramp+lowdwel+highramp+highdwel
solve ! solve load step 4. THERMAL FINITE ELEMENT MODEL
save ! save data
The FR4 test board for the five-chip MCM
The above command sequence of ramp low, dwell low, package thermal model was expanded to the
ramp high, dwell high accounts for one simulated dimensions of a Joint Electron Device Engineering
thermal cycle. Note that the same sequence of ramp Council (JEDEC) standard four-layer thermal test
low, dwell low, ramp high, dwell high commands are board [30] as shown in Fig. 12. The 40x40mm MCM
repeated for the amount of cycles the user would like package was positioned at the center of the
to simulate. However, the user must adjust the 101.5x101.5x1.6mm JEDEC test board. The thermal
ANSYS TIME command to reflect the time at the end analysis only encompassed one global model
of each load step. For instance, the next sequence of configuration which utilized solder balls as shown in
commands after dwell high would be ramp low, and Fig. 3.
the TIME command line would read as follows:
Thermal Model Basic Assumptions
time,2*lowramp+lowdwel+highramp+highdwel
Table 4. Thermal Model Material Properties
Since the same set of commands is repeated for each Material Conductivity (W/mm·C)
simulated thermal cycle, the user may reduce the Silicon 0.086
amount of ANSYS APDL code by incorporating a do- Copper 0.393
loop which executes once for each desired cycle. BCB 0.0002
However, the full command sequence is presented 63/37 0.050
above for the benefit of the reader. 90/10 0.036
All local models were simulated over three full Underfill 0.013
thermal cycles at which point the stress-strain Static Air 2.635E-05
hysteresis loop stabilized and the change in solder
FR4 XY: 0.001
material plastic work from cycle to cycle became
Z: 0.003
relatively constant. The average viscoplastic strain
energy density accumulated between cycles 2 and 3 at
Due to the non-symmetric nature of the MCM
the +Z and -Z interface element joints was utilized for
package structure, a full-symmetry, three-dimensional
all solder joint fatigue assessments.
finite element model was developed. Steady-state,
laminar flow was assumed in a free or natural
/post1 ! enter post processor
convection environment. These assumptions were
reflected by the utilization of temperature dependent
*do,i,8,12,4 ! get data load steps 8 & 12
heat transfer coefficients which also assumed laminar
set,i,last,1 ! read load step
flow and accounted for both natural convection and
etable,vt,volu ! create elem volu table
radiation heat transfer [28]. Like the global fatigue
etable,pt,nl,plwk ! create elem work table
models, the thermal model treated the underfill and
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solder bumps as a single composite layer with
volumetrically smeared material properties. Thermal c4upcb=-2.744074E-13 ! set upper test pcb coeff's
model material properties are displayed in Table 4. c3upcb=1.219123E-10
c2upcb=-1.959122E-08
Thermal Model Computational Domain c1upcb=1.416470E-06
cnupcb=-2.276034E-05
The focus of the thermal study was to perform a
first order engineering evaluation to determine the c4lpcb=-1.372037E-13 ! set lower test pcb coeff's
appropriate enhanced cooling apparatus (i.e. heat sink, c3lpcb=6.098165E-11
heat pipe, etc.) which would be necessary to cool the c2lpcb=-9.766855E-09
MPU chip to 65C in a 35C ambient environment. The c1lpcb=7.206510E-07
thermal analysis utilized an edited global model from cnlpcb=-8.869051E-06
the solder fatigue study and therefore was
approximately 110455 nodes and 99800 elements in mptgen,1,100,tamb,5 ! generate temp table
size. The model incorporated eight node ANSYS
Solid70 thermal elements for all material structures. ! generate temp dependent surface coefficient tables
mp,hf,20,cnupkg,c1upkg,c2upkg,c3upkg,c4upkg
Thermal Model Boundary Conditions mp,hf,21,cnupcb,c1upcb,c2upcb,c3upcb,c4upcb
mp,hf,22,cnlpcb,c1lpcb,c2lpcb,c3lpcb,c4lpcb
Table 5. Thermal Analysis Power Configurations
IC Name Power Config. 1 Power Config. 2 The c4, c3, c2, c1, and cn values for the various
(Watts) (Watts) boundary surfaces are calculated by performing a
Northbridge 1.80 1.80 fourth order curve fit of the convection + radiation
Southbridge 0.80 0.80 surface coefficients over the desired temperature
Cache RAM 1 2.75 1.50 range. This was done automatically using a
Cache RAM 2 2.75 1.50 mathematical spreadsheet as discussed by Zahn and
MPU 16.00 9.00 Stout [28]. Once the temperature dependent surface
coefficient tables are generated, they are applied to the
Dual surface isoflux free convection correlations appropriate surface nodes using the ANSYS SF
were applied in simulations where a heat sink was not command.
assumed. The isoflux surface coefficients were
calculated using the sum of the dissipated powers for tamb=35 ! set ambient temp
all five MCM chips. Isothermal free convection sf,all,conv,-20,tamb ! apply surface coeff to pkg
correlations were applied in simulations where a
package surface cooling apparatus (i.e.heat sink, heat In the above command line example, the convection
pipe, etc.) was assumed. In these simulations the value is -20 indicating the use of temperature
package surface convection coefficient was applied as dependent convection table 20 generated previously by
a uniform constant value. Thermal simulations were the ANSYS MP command line. The “tamb” value is
repeated until the appropriate package surface the assumed ambient temperature of the cooling
convection coefficient was found which would cool the environment, which for the purpose of this analysis
MPU chip to 65C in a 35C ambient environment. The was set to 35C. Note that in those thermal simulations
final surface convection coefficient was then utilized where an enhanced cooling apparatus was assumed
to calculate a case-to-ambient thermal resistance which attached to the surface of the MCM package, a
would be required of the package surface cooling uniform and constant surface convection coefficient
apparatus. was applied also using the ANSYS SF command.
Chip power dissipations were applied as surface
heat fluxes using the ANSYS SF command. Two 5. FATIGUE MODEL SIMULATION RESULTS
different power configurations were analyzed as
indicated in Table 5. Temperature dependent surface The solder joint viscoplastic strain energy density
convection + radiation coefficients were applied by accumulated per thermal cycle was used to evaluate
first generating a temperature table using the ANSYS the fatigue resistance of the ball and bump
MPTGEN command and then generating interconnects. For abbreviation purposes, we will
corresponding coefficients using the ANSYS MP refer to this as the amount of “plastic work”
command as follows: accumulated per cycle as displayed in Figures 13
through 16 for the various interconnect joints
c4upkg=4.911385E-25 ! set upper pkg coeff's analyzed.
c3upkg=2.835000E-14 Figure 13 shows the local solder ball model
c2upkg=3.163860E-11 fatigue results for the four analyzed MCM package
c1upkg=1.343671E-08 configurations. The reader should refer to Fig’s 3 and
cnupkg=9.368580E-06 4 to view solder ball configurations 1 and 2

-6-
respectively. Due to the increased standoff height of required from the packages enhanced surface cooling
ball configuration 2, the solder fatigue life proves to be apparatus (i.e. heat sink, heat pipe, etc.).
superior. This is certainly the case for the -Z
(ball/pcb) solder joint where the amount of plastic Table 6. Thermal Simulation Results, No Heatsink
work per cycle is significantly reduced. Power Config. 1 Power Config. 2
Figure 14 indicates that the solder bump fatigue (C) (C)
for the Northbridge, Southbridge, and Cache RAM IC Northbridge 214.4 151.5
chips consistently occurs at the +Z end of the solder Southbridge 192.0 137.6
joint connecting the IC’s to their respective Cache RAM 1 227.9 155.4
micropallets. Bump configuration 2 (see Fig. 6), Cache RAM 2 221.2 150.7
which is a combination of high temperature and MPU 277.5 183.4
eutectic solder, provides slightly improved -Z joint
performance over bump configuration 1 (see Fig. 5). Table 7. Thermal Simulation Results, Added Heatsink
However, it is interesting to note that the 100%
Power Config. 1 Power Config. 2
composed eutectic material of solder bump
(C) (C)
configuration 1 seems to provide improved fatigue
performance over bump configuration 2 at the +Z joint Heatsink θCA 0.16 C/W 0.42 C/W
of the IC’s. Northbridge 40.2 45.0
Since the bump profile connecting the MPU IC to Southbridge 37.9 40.7
it respective micropallet does not change during the Cache RAM 1 42.9 45.5
course of this study (see Fig. 7), its fatigue life can Cache RAM 2 42.6 44.4
only be influenced by changes to the Northbridge, MPU 64.7 64.2
Southbridge, and Cache RAM IC solder bump
configurations, or the adjusted configurations of the 1
solder balls. Figure 15 indicates that the fatigue of the θCS + θSA =
MPU/micropallet solder bump interconnect joints
h⋅A
(both +Z and -Z) are in no way sensitive to other ball
Where:
or bump configurations investigated a part of this
study. θCA Case to Ambient Thermal Resistance (C/W)
The weakest solder reliability in the silicon based θCA =(θCS+θSA)
MCM package seems to be in the design of the MPU θCS Case to Sink Thermal Resistance (C/W)
microboard/micropallet solder bump interconnect θSA Sink to Ambient Thermal Resistance (C/W)
joints (see Fig. 7) whose profile is also frozen h Applied Package Surface Convection Coeff.
throughout the study. Figure 16 indicates that the (W/mm2·C)
amount of plastic work per cycle is by far the most A Surface Area of Package (40x40 mm2)
damaging of the study. Although, the utilization of
ball configuration 2 seems to relieve some of the Table 7 displays the θCA values and resulting
damage, the bump +Z and -Z solder joints are still MCM chip temperatures required to cool the MPU.
estimated to accumulate 0.10MPa of plastic work per Figure 18 shows the isotherm simulation results from
thermal cycle. This is the worst combined +/- joint MCM power configuration 1, after the corresponding
fatigue seen in the analysis and therefore, the point of θCA convection coefficient h-value was applied
greatest concern with respect to solder fatigue uniformly across the package surface. The analyst
reliability in the silicon based five-chip MCM would use these resulting θCA values to investigate heat
package. sink or heat pipe manufacturing vendor guides in an
effort to locate cost effective case to sink (θCS) and
6. THERMAL MODEL SIMULATION sink to ambient (θSA) combinations which meet system
RESULTS cooling requirements. However, it should be noted
that this is only a first order thermal analysis in an
Table 6 indicates the free-convection steady-state effort to determine package cooling requirements.
junction temperature simulation results for MCM chip Further analysis using computational fluid dynamics
power configurations 1 and 2 indicated in Table 5 (CFD) simulation methodologies (i.e. ANSYS
without a package heatsink apparatus. Figure 17 FLOTRAN) is strongly encouraged, including some
displays isotherm simulation results from the MCM system level analysis to better assess the circulation
chip power configuration 1 analysis. For both power environment.
configurations, thermal simulations were repeated until
the appropriate package surface convection coefficient 7. SUMMARY
was found which would cool the MPU chip to 65C in a
35C ambient environment. The final surface Finite element analysis methodologies have been
convection coefficient was then utilized to calculate a used to evaluate interconnect joint fatigue performance
case-to-ambient thermal resistance which would be of multiple solder ball and bump configurations in a

-7-
silicon based five-chip MCM package. The fatigue [5] Subrahmanyan, R., “A Damage Integral
analyses utilized the ANSYS sub-modeling Approach for Low-Cycle Isothermal and
methodology by which global model simulation results Thermal Fatigue,” Ph.D. Thesis, Cornell
were applied as boundary conditions in localized sub- University, 1991.
models of the solder balls and bumps. The finite
element analysis was extended to include a full- [6] Dasgupta, A., Oyan, C., Barker, D., and Pecht,
symmetry three-dimensional steady-state thermal M., “Solder Creep-Fatigue Analysis by an
evaluation of the MCM package in order to determine Energy-Partitioning Approach,” ASME Journal
the appropriate θCA required to cool the MPU chip to of Electronic Packaging, Vol. 114, June 1992,
65C in a 35C ambient environment. This included the pp. 152-160.
use of non-linear surface convection + radiation
coefficients to account for the heat loss to the ambient [7] Pao, Y.H., “A Fracture Mechanics Approach to
environment. Methodologies for simulation tool Thermal Fatigue Life Prediction of Solder
implementation were discussed including multiple Joints,” IEEE CHMT, Vol. 15, No. 4, 1992, pp.
examples in the use of the ANSYS Parametric Design 559-570.
Language for pre-processing, solution execution, and
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Although numerous methodologies exist to F.E., and Augis, J.A., “A Comprehensive
convert finite element simulation results (i.e. Surface Mount Reliability Model (CSMR)
viscoplastic strain energy density) to cycles to failure Covering Several Generations of Packaging and
under accelerated temperature cycling conditions, Assembly Technology,” Proceeding of, 43rd
these methodologies assume eutectic solder materials. Electronic Components & Technology
For reasons of analytical uniformity, only the average Conference, June 1993, pp. 62-71.
viscoplastic strain energy density accumulated per
thermal cycle (i.e. plastic work/cycle) was used to [9] Syed, A.R., “Creep Crack Growth Prediction of
evaluate the relative performance of the solder balls Solder Joints During Temperature Cycling – An
and bumps. This was done using only the solder Engineering Approach,” Transactions of the
interface elements at the +Z and -Z solder joint ASME, Vol. 117, June 1995, pp. 116-122.
locations. For more detailed thermal analysis of heat
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evaluate the use of computational fluid dynamic Dody, G., “Reliability of Plastic Ball Grid
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Finally, it would be optimal to extend the analysis pp. 379-442.
in order to evaluate the effects of heat sink attachments
on the second level reliability of solder ball and bump [11] Darveaux, R., “Solder Joint Fatigue Life
interconnect attachments. Model,” Proceedings of TMS Annual Meeting,
Orlando FL, February 1997, pp. 213-218.
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[15] Dougherty, D., Fusaro, J., and Culbertson, D.,
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[16] Johnson, Z., “Implementation of and Extensions Proceedings of the 6th Intersociety Conference
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Fig. 1. Top and bottom views of silicon based five-chip MCM package.

Underfill

MicroBoard IC MicroBoard IC MicroBoard IC MicroBoard

Cu Pads
MicroPallet MicroPallet
BCB
Printed Circuit Board Cu Traces
MicroPallet
Fig. 2. Simplified profile of the MCM package.
Printed Circuit Board

uBoard
0.40mm
Cu 0.0035mm
BCB 0.005mm
0.0035mm
0.05mm
63/3

90/1
0.625mm 0.625mm dia.

0.05mm
0.027mm

FR4 1.57mm

Fig. 3. Solder ball configuration 1.

- 10 -
 uBoard
0.40mm
Cu 0.0035mm
BCB 0.005mm
0.0035mm
0.05mm
63/3

90/1
2.00mm 0.50mm dia.

0.05mm
0.027mm

FR4 1.57mm

Fig. 4. Solder ball configuration 2.

uBoard
0.40mm
0.0035mm 0.05mm dia.

63/3 0.072mm dia.

0.05mm

0.0035mm
0.005mm
0.0035mm

0.30mm
uPallet

Fig. 5. Solder bump configuration 1.

uBoard
0.40mm

0.0035mm
0.05mm 63/3

0.125mm 0.125mm dia.

90/1

uPallet 0.30mm

Fig. 6. Solder bump configuration 2.

- 11 -
 uBoard MPU 0.332mm
0.40mm
Cu 0.0035mm
0.080mm
BCB 0.005mm 90/1
0.0035mm 0.05mm dia.
0.125mm dia.
63/3
0.05mm 0.072mm dia. 0.05mm

63/3
0.0035mm 0.0035mm
0.005mm
0.0035mm
0.30mm uPallet

uBoard/uPallet MPU/uPallet
Bump Configuration Bump Configuration

Fig. 7. MPU MicroBoard/Micropallet bump configuration and MPU IC/Micropallet bump configuration.

Fig. 8. XYZ constraints placed on the FR4 pcb. Fig. 9. Global fatigue results (displacements/K).

- 12 -
Fig. 10. Global model worst-case interconnect locations. Fig. 11. Local fatigue model constraint application.

Fig. 12. Joint Electron Device Engineering Council (JEDEC) standard four-layer thermal test board

Ball Fatigue by Plastic Work/Cycle

3.00E-01
Plastic Work/Cycle (MPa)

2.50E-01

2.00E-01
+Z Joint
1.50E-01
-Z Joint
1.00E-01

5.00E-02

0.00E+00
Ball1/Bump1 Ball1/Bump2 Ball2/Bump1 Ball2/Bump2

Fig. 13. Solder ball viscoplastic strain energy density for +Z and -Z joint elements.

- 13 -
 IC Bump Fatigue by Plastic Work/Cycle

3.00E-01
Plastic Work/Cycle (MPa)

2.50E-01

2.00E-01
+Z Joint
1.50E-01
-Z Joint
1.00E-01

5.00E-02

0.00E+00
Ball1/Bump1 Ball1/Bump2 Ball2/Bump1 Ball2/Bump2

Fig. 14. IC solder bump viscoplastic strain energy density for +Z and -Z joint elements.

MPU IC/uPallet Bump Fatigue by Plastic Work/Cycle

3.00E-01
Plastic Work/Cycle (MPa)

2.50E-01

2.00E-01
+Z Joint
1.50E-01
-Z Joint
1.00E-01

5.00E-02

0.00E+00
Ball1/Bump1 Ball1/Bump2 Ball2/Bump1 Ball2/Bump2

Fig. 15 IC MPU/uPallet solder bump viscoplastic strain energy density for +Z and -Z joint elements.

MPU uBoard/uPallet Bump Fatigue by Plastic Work/Cycle

3.00E-01

2.50E-01
Plastic Work/Cycle

2.00E-01
+Z Joint
1.50E-01
-Z Joint
1.00E-01

5.00E-02

0.00E+00
Ball1/Bump1 Ball1/Bump2 Ball2/Bump1 Ball2/Bump2

Fig. 16. IC MPU uBoard/uPallet solder bump viscoplastic strain energy density for +Z and -Z joint elements.

- 14 -
Fig. 17. Isotherm results from the MCM chip power configuration 1 analysis (no enhanced thermal cooling).

Fig. 18. Isotherm results from the MCM chip power configuration 1 analysis (θCA enhanced package cooling
added).

- 15 -