93AA66A/B/C, 93LC66A/B/C,

93C66A/B/C
4K Microwire Compatible Serial EEPROM
Device Selection Table
Part Number VCC Range ORG Pin Word Size Temp Ranges Packages
93AA66A 1.8-5.5 No 8-bit I P, SN, ST, MS, OT, MC
93AA66B 1.8-5-5 No 16-bit I P, SN, ST, MS, OT, MC
93LC66A 2.5-5.5 No 8-bit I, E P, SN, ST, MS, OT, MC
93LC66B 2.5-5.5 No 16-bit I, E P, SN, ST, MS, OT, MC
93C66A 4.5-5.5 No 8-bit I, E P, SN, ST, MS, OT, MC
93C66B 4.5-5.5 No 16-bit I, E P, SN, ST, MS, OT, MC
93AA66C 1.8-5.5 Yes 8- or 16-bit I P, SN, ST, MS, MC
93LC66C 2.5-5.5 Yes 8- or 16-bit I, E P, SN, ST, MS, MC
93C66C 4.5-5.5 Yes 8- or 16-bit I, E P, SN, ST, MS, MC

Features: Pin Function Table

• Low-Power CMOS Technology Name Function
• ORG Pin to Select Word Size for ‘66C’ Version CS Chip Select
• 512 x 8-bit Organization ‘A’ Devices (no ORG) CLK Serial Data Clock
• 256 x 16-bit organization ‘B’ Devices (no ORG) DI Serial Data Input
• Self-tImed Erase/Write Cycles (including DO Serial Data Output
Auto-Erase)
VSS Ground
• Automatic Erase All (ERAL) Before Write All
(WRAL) NC No internal connection
• Power-On/Off Data Protection Circuitry ORG Memory Configuration
• Industry Standard 3-Wire Serial I/O VCC Power Supply
• Device Status Signal (Ready/Busy)
• Sequential Read Function Description:
• 1,000,000 Erase/Write Cycles The Microchip Technology Inc. 93XX66A/B/C devices
• Data Retention > 200 Years are 4Kbit low-voltage serial Electrically Erasable
• Pb-free and RoHS Compliant PROMs (EEPROM). Word-selectable devices such as
• Temperature Ranges Supported: the 93AA66C, 93LC66C or 93C66C are dependent
upon external logic levels driving the ORG pin to set
- Industrial (I) -40°C to +85°C word size. For dedicated 8-bit communication, the
- Automotive (E) -40°C to +125°C 93XX66A devices are available, while the 93XX66B
devices provide dedicated 16-bit communication.
Advanced CMOS technology makes these devices
ideal for low-power, nonvolatile memory applications.
The entire 93XX Series is available in standard
packages including 8-lead PDIP and SOIC, and
advanced packaging including 8-lead MSOP, 6-lead
SOT-23, 8-lead 2x3 DFN and 8-lead TSSOP. All
packages are Pb-free (Matte Tin) finish.

© 2008 Microchip Technology Inc. DS21795D-page 1

93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
Package Types (not to scale)
ROTATED SOIC PDIP/SOIC
(ex: 93LC46BX) (P, SN)
NC 1 8 ORG* CS 1 8 VCC
VCC 2 7 VSS CLK 2 7 NC
CS 3 6 DO DI 3 6 ORG*
CLK 4 5 DI DO 4 5 VSS

TSSOP/MSOP SOT-23
(ST, MS) (OT)
CS 1 8 VCC DO 1 6 VCC
CLK 2 7 NC
DI 3 6 ORG* VSS 2 5 CS
DO 4 5 VSS
DI 3 4 CLK

DFN
(MC)
CS 1 8 VCC
CLK 2 7 NC
DI 3 6 ORG*
DO 4 5 VSS

*ORG pin is NC on A/B devices.

DS21795D-page 2 © 2008 Microchip Technology Inc.

 93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings(†)

VCC.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. VSS ..........................................................................................................-0.6V to VCC +1.0V
Storage temperature ............................................................................................................................... -65°C to +150°C
Ambient temperature with power applied................................................................................................ -40°C to +125°C
ESD protection on all pins ......................................................................................................................................................≥ 4 kV

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.

TABLE 1-1: DC CHARACTERISTICS

All parameters apply over the specified Industrial (I): TA = -40°C to +85°C, VCC = +1.8V to +5.5V
ranges unless otherwise noted. Automotive (E): TA = -40°C to +125°C, VCC = +2.5V to +5.5V
Param.
Symbol Parameter Min Typ Max Units Conditions
No.
D1 VIH1 High-level input voltage 2.0 — VCC +1 V VCC ≥ 2.7V
VIH2 0.7 VCC — VCC +1 V VCC < 2.7V
D2 VIL1 Low-level input voltage -0.3 — 0.8 V VCC ≥ 2.7V
VIL2 -0.3 — 0.2 VCC V VCC < 2.7V
D3 VOL1 Low-level output voltage — — 0.4 V IOL = 2.1 mA, VCC = 4.5V
VOL2 — — 0.2 V IOL = 100 μA, VCC = 2.5V
D4 VOH1 High-level output voltage 2.4 — — V IOH = -400 μA, VCC = 4.5V
VOH2 VCC - 0.2 — — V IOH = -100 μA, VCC = 2.5V
D5 ILI Input leakage current — — ±1 μA VIN = VSS or VCC
D6 ILO Output leakage current — — ±1 μA VOUT = VSS or VCC
D7 CIN, Pin capacitance (all inputs/ — — 7 pF VIN/VOUT = 0V (Note 1)
COUT outputs) TA = 25°C, FCLK = 1 MHz
D8 ICC write Write current — — 2 mA FCLK = 3 MHz, Vcc = 5.5V
— 500 — μA FCLK = 2 MHz, Vcc = 2.5V
D9 ICC read Read current — — 1 mA FCLK = 3 MHz, VCC = 5.5V
— — 500 μA FCLK = 2 MHz, VCC = 3.0V
— 100 — μA FCLK = 2 MHz, VCC = 2.5V
D10 ICCS Standby current — — 1 μA I – Temp
— — 5 μA E – Temp
CLK = Cs = 0V
ORG = DI = VSS or VCC
(Note 2) (Note 3)
D11 VPOR VCC voltage detect
93AA66A/B/C, 93LC66A/B/C — 1.5V — V (Note 1)
93C66A/B/C — 3.8V — V
Note 1: This parameter is periodically sampled and not 100% tested.
2: ORG pin not available on ‘A’ or ‘B’ versions.
3: Ready/Busy status must be cleared from DO; see Section 3.4 "Data Out (DO)".

© 2008 Microchip Technology Inc. DS21795D-page 3

93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
TABLE 1-2: AC CHARACTERISTICS
All parameters apply over the specified Industrial (I): TA = -40°C to +85°C, VCC = +1.8V to +5.5V
ranges unless otherwise noted. Automotive (E): TA = -40°C to +125°C, VCC = +2.5V to +5.5V
Param.
Symbol Parameter Min Max Units Conditions
No.
A1 FCLK Clock frequency — 3 MHz 4.5V ≤ VCC < 5.5V, 93XX66C only
2 MHz 2.5V ≤ VCC < 5.5V
1 MHz 1.8V ≤ VCC < 2.5V
A2 TCKH Clock high time 200 — ns 4.5V ≤ VCC < 5.5V, 93XX66C only
250 ns 2.5V ≤ VCC < 5.5V
450 ns 1.8V ≤ VCC < 2.5V
A3 TCKL Clock low time 100 — ns 4.5V ≤ VCC < 5.5V, 93XX66C only
200 ns 2.5V ≤ VCC < 5.5V
450 ns 1.8V ≤ VCC < 2.5V
A4 TCSS Chip Select setup time 50 — ns 4.5V ≤ VCC < 5.5V
100 ns 2.5V ≤ VCC < 4.5V
250 ns 1.8V ≤ VCC < 2.5V
A5 TCSH Chip Select hold time 0 — ns 1.8V ≤ VCC < 5.5V
A6 TCSL Chip Select low time 250 — ns 1.8V ≤ VCC < 5.5V
A7 TDIS Data input setup time 50 — ns 4.5V ≤ VCC < 5.5V, 93XX66C only
100 ns 2.5V ≤ VCC < 5.5V
250 ns 1.8V ≤ VCC < 2.5V
A8 TDIH Data input hold time 50 — ns 4.5V ≤ VCC < 5.5V, 93XX66C only
100 ns 2.5V ≤ VCC < 5.5V
250 ns 1.8V ≤ VCC < 2.5V
A9 TPD Data output delay time — 200 ns 4.5V ≤ VCC < 5.5V, CL = 100 pF
250 ns 2.5V ≤ VCC < 4.5V, CL = 100 pF
400 ns 1.8V ≤ VCC < 2.5V, CL = 100 pF
A10 TCZ Data output disable time — 100 ns 4.5V ≤ VCC < 5.5V, (Note 1)
200 ns 1.8V ≤ VCC < 4.5V, (Note 1)
A11 TSV Status valid time — 200 ns 4.5V ≤ VCC < 5.5V, CL = 100 pF
300 ns 2.5V ≤ VCC < 4.5V, CL = 100 pF
500 ns 1.8V ≤ VCC < 2.5V, CL = 100 pF
A12 TWC Program cycle time — 6 ms Erase/Write mode (AA and LC
versions)
A13 TWC — 2 ms Erase/Write mode
(93C versions)
A14 TEC — 6 ms ERAL mode, 4.5V ≤ VCC ≤ 5.5V
A15 TWL — 15 ms WRAL mode, 4.5V ≤ VCC ≤ 5.5V
A16 — Endurance 1M — cycles 25°C, VCC = 5.0V, (Note 2)
Note 1: This parameter is periodically sampled and not 100% tested.
2: This application is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model, which may be obtained from Microchip’s web
site at www.microchip.com.

DS21795D-page 4 © 2008 Microchip Technology Inc.

 93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
FIGURE 1-1: SYNCHRONOUS DATA TIMING

VIH
CS
VIL TCSS TCKH TCKL
TCSH
VIH
CLK
VIL
TDIS TDIH
VIH
DI
VIL
TPD TCZ
TPD
DO VOH
(Read) TCZ
VOL
TSV
DO VOH
(Program) Status Valid
VOL

Note: TSV is relative to CS.

TABLE 1-3: INSTRUCTION SET FOR X16 ORGANIZATION (93XX66B OR 93XX66C WITH ORG = 1)
Instruction SB Opcode Address Data In Data Out Req. CLK Cycles

ERASE 1 11 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY) 11
ERAL 1 00 1 0 X X X X X X — (RDY/BSY) 11
EWDS 1 00 0 0 X X X X X X — High-Z 11
EWEN 1 00 1 1 X X X X X X — High-Z 11
READ 1 10 A7 A6 A5 A4 A3 A2 A1 A0 — D15 – D0 27
WRITE 1 01 A7 A6 A5 A4 A3 A2 A1 A0 D15 – D0 (RDY/BSY) 27
WRAL 1 00 0 1 X X X X X X D15 – D0 (RDY/BSY) 27

TABLE 1-4: INSTRUCTION SET FOR X8 ORGANIZATION (93XX66A OR 93XX66C WITH ORG = 0)
Req. CLK
Instruction SB Opcode Address Data In Data Out
Cycles

ERASE 1 11 A8 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY) 12
ERAL 1 00 1 0 X X X X X X X — (RDY/BSY) 12
EWDS 1 00 0 0 X X X X X X X — High-Z 12
EWEN 1 00 1 1 X X X X X X X — High-Z 12
READ 1 10 A8 A7 A6 A5 A4 A3 A2 A1 A0 — D7 – D0 20
WRITE 1 01 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 – D0 (RDY/BSY) 20
WRAL 1 00 0 1 X X X X X X X D7 – D0 (RDY/BSY) 20

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93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
2.0 FUNCTIONAL DESCRIPTION 2.2 Data In/Data Out (DI/DO)
When the ORG pin is connected to VCC, the (x16) orga- It is possible to connect the Data In and Data Out pins
nization is selected. When it is connected to ground, together. However, with this configuration it is possible
the (x8) organization is selected. Instructions, for a “bus conflict” to occur during the “dummy zero”
addresses and write data are clocked into the DI pin on that precedes the read operation, if A0 is a logic high
the rising edge of the clock (CLK). The DO pin is level. Under such a condition the voltage level seen at
normally held in a High-Z state except when reading Data Out is undefined and will depend upon the relative
data from the device, or when checking the Ready/ impedances of Data Out and the signal source driving
Busy status during a programming operation. The A0. The higher the current sourcing capability of A0,
Ready/Busy status can be verified during an Erase/ the higher the voltage at the Data Out pin. In order to
Write operation by polling the DO pin; DO low indicates limit this current, a resistor should be connected
that programming is still in progress, while DO high between DI and DO.
indicates the device is ready. DO will enter the High-Z
state on the falling edge of CS. 2.3 Data Protection
All modes of operation are inhibited when VCC is below
2.1 Start Condition
a typical voltage of 1.5V for ‘93AA’ and ‘93LC’ devices
The Start bit is detected by the device if CS and DI are or 3.8V for ‘93C’ devices.
both high with respect to the positive edge of CLK for The EWEN and EWDS commands give additional
the first time. protection against accidentally programming during
Before a Start condition is detected, CS, CLK and DI normal operation.
may change in any combination (except to that of a Note: For added protection, an EWDS command
Start condition), without resulting in any device should be performed after every write
operation (Read, Write, Erase, EWEN, EWDS, ERAL operation.
or WRAL). As soon as CS is high, the device is no
longer in Standby mode. After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
An instruction following a Start condition will only be performed before the initial ERASE or WRITE instruction
executed if the required opcode, address and data bits can be executed.
for any particular instruction are clocked in.
Note: When preparing to transmit an instruction, Block Diagram
either the CLK or DI signal levels must be
VCC VSS
at a logic low as CS is toggled active high.

Memory Address
Array Decoder

Address
Counter

Output DO
Data Register
Buffer
DI
Mode
ORG* Decode
CS Logic

CLK Clock
Register

*ORG input is not available on A/B devices

DS21795D-page 6 © 2008 Microchip Technology Inc.

 93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
2.4 Erase The DO pin indicates the Ready/Busy status of the
device if CS is brought high after a minimum of 250 ns
The ERASE instruction forces all data bits of the speci- low (TCSL). DO at logical ‘0’ indicates that programming
fied address to the logical ‘1’ state. CS is brought low is still in progress. DO at logical ‘1’ indicates that the
following the loading of the last address bit. This falling register at the specified address has been erased and
edge of the CS pin initiates the self-timed program- the device is ready for another instruction.
ming cycle, except on ‘93C’ devices where the rising
edge of CLK before the last address bit initiates the Note: Issuing a Start bit and then taking CS low
write cycle. will clear the Ready/Busy status from DO.

FIGURE 2-1: ERASE TIMING FOR 93AA AND 93LC DEVICES

TCSL
CS
Check Status

CLK

DI 1 1 1 AN AN-1 AN-2 ••• A0

TSV TCZ

High-Z Ready
DO Busy
High-Z

TWC

FIGURE 2-2: ERASE TIMING FOR 93C DEVICES

TCSL
CS
Check Status

CLK

DI 1 1 1 AN AN-1 AN-2 ••• A0

TSV TCZ

High-Z
DO Busy Ready
High-Z

TWC

© 2008 Microchip Technology Inc. DS21795D-page 7

93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
2.5 Erase All (ERAL) The DO pin indicates the Ready/Busy status of the
device, if CS is brought high after a minimum of 250 ns
The Erase All (ERAL) instruction will erase the entire low (TCSL).
memory array to the logical ‘1’ state. The ERAL cycle
is identical to the erase cycle, except for the different Note: Issuing a Start bit and then taking CS low
opcode. The ERAL cycle is completely self-timed and will clear the Ready/Busy status from DO.
commences at the falling edge of the CS, except on VCC must be ≥ 4.5V for proper operation of ERAL.
‘93C’ devices where the rising edge of CLK before the
last data bit initiates the write cycle. Clocking of the
CLK pin is not necessary after the device has entered
the ERAL cycle.

FIGURE 2-3: ERAL TIMING FOR 93AA AND 93LC DEVICES

TCSL
CS
Check Status

CLK

DI 1 0 0 1 0 x ••• x

TSV TCZ

High-Z
DO Busy Ready
High-Z

TEC
VCC must be ≥4.5V for proper operation of ERAL.

FIGURE 2-4: ERAL TIMING FOR 93C DEVICES

TCSL
CS
Check Status

CLK

DI 1 0 0 1 0 x ••• x

TSV TCZ

High-Z
DO Busy Ready
High-Z

TEC

DS21795D-page 8 © 2008 Microchip Technology Inc.

 93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
2.6 Erase/Write Disable and Enable To protect against accidental data disturbance, the
(EWDS/EWEN) EWDS instruction can be used to disable all erase/write
functions and should follow all programming opera-
The 93XX66A/B/C powers up in the Erase/Write tions. Execution of a READ instruction is independent of
Disable (EWDS) state. All Programming modes must be both the EWEN and EWDS instructions.
preceded by an Erase/Write Enable (EWEN) instruction.
Once the EWEN instruction is executed, programming
remains enabled until an EWDS instruction is executed
or Vcc is removed from the device.

FIGURE 2-5: EWDS TIMING

TCSL
CS

CLK

DI 1 0 0 0 0 x ••• x

FIGURE 2-6: EWEN TIMING

TCSL

CS

CLK

1 0 0 1 1 x ••• x
DI

2.7 Read the rising edge of the CLK and are stable after the
specified time delay (TPD). Sequential read is possible
The READ instruction outputs the serial data of the when CS is held high. The memory data will
addressed memory location on the DO pin. A dummy automatically cycle to the next register and output
zero bit precedes the 8-bit (If ORG pin is low or A-Version sequentially.
devices) or 16-bit (If ORG pin is high or B-version
devices) output string. The output data bits will toggle on

FIGURE 2-7: READ TIMING

CS

CLK

DI 1 1 0 An ••• A0

High-Z
DO 0 Dx ••• D0 Dx ••• D0 Dx ••• D0

© 2008 Microchip Technology Inc. DS21795D-page 9

93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
2.8 Write The DO pin indicates the Ready/Busy status of the
device, if CS is brought high after a minimum of 250 ns
The WRITE instruction is followed by 8 bits (If ORG is low (TCSL). DO at logical ‘0’ indicates that programming
low or A-version devices) or 16 bits (If ORG pin is high is still in progress. DO at logical ‘1’ indicates that the
or B-version devices) of data which are written into the register at the specified address has been written with
specified address. For 93AA66A/B/C and 93LC66A/B/C the data specified and the device is ready for another
devices, after the last data bit is clocked into DI, the instruction.
falling edge of CS initiates the self-timed auto-erase and
programming cycle. For 93C66A/B/C devices, the self- Note: Issuing a Start bit and then taking CS low
timed auto-erase and programming cycle is initiated by will clear the Ready/Busy status from DO.
the rising edge of CLK on the last data bit.

FIGURE 2-8: WRITE TIMING FOR 93AA AND 93LC DEVICES

TCSL

CS

CLK

DI 1 0 1 AN ••• A0 Dx ••• D0

TSV TCZ

High-Z
DO Busy Ready
High-Z

TWC

FIGURE 2-9: WRITE TIMING FOR 93C DEVICES

TCSL

CS

CLK

DI 1 0 1 AN ••• A0 Dx ••• D0

TSV TCZ

High-Z
DO Busy Ready
High-Z

TWC

DS21795D-page 10 © 2008 Microchip Technology Inc.

 93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
2.9 Write All (WRAL) The DO pin indicates the Ready/Busy status of the
device if CS is brought high after a minimum of 250 ns
The Write All (WRAL) instruction will write the entire low (TCSL).
memory array with the data specified in the command.
For 93AA66A/B/C and 93LC66A/B/C devices, after the Note: Issuing a Start bit and then taking CS low
last data bit is clocked into DI, the falling edge of CS will clear the Ready/Busy status from DO.
initiates the self-timed auto-erase and programming VCC must be ≥ 4.5V for proper operation of WRAL.
cycle. For 93C66A/B/C devices, the self-timed auto-
erase and programming cycle is initiated by the rising
edge of CLK on the last data bit. Clocking of the CLK
pin is not necessary after the device has entered the
WRAL cycle. The WRAL command does include an
automatic ERAL cycle for the device. Therefore, the
WRAL instruction does not require an ERAL instruction,
but the chip must be in the EWEN status.

FIGURE 2-10: WRAL TIMING FOR 93AA AND 93LC DEVICES

TCSL

CS

CLK

DI 1 0 0 0 1 x ••• x Dx ••• D0
TSV TCZ

High-Z Busy Ready

DO
HIGH-Z
TWL

VCC must be ≥4.5V for proper operation of WRAL.

FIGURE 2-11: WRAL TIMING FOR 93C DEVICES

TCSL

CS

CLK

DI 1 0 0 0 1 x ••• x Dx ••• D0
TSV TCZ

High-Z
DO Busy Ready
HIGH-Z

TWL

© 2008 Microchip Technology Inc. DS21795D-page 11

93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
3.0 PIN DESCRIPTIONS

TABLE 3-1: PIN DESCRIPTIONS

SOIC/PDIP/
Name MSOP/TSSOP/ SOT-23 Rotated SOIC Function
DFN
CS 1 5 3 Chip Select
CLK 2 4 4 Serial Clock
DI 3 3 5 Data In
DO 4 1 6 Data Out
VSS 5 2 7 Ground
ORG/NC 6 N/A 8 Organization / 93XX66C
No Internal Connection / 93XX66A/B
NC 7 N/A 1 No Internal Connection
VCC 8 6 2 Power Supply

3.1 Chip Select (CS) data bits before an instruction is executed. CLK and DI
then become “don’t care” inputs waiting for a new Start
A high level selects the device; a low level deselects condition to be detected.
the device and forces it into Standby mode. However, a
programming cycle which is already in progress will be
3.3 Data In (DI)
completed, regardless of the Chip Select (CS) input
signal. If CS is brought low during a program cycle, the Data In (DI) is used to clock in a Start bit, opcode,
device will go into Standby mode as soon as the address and data synchronously with the CLK input.
programming cycle is completed.
CS must be low for 250 ns minimum (TCSL) between 3.4 Data Out (DO)
consecutive instructions. If CS is low, the internal
Data Out (DO) is used in the Read mode to output data
control logic is held in a Reset status.
synchronously with the CLK input (TPD after the posi-
tive edge of CLK).
3.2 Serial Clock (CLK)
This pin also provides Ready/Busy status information
The Serial Clock is used to synchronize the communi- during erase and write cycles. Ready/Busy status infor-
cation between a master device and the 93XX series mation is available on the DO pin if CS is brought high
device. Opcodes, address and data bits are clocked in after being low for minimum Chip Select Low Time
on the positive edge of CLK. Data bits are also clocked (TCSL) and an erase or write operation has been
out on the positive edge of CLK. initiated.
CLK can be stopped anywhere in the transmission The Status signal is not available on DO, if CS is held
sequence (at high or low level) and can be continued low during the entire erase or write cycle. In this case,
anytime with respect to Clock High Time (TCKH) and DO is in the High-Z mode. If status is checked after the
Clock Low Time (TCKL). This gives the controlling erase/write cycle, the data line will be high to indicate
master freedom in preparing opcode, address and the device is ready.
data.
Note: Issuing a Start bit and then taking CS low
CLK is a “don’t care” if CS is low (device deselected). If will clear the Ready/Busy status from DO.
CS is high, but the Start condition has not been
detected (DI = 0), any number of clock cycles can be 3.5 Organization (ORG)
received by the device without changing its status (i.e.,
waiting for a Start condition). When the ORG pin is connected to VCC or Logic HI, the
(x16) memory organization is selected. When the ORG
CLK cycles are not required during the self-timed write
pin is tied to VSS or Logic LO, the (x8) memory
(i.e., auto erase/write) cycle.
organization is selected. For proper operation, ORG
After detection of a Start condition the specified number must be tied to a valid logic level.
of clock cycles (respectively low-to-high transitions of
93XX66A devices are always (x8) organization and
CLK) must be provided. These clock cycles are
93XX66B devices are always (x16) organization.
required to clock in all required opcode, address and

DS21795D-page 12 © 2008 Microchip Technology Inc.

 93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
4.0 PACKAGING INFORMATION

4.1 Package Marking Information

8-Lead MSOP (150 mil) Example:

XXXXXXT 3L66BI
YWWNNN 5281L7

6-Lead SOT-23 Example:

XXNN 3EL7

8-Lead PDIP Example:

XXXXXXXX 93LC66B
T/XXXNNN I/P e3 1L7
YYWW 0528

8-Lead SOIC Example:

XXXXXXXT 93LC66BI
XXXXYYWW SN e3 0528
NNN 1L7

8-Lead TSSOP Example:

XXXX L66B
TYWW I528
NNN 1L7

8-Lead 2x3 DFN Example:

XXX 374
YWW 528
NN L7

© 2008 Microchip Technology Inc. DS21795D-page 13

93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C

1st Line Marking Codes

Part Number SOT-23 DFN
TSSOP MSOP
I Temp. E Temp. I Temp. E Temp.
93AA66A A66A 3A66AT 3BNN — 361 —
93AA66B A66B 3A66BT 3LNN — 371 —
93AA66C A66C 3A66CT — — 381 —
93LC66A L66A 3L66AT 3ENN 3FNN 364 365
93LC66B L66B 3L66BT 3PNN 3RNN 374 375
93LC66C L66C 3L66CT — — 384 385
93C66A C66A 3C66AT 3HNN 3JNN 367 368
93C66B C66B 3C66BT 3TNN 3UNN 377 378
93C66C C66C 3C66CT — — 387 388
Note: T = Temperature grade (I, E)
NN = Alphanumeric traceability code

Legend: XX...X Part number or part number code

T Temperature (I, E)
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code (2 characters for small packages)
e3 Pb-free JEDEC designator for Matte Tin (Sn)

Note: For very small packages with no room for the Pb-free JEDEC designator
e3 , the marking will only appear on the outer carton or reel label.

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

DS21795D-page 14 © 2008 Microchip Technology Inc.

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DS21795D-page 16 © 2008 Microchip Technology Inc.

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DS21795D-page 18 © 2008 Microchip Technology Inc.

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DS21795D-page 20 © 2008 Microchip Technology Inc.

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