M o re Standard Gotchas

Subtleties in the Verilog and SystemVerilog

Standards That Every Engineer Should Know!

Stuart Sutherland Don Mills Chris Spear

Sutherland HDL, Inc. LCDM Engineering Synopsys, Inc.
Portland, Oregon Chandler, Arizona Marlboro, Massachusetts
[email protected] [email protected] [email protected]
 Stu Sutherland
Sutherland HDL

Presentation Overview Don Mills

LCDM Engineering

Chris Spear
Synopsys

‰ What is a “gotcha”?
‰ Why do standards have gotchas?

‰ What’s covered in this paper

‰ Several example gotchas,

and how to avoid them!

‰ Summary

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 Stu Sutherland
Sutherland HDL

What Is A Gotcha? Don Mills

LCDM Engineering

Chris Spear
Synopsys

ƒ In programming, a “gotcha” is a legal language construct that

does not do what the designer expects
A Classic C programming Gotcha...
Gotcha! If
If middle
middle of
of the
the month,
month, then
then pay
pay employees…
employees…
if (day = 15)
/* process payroll */ GOTCHA!
GOTCHA! This
This code
code will
will assign
assign the
the value
value of
of 15
15 to
to
day,
day, and
and then
then if
if day
day is
is not
not zero,
zero, pay
pay the
the employees
employees
if (day = = 15) ...

ƒ In hardware design and verification, most gotchas will simulate,

but give undesired results
ƒ Gotchas can be difficult to find and debug
ƒ A gotcha can be disastrous if not found before tape-out!
Engineers need to know how to recognize and
avoid gotchas in hardware modeling!
3 of 18
 Stu Sutherland
Why Do Sutherland HDL
Don Mills

Standards Have Gotchas?

LCDM Engineering

Chris Spear
Synopsys

ƒ Standards developers are idiots

ƒ Users of standards are idiots
ƒ Languages can be used the right way, or the wrong way
if (day = 15) Gotcha! A
A dumb
dumb way
way to
to use
use “assignment
“assignment
/* process payroll */ within
within an
an expression”
expression”

while (data = fscanf(…)) A

A clever
clever way
way to
to use
use “assignment
“assignment
/* read in data until it is 0 */ within
within an
an expression”
expression”

ƒ Hardware models are not just simulated, they are synthesized,

analyzed, emulated, prototyped, formally proved, …
ƒ Each type of tool needs different information from the language
ƒ Verilog and SystemVerilog allow designers to
prove what will — and what will not — work correctly
ƒ Models that won't work correctly need to be legal syntax 4 of 18
 Stu Sutherland
Sutherland HDL

Is This a Verilog Gotcha? Don Mills

LCDM Engineering

Chris Spear
Synopsys

ƒ Is the classic C gotcha also a gotcha in Verilog?

always @(state) Legal or Illegal?
if (state = LOAD) Illegal! Verilog does not allow
...
assignment statements inside of expressions

ƒ What about in SystemVerilog?

ƒ SystemVerilog extends Verilog with more C and C++ features
always @(state) Legal or Illegal?
if (state = LOAD)
If you don’t know the answer, then
...
you really need to read this paper!
(We will answer this question at the end of
our presentation...)

5 of 18
 Stu Sutherland

Standard Gotcha's, Part One Sutherland HDL

Don Mills
LCDM Engineering

(SNUG-Boston 2006) Chris Spear

Synopsys

ƒ Detailed descriptions of 57 gotchas…and how to avoid them!

• Case sensitivity • Literal size mismatch in assignments • Operations in sensitivity lists
• Implicit net declarations • Z extension backward compatibility • Sequential blocks with begin...end
• Escaped identifiers in hierarchy paths • Filling vectors • Sequential blocks with partial reset
• Verification of dynamic data • Passing real types through ports • Blocking assigns in sequential blocks
• Variables declared in unnamed blocks • Port connection rules • Evaluation of true/false on 4-state values
• Hierarchical references to package items • Back-driven input ports • Not operator versus invert operator
• Variables not dumped to VCD files • Self- & context-determined operations • Nested if...else blocks
• Shared variables in modules • Operation size and sign extension • Casez/casex masks in case expressions
• Shared variables in interfaces, packages • Signed math operations • Incomplete or redundant decisions
• Shared variables in tasks and functions • Bit and part select operations • Out-of-bounds in enumerated types
• Importing enum types from packages • Increment and decrement operations • Statements that hide design problems
• Importing from multiple packages • Pre-increment versus post-increment • Simulation versus synthesis mismatches
• Resetting 2-state models • Multiple read/writes in one statement • Multiple levels of same virtual method
• Locked state machines • Operator evaluation short circuiting • Event trigger race conditions
• Hidden design problems • Assignments in expressions • Using semaphores for synchronization
• Out-of-bounds indication lost • Procedural block activation • Using mailboxes for synchronization
• Signed versus unsigned literal integers • Combinational logic sensitivity lists • Coverage reporting
• Default base of literal integers • Arrays in sensitivity lists • $unit declarations
• Size mismatch in literal integers • Vectors in sensitivity lists • Compiling $unit
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 Stu Sutherland

Standard Gotcha's, Part Two Sutherland HDL

Don Mills
LCDM Engineering

(SNUG-San Jose 2007) Chris Spear

Synopsys

ƒ 38 additional gotchas…and how to avoid them!

• Overlapped decision statements • Summing a subset of an array • Coverage is always 0%
• Full_case or unique case • Task/function arguments • Coverage report results
synthesis gotcha with defaults get lumped together
• Combinational logic hidden storage • Static task/function gotcha • Covergroup directions that
• Nonblocking assignments • Local variables error are not what they seem
in comb. logic • Program statements in classes • Assertion pass statements
• Memory models that can't be loaded execute at wrong time
• Using interfaces with classes
• Default of 1-bit internal nets • Assertion fail statements
• Mailboxes that forget
• Port direction coercion execute at wrong time
stored values
• Compile errors with clocking blocks • Procedural assertion gotcha
• Passing handles to functions
• Misplaced semicolons on begin...end • Default time units
• Creating arrays of objects
• Misplaced semicolons in if...else • Package chaining
• Some variables won't randomize
• Misplaced semicolons in loops • Non-standard keywords
• Boolean randomization constraints
• Unintentional infintite loops that do weird things • Array literals versus
concatenations
• Locked simulation with • Undectected randomization
concurrent loops failures • Declaring floating point ports
• Using loop variables outside the loop • Unwanted negative random values
(The
(The highlighted
highlighted gotchas
gotchas are
are the
the ones
ones we
we will
will discuss
discuss in
in this
this presentation)
presentation) 7 of 18
 Stu Sutherland
A Synthesis Gotcha: Defaults Sutherland HDL
Don Mills

with Full_case or Unique Case

LCDM Engineering

Chris Spear
Synopsys

ƒ Default assignments before a case statement simplifies code

ƒ Using full_case or unique case can avoid unintended latches
ƒ But… combining the two styles is a gotcha!
always_comb begin
load_s = 1'b0; default
default values
values for
for
load_f = 1'b0; combinational
combinational outputs
outputs
load_pc = 1'b0; (could
(could be
be several
several dozen
dozen outputs)
outputs)
inc_pc = 1'b0;
set_br = 1'b0; DC
DC treats
treats aa full_case
full_case oror unique
unique case
case
dmem_rdN = 1'b0; Gotcha! statement
statement as as fully
fully self-contained
self-contained
dmem_wrN = 1'b0;
(any
(any assignments
assignments to to the
the same
same variables
variables
case (state) // synopsys full_case
before
before the
the case
case statement
statement areare ignored!)
ignored!)
state1 : inc_pc = 1'b1;
state2 : set_br = 1'b1;
...
only
only values
values different
different than
than default
default
endcase are
are listed
listed in
in case
case statement
statement
end (could
(could be
be dozens
dozens of
of branches)
branches)

ƒ To avoid this Gotcha… Don't mix default assignments with

full_case or unique case decisions 8 of 18
 Stu Sutherland
Gotcha: Sutherland HDL
Don Mills

Unintentional Infinite Loops

LCDM Engineering

Chris Spear
Synopsys

ƒ For-loops typically exit when a control variable exceeds some limit

ƒ But…it is possible to declare variables that cannot hold the
loop exit value
Why doesn't my test
integer sb[0:15]; ever finish?
reg [3:0] i;
initial begin
... // do lots of tests... Gotcha!
for (i=0; i<=15; i=i+1) begin
$display("sb[%0d]=%0d", i, sb[i]);
end
$finish;
end

ƒ To avoid this Gotcha…

ƒ Use the int type for for-loop control variable
ƒ Use SystemVerilog style for-loops for (int i=0; i<=15; i=i+1)
ƒ Makes the loop variable type more obvious 9 of 18
 Stu Sutherland
Gotcha: Using Loop Variables Sutherland HDL
Don Mills

Outside of the Loop

LCDM Engineering

Chris Spear
Synopsys

ƒ For-loop variables can be declared two different ways

ƒ Outside of the loop (Verilog style)
ƒ As part of the loop (SystemVerilog style)
ƒ But…it is a local variable that cannot be used outside the loop!
Verilog
Verilog Style
Style for
for Loop
Loop Variable
Variable SystemVerilog
SystemVerilog Style
Style for
for Loop
Loop Variable
Variable
integer a[0:31], b[0:31]; integer a[0:31], b[0:31];
int i; initial begin
initial begin for (int i=0; i<=31; i++) begin
for (i=0; i<=31; i=i+1) begin if (a[i] != b[i]) break;
if (a[i] != b[i]) break; end
end if (i < 32) Gotcha!
if (i < 32) $display("Mismatch at %0d", i);
$display("Mismatch at %0d", i); end
end Variables
Variables declared
declared as
as part
part of
of the
the
for-loop
for-loop are
are local
local to
to just
just the
the loop
loop
ƒ To avoid this Gotcha…
ƒ When the loop control variable needs to be used outside of the
loop, use the Verilog style of loop control variable 10 of 18
 Stu Sutherland
Gotcha: Using Programming Sutherland HDL
Don Mills

Statements in Classes
LCDM Engineering

Chris Spear
Synopsys

ƒ Classes enable writing Object Oriented re-usable testbenches

ƒ But…classes cannot directly execute programming statements
ƒ Classes contain "methods" that are called from procedural code
Definition
Definition of
of an
an object
object Definition
Definition of
of another
another object
object
class Foo; class Bar;
int data; Foo f = new; Instantiate
Instantiate object
object Foo
Foo
function int get (...); f.data = 3; and
and initialize
initialize it's
it's data
data
... endclass
endfunction Gotcha!
task put (...);
... A
A class
class cannot
cannot directly
directly execute
execute
endtask
endclass programming
programming statements
statements

ƒ To avoid this Gotcha…

ƒ See the next slide
11 of 18
 Stu Sutherland
Using Programming Statements Sutherland HDL
Don Mills

in Classes (continued)
LCDM Engineering

Chris Spear
Synopsys

ƒ Classes enable writing Object Oriented re-usable testbenches

ƒ But…classes cannot directly execute programming statements
ƒ To avoid this Gotcha…
ƒ Use "methods" to hold class programming statements
ƒ The new method can be used to initialize class variables
Definition
Definition of
of an
an object
object Definition
Definition of
of another
another object
object
class Foo; class Bar;
int data; Foo f = new(3);
function new (int d); The
The assignment
assignment f.data = 3;
this.data = d; statement
statement isis endclass
Initialize
Initialize Foo's
Foo's data
data
endfunction in
in aa method
method
using
using its
its new
new method
method
function int get (...); instead
instead of of executing
executing aa
...
programming
programming
endfunction
statement!
statement!
task put (...);
...
endtask
endclass
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 Stu Sutherland
Gotcha: Randomization Sutherland HDL
Don Mills

Constraints That Don't Work

LCDM Engineering

Chris Spear
Synopsys

ƒ Constraints are used to set limits on randomly generated values

ƒ But…multiple Boolean constraints may limit values differently
than intended Intent:
Intent: Constrain
Constrain values
values such
such
that lo is
that lo is less
less than med,, and
than med and
class bad1;
rand bit [7:0] lo, med, hi; med is
med is less
less than
than hi
hi
constraint increasing { lo < med < hi; }
endclass Gotcha!

Sample
Sample of
of values
values generated:
generated: Why is med greater than hi?
lo
lo == 20,
20, med
med == 224,
224, hi
hi == 164
164
lo == 114, Why is lo greater than med?
lo 114, med
med == 39,
39, hi
hi == 189
189
lo
lo == 186,
186, med
med == 148,
148, hi
hi == 161
161 Constrains hi to
Constrains hi to be
be greater
greater than
than result
result
of
of true/false
true/false test
test of
of "lo
"lo << med"
med"
•• lo
lo and med are
and med are not
not constrained
constrained
ƒ To avoid this Gotcha… •• Result
Result of
of true/false
true/false test
test is
is 00 or
or 11
ƒ Constraints involving multiple constraint increasing {
Boolean operations should be lo < med;
broken into multiple statements med < hi; }
13 of 18
 Stu Sutherland
Gotcha: Assertion Pass Statements Sutherland HDL
Don Mills

Execute at the Wrong Time

LCDM Engineering

Chris Spear
Synopsys

ƒ SystemVerilog Assertions can execute an optional "pass

statement" whenever the assertion succeeds
[ name : ] assert property ( property_specification ) [ pass_statement ] [ else fail_statement ] ;

property p_req_ack; •• IfIf req

req then
then check
check for ack on
for ack on next
next clock
clock cycle
cycle
@(posedge clk) req |-> ##1 ack;
•• IfIf no req then
no req then abort
abort with
with "vacuous
"vacuous success"
success"
endproperty
Intent:
Intent: Count
Count how
how many
many
assert property (p_req_ack) req_ack_count++; times req is
times req is followed
followed by
by ack
ack

Gotcha! Counts
Counts how
how many
many times req is
times req is followed
followed by
by ack
ack
and
and how
how many
many times
times there
there was
was no
no req
req

ƒ But…pass statements execute on both Success and Vacuous

Success
ƒ To avoid this Gotcha…
ƒ The next version of SystemVerilog will have a control to only
execute pass statements on success 14 of 18
 Stu Sutherland
Gotcha: Assertion Fail Statements Sutherland HDL
Don Mills

Execute at the Wrong Time

LCDM Engineering

Chris Spear
Synopsys

ƒ SystemVerilog Assertions can execute an optional "fail statement"

whenever the assertion fails
[ name : ] assert property ( property_specification ) [ pass_statement ] [ else fail_statement ] ;

property p_req_ack; Intent:

Intent:
@(posedge clk) req |-> ##1 ack; •• Increment
Increment counter
counter ifif assertion
assertion passes
passes and
and
endproperty cnt_en is
cnt_en is true
true
•• Exit
Exit with
with fatal
fatal error
error ifif assertion
assertion fails
fails
assert property (p_req_ack)
if (cnt_en) req_ack_count++; Pass statement
else $fatal; Fail statement? Gotcha!

The else is
The else is paired
paired with
with the if,, instead
the if instead of
of the
the assert
assert

ƒ But…the assertion else can be inadvertantly paired with an if

statement that is part of the pass statement
ƒ To avoid this Gotcha…
ƒ Add begin...end around the pass if statement
15 of 18
 Stu Sutherland
Gotcha: Sutherland HDL
Don Mills

Assignments in Expressions
LCDM Engineering

Chris Spear
Synopsys

ƒ Is the classic C gotcha also a gotcha in SystemVerilog?

always @(state)
if (state = LOAD) Legal or Illegal?
...

ƒ SystemVerilog allows assignments in expressions…

ƒ But,… the syntax is different than C — the assign statement must
be enclosed in parentheses
The
The different
different syntax
syntax helps
helps prevent
prevent the
the
always @(state)
gotcha
gotcha of
of using
using == where
where ==
== is
is intended,
intended, but…
but…
if ( (state = LOAD) )
... The different syntax is confusing to C/C++
Gotcha! programmers when an assignment is intended

ƒ To avoid this Gotcha…

ƒ “It is what it is” — Engineers need to learn the unique
SystemVerilog syntax
16 of 18
 Stu Sutherland
Sutherland HDL

Summary Don Mills

LCDM Engineering

Chris Spear
Synopsys

ƒ Programming languages have "gotchas"

ƒ A legal construct used in a way that gives unexpected results
ƒ Gotchas occur because useful language features can be abused
ƒ A gotcha in a hardware model can be disastrous
ƒ Difficult to find and debug
ƒ If not found before tape-out, can be very costly
ƒ This paper describes 38 Verilog and SystemVerilog gotchas
ƒ Detailed explanations of each gotcha
ƒ Guidelines on how to avoid each gotcha
ƒ Lots of code examples
ƒ This paper is Part 2
ƒ Part 1 was presented at SNUG-Boston 2006
17 of 18
 Stu Sutherland
Sutherland HDL

Questions & Answers… Don Mills

LCDM Engineering

Chris Spear
Synopsys

Do you have a favorite gotcha that is not in

the Part 1 or Part 2 paper?
Please send it to Stu or Don!
We are collecting gotchas for publication in a book...

[email protected] [email protected]

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