1

Brocade
Product Training
Module 6
Fibre Channel Arbitrated Loop
(FC-AL) Initialization
Brocade Education Services
© 2003 Brocade Communications Systems,
Incorporated.
 FC-AL Initialization 2

Learning Objectives

‹ Identify the FC-AL topology

‹ Describe how a FC-AL does initialization

Additional Notes
 FC-AL Initialization 3

Topics

‹ What is arbitrated loop

‹ Private vs. Public loops

‹ Valid AL_PAs

‹ Loop Initialization

‹ Show examples

Additional Notes
 Fibre Channel - Arbitrated Loop 4

What is it?

‹ A Fibre Channel topology

‹ Allows up to 127 participating node ports to communicate with each other

‹ Requires a port to successfully arbitrate prior to establishing a circuit to

send and/or receive frames

Fibre Channel supports three topologies:

1. Point-to-Point
2. Arbitrated Loop (FC-AL)
3. Switched Fabric

We will briefly review what FC-AL looks like before focusing on how a loop is initialized.
 5
Arbitrated Loop Topology

L_Port
‹ Transmit of one port Rx Tx
connects to receive of
next port

‹ Bandwidth is shared Tx Rx
among all the devices in
the loop L_Port L_Port

Rx Tx
‹ Only 2 devices may
communicate at a time
L_Port
Tx Rx

FC-AL was actually the third of the three topologies. It was developed to fill the gap between the
rather limited capabilities of point-to-point and the relatively expensive switched fabric.
The transmit and receive functions of each device are hooked together in a manner where a “loop” is
formed. All communications are passed around the loop. With up to 127 devices possible on a single
loop, the protocol requires a device must first arbitrate to win control of the loop before actual data
communication can take place. Once a device has control of the loop it can now select which device
on the loop with which it would like to “talk”.
Since only two devices can talk at a time the loop is a fully blocking topology. This means the rated
bandwidth is shared among the devices on the loop. As more devices are added to the loop the rated
bandwidth remains the same but each device essentially gets a smaller piece of it.
 Arbitrated Loop Topology 6

Types of Loops

‹ FC-AL provides configuration flexibility with two types of loops:

‹ Private

‹ Public

Additional Notes
 Arbitrated Loop Topology 7

Private Loop

NL_Port
‹ A loop with only
NL_Ports Rx Tx

‹ No external or public
access
Tx Rx

‹ Node ports are hosts NL_Port NL_Port

and storage
Rx Tx

Tx Rx

NL_Port

A private loop is a loop that allows communication to take place only between the devices on the
loop. There is no external or public access to the loop (no FL_Port).
 Arbitrated Loop Topology 8

Private Loop Example

NL
NL

NL

Hub
NL

NL
NL NL

This diagram shows an example of a private loop. Communication can occur only between the hosts
and storage on this loop. There is no external means to talk to any other devices.
Note: A hub has been added. It is there to provide for the integrity of the loop. The hub still makes
the connections to form a loop as described.
 Arbitrated Loop Topology 9

Public Loop

NL_Port
‹ A loop that has a
Rx
participating FL_port
Tx Tx

‹ Only one FL_Port may NL_Port

participate
Rx Rx

‹ The Fabric port is on a NL_Port

switch
Tx Tx

FL_Port
NL_Port
Rx Rx
Tx

A public loop is a loop that contains an active FL_Port. It is called public because devices on the
loop can communicate with the devices outside the loop. It also allows for devices outside the loop
to communicate to devices on the loop. This communication is possible because of the FL_Port. It
handles data flow into and out of the loop.
Because of the complexity of allowing an FL_Port to be part of a loop, only one FL_Port can
participate. If two FL_Ports are connected to the same loop one becomes the active FL_Port and the
other becomes nonparticipating. Should the active FL_Port fail, the nonparticipating port will
become the active.
Since the FL_Port takes an AL_PA (and is always ’00’), a public loop can only contain up to 126
devices.
 Arbitrated Loop Topology 10

Public Loop Example

Switch NL
NL

F F FL
NL

Hub
N N
NL

NL
NL NL

This diagram shows an example of a public loop.

Communication can take place between:
1. Devices on the loop.
2. A device on the loop and a device attached to the switch. (A host on the loop could access data
from the fabric attached storage.)
3. A device attached to the switch and a device on the loop. (The fabric attached host could write
data to the storage on the loop.)
 Arbitrated Loop Physical Address 11

AL_PA

‹ An 8-bit address assigned to each device in the loop

‹ Maximum of 127 AL_PAs

‹ These 127 are a unique set out of the possible 256 bit-patterns

‹ Lower the AL_PA, higher the priority

Arbitrated Loop uses 8 bits to identify each of the devices on a loop. This is the Physical Address for
the device and is known as the AL_PA. The protocol allows for 127 devices, so 127 unique AL_PAs
need to exist.
Using certain bit combinations can create disparity errors so the 127 AL_PAs available for the
NL_Ports are a fixed set. The next slide shows the valid AL_PA table.
Not all AL_PAs are created equal. In arbitrating for control of the loop, the device with the highest
priority wins. The lower the AL_PA assigned the higher the priority for the device on the loop.
 12
Valid AL_PAs

00 10 80 90 E0
01 31 51 71 81 B1 D1 E1
Highest 02 32 52 72 82 B2 D2 E2
priority 23 33 43 53 63 73 A3 B3 C3 D3
04 34 54 74 84 B4 D4 E4
25 35 45 55 65 75 A5 B5 C5 D5
26 36 46 56 66 76 A6 B6 C6 D6
17 27 47 67 97 A7 C7
08 18 88 98 E8
29 39 49 59 69 79 A9 B9 C9 D9
2A 3A 4A 5A 6A 7A AA BA CA DA
1B 2B 4B 6B 9B AB CB
2C 3C 4C 5C 6C 7C AC BC CC DC Lowest
1D 2D 4D 6D 9D AD CD priority
1E 2E 4E 6E 9E AE CE
0F 1F 8F 9F EF

The 8-bit addresses not shown in this table will never be used as an AL_PA for a device on the loop
(03, 05, 06, etc).
The AL_PA for the FL_Port on a public loop will always be ’00’.
 Loop Initialization 13

What can cause it?

‹ Power On / Power On Reset

‹ Enter/Leave participating mode

‹ Loop failure

‹ Arbitration Wait timeout

‹ Selective Reset LIP

Power On / Power On Reset

Loop Initialization occurs when a port is powered on or was given an equivalent reset.
Enter/Leave Participating Mode
A port in nonparticipating mode may after a dependent timeout attempt to become a participating
port. If the port is successful in obtaining an AL_PA it can participate in loop operations after
initialization completes. If the port is unsuccessful it remains in nonparticipating mode.
A port already in participating mode can change to nonparticipating mode. It gives up the AL_PA it
was assigned and makes it available for other ports to acquire.
Loop Failure
This may have occurred due to a port on the loop failing, being powered off, or a physical
connection in the loop is broken.
Arbitration Wait Timeout
Excessive unfairness or a hung port may cause a port to not win arbitration. The port may use loop
initialization to clear this condition.
Selective reset LIP
Causes the ports on the loop to do a vendor unique reset. Usually, this is equivalent to a power on
reset.
 Loop Initialization 14

What happens?

‹ Loop initialization begins by a port transmitting LIPs

‹ All loop activity is suspended

‹ All ports enter the Open-Initializing state

‹ One port is selected as Master

‹ Ports are assigned an AL_PA

‹ Positional AL_PA map of loop is built (if supported)

‹ All ports return to Monitoring state

‹ Normal loop operations resume

The Loop Initialization Primitive (LIP) is used to begin the process and suspend any activities if the
loop is currently active. Receiving ports recognize the loop initialization process when at least three
consecutive LIPs are received. The port enters the Open-Init state and continues to retransmit the
LIPs to the next port on the loop.
Once all the ports are in the Open-Init state, a series of frames are passed around the loop to
determine a loop master, assign an AL_PA to each device on the loop and report the position of each
device (optional).
The loop returns to the monitoring state and normal loop operations can resume.
 Loop Initialization 15

Sequence of events

‹ LIPs (Loop Initialization Primitive Sequence)

‹ LISM ( … Select Master)

‹ LIFA ( … Fabric Assigned)

‹ LIPA ( … Previous Assigned)
‹ LIHA ( … Hardware Assigned)
‹ LISA ( … Software Assigned)

‹ LIRP ( … Report Position (if supported))

‹ LILP ( … Loop Position (if supported))

‹ CLS (Close)
‹ Initialization is complete !

LIP and CLS are Ordered Sets used to indicate states or events. Ordered Sets are special four-
character combinations that have special meaning in Fibre Channel.
A LIP is a Primitive Sequence Ordered Set. Primitive Sequences are used to indicate states or
conditions and are normally transmitted continuously until something causes the current state to
change.
CLS is a Primitive Signal Ordered Set. Primitive Signals are used to indicate events or actions and
are normally transmitted once.
LISM is a frame that each device enters on the loop. It will determine the device that becomes the
loop master. This port controls the rest of the loop initialization process.
LIFA, LIPA, LIHA, LISA are frames passed around the loop for devices to have their AL_PA
assigned.
LIRP and LILP are also frames that are passed around the loop but are used to allow the reporting of
the position of the device on the loop. This is an optional step in the loop initialization process. It
allows any device to learn not only the AL_PA of all the devices but the order in which they occur
on the loop.
 Loop Initialization 16

Examples

‹ Let’s look at two events that cause Loop Initialization:

‹A switch is powered on

‹A device is added to an operational loop

Additional Notes
 Loop Initialization 17

Switch is powered ON
“ON”

FL

NL
NL

NL
FC-AL

NL
NL

The devices above are on a public loop and the switch is powered on for the first time.
 Loop Initialization 18

LIPs – Loop Initialization Primitive Sequence

‹ One of the Ordered Sets (4 bytes)

‹ FL_Port sends continuously to signal loop initialization

‹ Receiving port recognizes when it detects three consecutive LIPs

‹ Port enters Open-Init state and retransmits LIPs to next port

‹ Continues until FL_Port receives three consecutive LIPs

‹ All ports are now in Open-Init state

‹ Normal loop operations are suspended

The first step in loop initialization is to notify all the ports on the loop that this process has begun.
The ports must first be put in an Open-Init state. It tells each port to suspend any operations that may
currently be going on and prepare for loop initialization.
 Loop Initialization 19

LIPs issued by Switch

FL LIP

NL
LIP
NL
LIP
NL

FC-AL

NL
NL

Since the FL_Port was the changing port due to the power on of the switch, it transmits at least 12
LIPs onto the loop. The FL_port is now waiting for at least three consecutive LIPs to come around
and be seen on its receive side.
 Loop Initialization 20

LIPs received by next port and retransmitted

FL

NL
Open-Init
NL state
LIP
NL LIP

FC-AL LIP

LIP

NL
NL

When a port detects three consecutive LIPs on its receive side, it suspends any current operations,
enters the Open-Init state and transmits at least 12 LIPs of the same type as received to the next port
on the loop.
 Loop Initialization 21

LIPs received and retransmitted around the Loop

Open-Init
state
FL
Open-Init
state NL LIP
Open-Init
NL state
NL
Open-Init
state
FC-AL
LIP

NL Open-Init
Open-Init NL
state
state LIP LIP

This process continues until the FL_Port receives three consecutive LIPs. At this point any
operations on the loop that may have been active are suspended and all ports are in the Open-Init
state.
Notice this process involves multiple LIPs moving around the loop until three reach the originating
port (the FL_Port in this example).
 Loop Initialization 22

Frame Format
H Word 0 R_CTL D_ID
E
Word 1 CS_CTL S_ID
A
D Word 2 TYPE F_CTL
E
Word 3 SEQ_ID DF_CTL SEQ_CNT
R
Word 4 OX_ID RX_ID
Word 5 Parameter or Relative Offset
P Word 6 Loop Initialization ID
A
Word 7
Y
L Word 8
O
Word 9
A
D Word 10

Frames will be used to pass around the loop for the next phase of loop initialization. The format of a
frame is (excludes SOF,CRC, EOF):

HEADER:
R_CTL Routing Control
D_ID Destination ID
CS_CTL Class Specific Control
S_ID Source ID
TYPE Data Structure Type
F_CTL Frame Control
SEQ_ID Sequence ID
DF_CTL Data Field Control
SEQ_CNT Sequence Count
OX_ID Originator ID
RX_ID Responder ID

PAYLOAD:
Loop Initialization ID
 Loop Initialization 23

LISM Frame – Select Master

‹ Loop Initialization Id (Frame Word 6) set to 11010000

‹ All L_Ports enter a LISM on the loop with their Port WWN

‹ The FL_Port sets AL_PA to 00

‹ The NL_Ports set AL_PA to EF

‹ Each L_Port monitors frames received

The first word of the payload is used to identify the type of frame being passed around the loop. The
LISM frame is 11010000. All ports enter a single LISM frame onto the loop with their Port World
Wide Name (WWN). The FL_Port sets the AL_PA in the source (S_ID) and destination (D_ID) to
x’00’. All NL_Ports set theirs to x’EF’.
As each port receives a LISM frame rules apply as to what LISM frame will be transmitted.
 Loop Initialization 24

LISM Frame – Select Master (cont.)

‹ If NL_Port receives a frame from an FL_Port, it retransmits the FL_Port

frame

‹ If NL_Port receives a frame from another NL_Port, the Port WWNs are
compared:
‹ If received frame is higher, it is discarded and receiver’s frame is
retransmitted
‹ Otherwise, received frame is retransmitted

As each port receives a LISM frame the following rules apply as to what LISM frame will be
transmitted.

1. An NL_Port will retransmit any LISM frame from an FL_Port.

2. An NL_Port will discard the LISM frame from another NL_Port and retransmit its own LISM
frame if the received Port’s WWN is higher. If it is lower it retransmits the received frame.
 Loop Initialization 25

LISM Frame – Select Master (cont.)

‹ If FL_Port receives a frame from an NL_Port, it is discarded and it

retransmits its own frame

‹ If FL_Port receives a frame from an FL_Port, the Port WWNs are

compared:
‹ If received frame is lower, there are multiple FL_Ports on the loop, this
one must enter nonparticipating mode and continue to retransmit all
received frames

‹ If received frame is higher, there are multiple FL_Ports on the loop, the
frame is discarded and it retransmits its own frame

‹ If received frame is equal, the FL_Port has received it’s own frame and
wins loop initialization master!

3. An FL_Port will discard any LISM frame received from an NL_Port and retransmit its own LISM
frame.

4. An FL_Port expects to receive the LISM frame it put on the loop since a public loop can only
have one FL_Port. If multiple FL_Ports are on the loop, the FL_Port with the lowest WWN will have
its LISM frame passed around the loop and thus become the loop master. Any other FL_Ports must
go into a nonparticipating mode and continue to retransmit frames received.
 Loop Initialization 26

LISM Frame
00 = FL_Port, EF = NL_Port

H Word 0 22 0000XX
E Word 1 00 0000XX
A
Word 2 01 380000
D
E Word 3 00 00 0000
R Word 4 FFFF FFFF
Word 5 00000000
PAY
Word 6 11010000
L
O
Word 7 Port_Name (8 bytes)
A
D
Word 8

Port World Wide Name (WWN)

Loop Initialization Id = 11010000

Port_Name = Port World Wide Name

For FL_Port:
D_ID = 000000
S_ID = 000000

For NL_Ports:
D_ID = 0000EF
S_ID = 0000EF
 Loop Initialization 27

LISM Fames entered

WWN=20070060691a5d79
LISM AL_PA=EF
WWN=21…3f8b44
FL LISM AL_PA=00
WWN=21…3f8b44 WWN=20…1a5d79
NL
LISM AL_PA=EF NL WWN=10…1e2c11
WWN=21…3f8b55
NL
LISM AL_PA=EF
FC-AL WWN=10…1e2c11
WWN=21…3f8b55

LISM AL_PA=EF
WWN=10…1e2c22
NL
NL WWN=21…3f8b33

WWN=10…1e2c22
LISM AL_PA=EF
WWN=21…3f8b33

This is the LISM frame that each port enters onto the loop.
 Loop Initialization 28

LISM Fames pass around

WWN=20070060691a5d79
LISM AL_PA=EF
WWN=21…3f8b44
FL LISM AL_PA=00
WWN=21…3f8b44 WWN=20…1a5d79
NL
LISM AL_PA=EF NL WWN=10…1e2c11
WWN=10…1e2c22
NL
LISM AL_PA=00
FC-AL WWN=20…1a5d79
WWN=21…3f8b55

LISM AL_PA=EF
WWN=10…1e2c22
NL
NL WWN=21…3f8b33

WWN=10…1e2c22
LISM AL_PA=EF
WWN=10…1e2c11

Each LISM frame is received by the next port on the loop. The rules previously described determine
what LISM frame is transmitted. For identification purposes, starting with the first NL_Port and
moving clockwise: NL1, NL2, NL3, NL4, NL5, FL1.
F
r
F
a
r
m
a
e
m
T
A e
P r
L W R
O a
_ W e
R n
P N c
T s
A e
m
i
i
v
t
e
A t
A
d
L e
L
_ d
_
P P
1 A A
0 = =
… 0 0
N 1 0 0
E
L e 2 2
F
1 2 0 0
c
 Loop Initialization 29

LISM Fames pass around (cont.)

WWN=20070060691a5d79
LISM AL_PA=EF
WWN=10…1e2c22
FL LISM AL_PA=00
WWN=21…3f8b44 WWN=20…1a5d79
NL
LISM AL_PA=EF NL WWN=10…1e2c11
WWN=10…1e2c22
NL
LISM AL_PA=00
FC-AL WWN=20…1a5d79
WWN=21…3f8b55

LISM AL_PA=EF
WWN=10…1e2c11
NL
NL WWN=21…3f8b33

WWN=10…1e2c22
LISM AL_PA=00
WWN=20…1a5d79

The LISM frames continue to pass around the loop.

F
r
F
a
r
m
a
e
m
T
A e
P r
L W R
O a
_ W e
R n
P N c
T s
A e
m
i
i
v
t
e
A tA
d
L e
L
_ d
_
P P
1 A A
0 = =
… 0 0
N 1 0 0
E
L e 2 2
F
1 2 0 0
c … …
1 1 1
 Loop Initialization 30

LISM Fames pass around (cont.)

WWN=20070060691a5d79
LISM AL_PA=EF
WWN=10…1e2c22
FL LISM AL_PA=00
WWN=21…3f8b44 WWN=20…1a5d79
NL
LISM AL_PA=EF NL WWN=10…1e2c11
WWN=10…1e2c11
NL
LISM AL_PA=00
FC-AL WWN=20…1a5d79
WWN=21…3f8b55

LISM AL_PA=00
WWN=20…1a5d79
NL
NL WWN=21…3f8b33

WWN=10…1e2c22
LISM AL_PA=00
WWN=20…1a5d79

Additional Notes
 Loop Initialization 31

LISM Fames pass around (cont.)

WWN=20070060691a5d79
LISM AL_PA=EF
WWN=10…1e2c11
FL LISM AL_PA=00
WWN=21…3f8b44 WWN=20…1a5d79
NL
LISM AL_PA=00 NL WWN=10…1e2c11
WWN=20…1a5d79
NL
LISM AL_PA=00
FC-AL WWN=20…1a5d79
WWN=21…3f8b55

LISM AL_PA=00
WWN=20…1a5d79
NL
NL WWN=21…3f8b33

WWN=10…1e2c22
LISM AL_PA=00
WWN=20…1a5d79

Additional Notes
 Loop Initialization 32

LISM Fames pass around (cont.)

WWN=20070060691a5d79
LISM AL_PA=00
WWN=20…1a5d79
FL LISM AL_PA=00
WWN=21…3f8b44 WWN=20…1a5d79
NL
LISM AL_PA=00 NL WWN=10…1e2c11
WWN=20…1a5d79
NL
LISM AL_PA=00
FC-AL WWN=20…1a5d79
WWN=21…3f8b55

LISM AL_PA=00
WWN=20…1a5d79
NL
NL WWN=21…3f8b33

WWN=10…1e2c22
LISM AL_PA=00
WWN=20…1a5d79

Additional Notes
 Loop Initialization 33

FL_Port receives its own LISM Frame

WWN=20070060691a5d79
LISM AL_PA=00
WWN=20…1a5d79
FL
WWN=21…3f8b44
NL
NL WWN=10…1e2c11

NL

FC-AL
WWN=21…3f8b55

NL
NL WWN=21…3f8b33

WWN=10…1e2c22

The LISM frames continue to pass around the loop. The FL_Port is the only port to receive the frame
it sent. It wins and becomes the Loop Master.

F
r
F
a
r
m
a
e
m
T
A e
P r
L W R
O a
_ W e
R n
P N c
T s
A e
m
i
i
v
t
e
A t
A
d
L e
L
_ d
_
P P
1 A A
0 = =
… 0 0
N 1 0 0
E
L e 2 2
F
1 2 0 0
c
 Loop Initialization 34

LIFA Frame – Fabric Assigned

‹ Sets Loop Initialization Id (Frame Word 6) to 11020000

‹ Sets AL_PA bit map to all zeros (Frame Words 7 – 10)

‹ Passes around the loop once

‹ Ports that have done a Fabric login (FLOGI) claim the same AL_PA in the
bit map (bit set to “1”)

This is the first step in assigning AL_PAs.

The 127 AL_PA bit map starts with all bits set to 0.
The LIFA frame is passed around the loop once.
Any port that had a fabric assigned address prior to loop initialization can reclaim the same AL_PA.
 Loop Initialization 35

LIFA Frame as it enters the Loop

H Word 0 22 000000
E Word 1 00 000000
A
Word 2 01 380000
D
Word 3 00 00 0000
E Bit 30 of
R Word 4 FFFF FFFF Word 7
Word 5 00000000 is AL_PA
00
P Word 6 11020000
A
Y Word 7 b’00000000000000000000000000000000’
L
Word 8 b’00000000000000000000000000000000’ Bit 0 of
O
Word 10
A Word 9 b’00000000000000000000000000000000’
is AL_PA
D
Word 10 b’00000000000000000000000000000000’ EF

Additional Notes
 AL_PA Bit Map 36

Word 7

W O R D 7
BYTE 0 BYTE 1 BYTE 2 BYTE 3
BIT AL_PA BIT AL_PA BIT AL_PA BIT AL_PA
31 L_bit 23 17 15 26 7 31
30 00 22 18 14 27 6 32
29 01 21 1B 13 29 5 33
28 02 20 1D 12 2A 4 34
27 04 19 1E 11 2B 3 35
26 08 18 1F 10 2C 2 36
25 0F 17 23 9 2D 1 39
24 10 16 25 8 2E 0 3A

Word 7, bit 31 (L_bit) is the “login required bit”. It will only be set by the FL_Port when the
configuration has changed and the ports are required to do a fabric login again. This would occur if
the first two bytes of the 24-bit address for the port have changed. Thus, if the Domain Id of the
switch or the Port Number of the FL_Port has changed, this bit would be set.
 AL_PA Bit Map 37

Word 8

W O R D 8
BYTE 0 BYTE 1 BYTE 2 BYTE 3
BIT AL_PA BIT AL_PA BIT AL_PA BIT AL_PA
31 3C 23 4C 15 56 7 69
30 43 22 4D 14 59 6 6A
29 45 21 4E 13 5A 5 6B
28 46 20 51 12 5C 4 6C
27 47 19 52 11 63 3 6D
26 49 18 53 10 65 2 6E
25 4A 17 54 9 66 1 71
24 4B 16 55 8 67 0 72

Additional Notes
 AL_PA Bit Map 38

Word 9

W O R D 9
BYTE 0 BYTE 1 BYTE 2 BYTE 3
BIT AL_PA BIT AL_PA BIT AL_PA BIT AL_PA
31 73 23 81 15 9B 7 A9
30 74 22 82 14 9D 6 AA
29 75 21 84 13 9E 5 AB
28 76 20 88 12 9F 4 AC
27 79 19 8F 11 A3 3 AD
26 7A 18 90 10 A5 2 AE
25 7C 17 97 9 A6 1 B1
24 80 16 98 8 A7 0 B2

Additional Notes
 AL_PA Bit Map 39

Word 10

W O R D 10
BYTE 0 BYTE 1 BYTE 2 BYTE 3
BIT AL_PA BIT AL_PA BIT AL_PA BIT AL_PA
31 B3 23 C5 15 CE 7 DA
30 B4 22 C6 14 D1 6 DC
29 B5 21 C7 13 D2 5 E0
28 B6 20 C9 12 D3 4 E1
27 B9 19 CA 11 D4 3 E2
26 BA 18 CB 10 D5 2 E4
25 BC 17 CC 9 D6 1 E8
24 C3 16 CD 8 D9 0 EF

Additional Notes
 Loop Initialization 40

LIFA Fame passed around the loop

LIFA FL LIFA

NL
NL
NL

FC-AL

NL
NL

A single LIFA frame gets passed around the loop once.

 Loop Initialization 41

LIFA Frame after passing around the Loop

H Word 0 22 000000
E Word 1 00 000000
A
Word 2 01 380000
D
Word 3 00 00 0000
E
R Word 4 FFFF FFFF
Word 5 00000000
P Word 6 11020000
A
Y Word 7 b’00000000000000000000000000000000’
L
Word 8 b’00000000000000000000000000000000’
O
A Word 9 b’00000000000000000000000000000000’
D
Word 10 b’00000000000000000000000000000000’

When initialization is due to a switch power on, no bits are set in the LIFA
frame since no ports have logged in yet

Additional Notes
 Loop Initialization 42

LIPA Frame – Previously Assigned

‹ Changes Loop Initialization Id (Frame Word 6) to 11030000

‹ Bit map remains as set by LIFA

‹ Passes around the loop once

‹ Ports that had a non-fabric assigned AL_PA prior to initialization claim the
same AL_PA in the bit map (bit set to “1”)

The received LIFA frame becomes the LIPA frame by changing the Id to 11030000. The bit map
remains as previously set by LIFA.
The LIPA frame passes around the loop once.
Any port that had an AL_PA prior to loop initialization and hadn’t done a fabric login can reclaim
the same AL_PA.
 Loop Initialization 43

LIPA Frame as it enters the Loop

H Word 0 22 000000
E Word 1 00 000000
A
Word 2 01 380000
D
Word 3 00 00 0000
E
R Word 4 FFFF FFFF
Word 5 00000000
P Word 6 11030000
A
Y Word 7 b’00000000000000000000000000000000’
L
Word 8 b’00000000000000000000000000000000’
O
A Word 9 b’00000000000000000000000000000000’
D
Word 10 b’00000000000000000000000000000000’

Additional Notes
 Loop Initialization 44

LIPA Fame passed around the loop

LIPA FL LIPA

NL
NL
NL

FC-AL

NL
NL

A single LIPA frame gets passed around the loop once.

 Loop Initialization 45

LIPA Frame after passing around the Loop

H Word 0 22 000000
E Word 1 00 000000
A
Word 2 01 380000
D
Word 3 00 00 0000
E
R Word 4 FFFF FFFF
Word 5 00000000
P Word 6 11030000
A
Y Word 7 b’00000000000000000000000000000000’
L
Word 8 b’00000000000000000000000000000000’
O
A Word 9 b’00000000000000000000000000000000’
D
Word 10 b’00000000000000000000000000000000’

When initialization is due to a switch power on, no bits are set in the LIPA
frame since this is the first initialization for the loop

Additional Notes
 Loop Initialization 46

LIHA Frame – Hard Assign

‹ Changes Loop Initialization Id (Frame Word 6) to 11040000

‹ Bit map remains as set by LIFA and LIPA

‹ Passes around the loop once

‹ Ports that have a preferred AL_PA (set by a switch, jumper, wiring, etc)
attempt to acquire that AL_PA in the bit map (bit set to “1”)

‹ If AL_PA already assigned, AL_PA is assigned during soft assign (LISA)

The received LIPA frame becomes the LIHA frame by changing the Id to 11040000. The bit map
remains as previously set by LIFA and LIPA.
The LIHA frame passes around the loop once.
Any port that did not have an AL_PA prior to loop initialization but has a preferred AL_PA set by
switches, jumpers, wiring, etc., can attempt to set that AL_PA.
If the AL_PA is already set, it will wait until the last step of soft assigned AL_PAs occurs.
 Loop Initialization 47

LIHA Frame as it enters the Loop

H Word 0 22 000000
E Word 1 00 000000
A
Word 2 01 380000
D
Word 3 00 00 0000
E
R Word 4 FFFF FFFF
Word 5 00000000
P Word 6 11040000
A
Y Word 7 b’00000000000000000000000000000000’
L
Word 8 b’00000000000000000000000000000000’
O
A Word 9 b’00000000000000000000000000000000’
D
Word 10 b’00000000000000000000000000000000’

Additional Notes
 Loop Initialization 48

LIHA Fame passed around the loop

Hard assign
‘D3’ LIHA FL LIHA

NL
NL
Hard assign
‘D2’ NL

FC-AL

Hard assign
NL ‘D1’
NL

A single LIHA frame gets passed around the loop once.

 Loop Initialization 49

LIHA Frame after passing around the Loop

H Word 0 22 000000
E Word 1 00 000000
A
Word 2 01 380000
D
Word 3 00 00 0000
E
R Word 4 FFFF FFFF
Word 5 00000000
P Word 6 11040000
A
Y Word 7 b’00000000000000000000000000000000’
L
Word 8 b’00000000000000000000000000000000’
O
A Word 9 b’00000000000000000000000000000000’
D
Word 10 b’00000000000000000111000000000000’

AL_PA ‘D1’, ‘D2’, ‘D3’ are set

Additional Notes
 Loop Initialization 50

LISA Frame – Soft Assign

‹ Changes Loop Initialization Id (Frame Word 6) to:

‹ 11050100 (Loop Master supports loop position mapping) or
‹ 11050000 (does not)

‹ Bit map remains as set by LIFA, LIPA and LIHA

‹ Passes around the loop once

‹ Ports that do not yet have an AL_PA assigned acquire the first available
AL_PA in the bit map

‹ Search order is from highest priority (AL_PA = 01) to lowest priority

(AL_PA = EF)

The received LIHA frame becomes the LISA frame by changing the Id to 11050000 or 11050100.
The bit map remains as previously set by LIFA, LIPA and LIHA.
The LISA frame passes around the loop once.
Ports without an AL_PA scan the bit map starting from the highest priority of AL_PA 01 and take
the first available address.
 Loop Initialization 51

LISA Frame (cont)

‹ If all AL_PAs are assigned, the port transmits the LISA frame and enters
nonparticipating mode

‹ Could occur if loop contains:

‹ more than 126 NL_Ports

‹ more than 1 FL_Port

‹ If port does not support loop position mapping, it sets byte 3 of Loop
Initialization ID to ’00’which causes Loop Master to bypass loop
position mapping frames

Additional Notes
 Loop Initialization 52

LISA Frame as it enters the Loop

H Word 0 22 000000
E Word 1 00 000000
A
Word 2 01 380000
D
Word 3 00 00 0000
E
R Word 4 FFFF FFFF
Word 5 00000000
P Word 6 11050100 or 11050000
A
Y Word 7 b’00000000000000000000000000000000’
L
Word 8 b’00000000000000000000000000000000’
O
A Word 9 b’00000000000000000000000000000000’
D
Word 10 b’00000000000000000111000000000000’

Additional Notes
 Loop Initialization 53

LISA Fame passed around the loop

Hard assign
‘D3’ LISA FL LISA
Soft assign
NL ‘01’

NL
Hard assign
‘D2’ NL

FC-AL

Hard assign
Soft assign
‘02’ NL ‘D1’
NL

A single LISA frame gets passed around the loop once.

 Loop Initialization 54

LISA Frame after passing around the Loop

H Word 0 22 000000
E Word 1 00 000000
A
Word 2 01 380000
D
Word 3 00 00 0000
E
R Word 4 FFFF FFFF
Word 5 00000000
P Word 6 11050100 or 11050000
A
Y Word 7 b’00110000000000000000000000000000’
L
Word 8 b’00000000000000000000000000000000’
O
A Word 9 b’00000000000000000000000000000000’
D
Word 10 b’00000000000000000111000000000000’

AL_PA ‘01’, ‘02’ are set

Additional Notes
 Loop Initialization 55

After the LISA Frame passes around

‹ Ports on the loop either:

‹ acquired a unique AL_PA or

‹ entered nonparticipating mode

‹ If Loop Initialization ID is 11050000:

‹ positional mapping is bypassed and

‹ CLS (close) is transmitted to end initialization

‹ If Loop Initialization ID is 11050100:

‹ positional mapping is performed

‹ uses LIRP and LILP frames

If any port on the loop does not support positional mapping, a Close Primitive Signal is transmitted
and loop initialization is ended.
If all ports support it, LIRP and LILP frames are passed around the loop.
 Loop Initialization 56

LIRP Frame – Report Position

‹ Sets Loop Initialization Id (Frame Word 6) to 11060000

‹ Map contains a 1-byte offset and 127 bytes for AL_PA positions

‹ Loop Master sets:

‹ Offset to ’01’

‹ Its own AL_PA at offset 1 to ’00’

‹ All remaining 126 positions to ‘FF’

‹ Passes around the loop once

The FL_Port starts by reporting its AL_PA which is always 00.

The remaining AL_PA positions are set to FF to make it easy to read the table once the positions
have reported.
The LIRP frame passes around the loop once.
 Loop Initialization 57

LIRP Frame as it passes around the Loop

‹ Each port:
‹ Increments the offset by 1

‹ Stores its AL_PA at that location in the map

‹ Nonparticipating ports just retransmit the frame

Each port sets its AL_PA and increments the offset. When the LIRP frame is received at the
FL_Port, the offset will be the number of ports on the loop and the map will contain the AL_PAs in
the order in which they occur on the loop.
Nonparticipating ports having nothing to report since they weren’t able to acquire an AL_PA. They
are still a port on the loop so they will just retransmit the frame to the next port.
 Loop Initialization 58

LIRP Frame as it enters the Loop

H Word 0 22 000000
E Word 1 00 000000
A
Word 2 01 380000
D
Word 3 00 00 0000
E
R Word 4 FFFF FFFF
Word 5 00000000
P Word 6 11060000
A Word 7 01 00 FF FF (1st byte is offset,
Y
Word 8 FF FF FF FF followed by
L
Word 9 FF FF FF FF 127 AL_PA entries)
O
A Word 10 FF FF FF FF
D ... FF FF FF FF
Word 38 FF FF FF FF

FL_Port is always AL_PA ‘00’

Additional Notes
 Loop Initialization 59

LIRP Fame passed around the loop

Hard assign
‘D3’ LIRP FL LIRP
Soft assign
NL ‘01’

NL
Hard assign
‘D2’ NL

FC-AL

Hard assign
Soft assign
‘02’ NL ‘D1’
NL

A single LIRP frame gets passed around the loop once.

 Loop Initialization 60

LIRP Frame after NL_Port 1

H Word 0 22 000000
E Word 1 00 000000
A
Word 2 01 380000
D
Word 3 00 00 0000
E
R Word 4 FFFF FFFF
Word 5 00000000
P Word 6 11060000
A Word 7 02 00 01 FF (1st byte is offset,
Y
Word 8 FF FF FF FF followed by
L
Word 9 FF FF FF FF 127 AL_PA entries)
O
A Word 10 FF FF FF FF
D ... FF FF FF FF
Word 38 FF FF FF FF

Additional Notes
 Loop Initialization 61

LIRP Frame after NL_Port 2

H Word 0 22 000000
E Word 1 00 000000
A
Word 2 01 380000
D
Word 3 00 00 0000
E
R Word 4 FFFF FFFF
Word 5 00000000
P Word 6 11060000
A Word 7 03 00 01 D1 (1st byte is offset,
Y
Word 8 FF FF FF FF followed by
L
Word 9 FF FF FF FF 127 AL_PA entries)
O
A Word 10 FF FF FF FF
D ... FF FF FF FF
Word 38 FF FF FF FF

Additional Notes
 Loop Initialization 62

LIRP Frame after NL_Port 3

H Word 0 22 000000
E Word 1 00 000000
A
Word 2 01 380000
D
Word 3 00 00 0000
E
R Word 4 FFFF FFFF
Word 5 00000000
P Word 6 11060000
A Word 7 04 00 01 D1 (1st byte is offset,
Y
Word 8 02 FF FF FF followed by
L
Word 9 FF FF FF FF 127 AL_PA entries)
O
A Word 10 FF FF FF FF
D ... FF FF FF FF
Word 38 FF FF FF FF

Additional Notes
 Loop Initialization 63

LIRP Frame after NL_Port 4

H Word 0 22 000000
E Word 1 00 000000
A
Word 2 01 380000
D
Word 3 00 00 0000
E
R Word 4 FFFF FFFF
Word 5 00000000
P Word 6 11060000
A Word 7 05 00 01 D1 (1st byte is offset,
Y
Word 8 02 D2 FF FF followed by
L
Word 9 FF FF FF FF 127 AL_PA entries)
O
A Word 10 FF FF FF FF
D ... FF FF FF FF
Word 38 FF FF FF FF

Additional Notes
 Loop Initialization 64

LIRP Frame after NL_Port 5

H Word 0 22 000000
E Word 1 00 000000
A
Word 2 01 380000
D
Word 3 00 00 0000
E
R Word 4 FFFF FFFF
Word 5 00000000
P Word 6 11060000
A Word 7 06 00 01 D1 (1st byte is offset,
Y
Word 8 02 D2 D3 FF followed by
L
Word 9 FF FF FF FF 127 AL_PA entries)
O
A Word 10 FF FF FF FF
D ... FF FF FF FF
Word 38 FF FF FF FF

Additional Notes
 Loop Initialization 65

LILP Frame – Loop Position

‹ Changes Loop Initialization Id (Frame Word 6) to 11070000

‹ Map positions remain as set by LIRP

‹ Passes around the loop once

‹ Allows interested ports to capture AL_PA positions

‹ Ports use as desired

The LIRP frame is changed to LILP by setting Id to 11070000.

The LILP frame passes around the loop once.
Any port on the loop is free to capture the positional map for whatever use it desires.
 Loop Initialization 66

LILP Frame as it enters the Loop

H Word 0 22 000000
E Word 1 00 000000
A
Word 2 01 380000
D
Word 3 00 00 0000
E
R Word 4 FFFF FFFF
Word 5 00000000
P Word 6 11070000
A Word 7 06 00 01 D1 (1st byte is offset,
Y
Word 8 02 D2 D3 FF followed by
L
Word 9 FF FF FF FF 127 AL_PA entries)
O
A Word 10 FF FF FF FF
D ... FF FF FF FF
Word 38 FF FF FF FF

Additional Notes
 Loop Initialization 67

LILP Fame passed around the loop

Hard assign
‘D3’ LILP FL LILP
Soft assign
NL ‘01’

NL
Hard assign
‘D2’ NL

FC-AL

Hard assign
Soft assign
‘02’ NL ‘D1’
NL

A single LILP frame gets passed around the loop once.

 Loop Initialization 68

After the LILP Frame passes around

‹ A single CLS (close) is passed around the loop

‹ Each port transitions to Monitoring state

‹ Any suspended operations may resume

‹ Ports may begin arbitration to win control of the loop

‹ Loop Initialization is complete !

A single CLS Primitive Signal is passed around the loop to cause each port to transition to the
Monitoring state.
Once in the Monitoring state, ports can now begin arbitrating to win control of the loop and transmit
and receive frames.
 Loop Initialization 69

Another look

‹ We’ve just completed how initialization occurs when a switch is powered

on

‹ Now let’s take a look at the same loop and see what happens when a
device is added and powered on

‹ Focus is on differences in initialization

Additional Notes
 Loop Initialization 70

Device added to Loop

Hard assign
‘D3’ FL
Soft assign
NL ‘01’
Private NL
Hard assign Public
‘D2’ NL

FC-AL NL (new
Private device)

Hard assign
Soft assign
‘02’ NL ‘D1’
NL

Private
Public

A new host is added to the loop.

 Loop Initialization 71

LIPs – New Port

‹ New port sends continuously to signal loop initialization

‹ Receiving port recognizes when it detects three consecutive LIPs

‹ Port enters Open-Init state and retransmits LIPs to next port

‹ Continues until new port receives three consecutive LIPs

‹ All ports are now in Open-Init state

‹ Normal loop operations are suspended

Powering on the new device will cause LIPs to be issued so loop initialization can begin. The LIP
process works the same as described earlier for the switch being powered on.
 Loop Initialization 72

LISM Frame – New Port

‹ All L_Ports enter a LISM on the loop

‹ The FL_Port sets AL_PA to 00

‹ The NL_Ports set AL_PA to EF

‹ Each L_Port monitors frames received

‹ FL_Port will win loop master

The FL_Port will still win being the loop master.

 Loop Initialization 73

LIFA Frame as it enters the Loop

H Word 0 22 000000
E Word 1 00 000000
A
Word 2 01 380000
D
Word 3 00 00 0000
E
R Word 4 FFFF FFFF
Word 5 00000000
P Word 6 11020000
A
Y Word 7 b’00000000000000000000000000000000’
L
Word 8 b’00000000000000000000000000000000’
O
A Word 9 b’00000000000000000000000000000000’
D
Word 10 b’00000000000000000000000000000000’

Additional Notes
 Loop Initialization 74

LIFA Fame passed around the loop

LIFA FL LIFA
Fabric assign
NL ‘01’
Private NL Public
NL

FC-AL NL (new
Private device)

Fabric assign
‘02’ NL
NL

Private
Public

The two public hosts (AL_PAs ’01’ and ’02’) did a fabric login after the last loop initialization.
They will reclaim there AL_PAs during LIFA.
 Loop Initialization 75

LIFA Frame after passing around the Loop

H Word 0 22 000000
E Word 1 00 000000
A
Word 2 01 380000
D
Word 3 00 00 0000
E
R Word 4 FFFF FFFF
Word 5 00000000
P Word 6 11020000
A
Y Word 7 b’00110000000000000000000000000000’
L
Word 8 b’00000000000000000000000000000000’
O
A Word 9 b’00000000000000000000000000000000’
D
Word 10 b’00000000000000000000000000000000’

AL_PA ’01’ and ’02’ reclaimed by Public hosts

Additional Notes
 Loop Initialization 76

LIPA Frame as it enters the Loop

H Word 0 22 000000
E Word 1 00 000000
A
Word 2 01 380000
D
Word 3 00 00 0000
E
R Word 4 FFFF FFFF
Word 5 00000000
P Word 6 11030000
A
Y Word 7 b’00110000000000000000000000000000’
L
Word 8 b’00000000000000000000000000000000’
O
A Word 9 b’00000000000000000000000000000000’
D
Word 10 b’00000000000000000000000000000000’

Additional Notes
 Loop Initialization 77

LIPA Fame passed around the loop

Previous assign
‘D3’ LIPA FL LIPA
Fabric assign
NL ‘01’
Private NL
Previous assign Public
‘D2’ NL

FC-AL NL (new
Private device)

Previous assign
Fabric assign
‘02’ NL ‘D1’
NL

Private
Public

The three storage devices (AL_PAs ’D1’, ’D2’ and ’D3’) had AL_PAs assigned during the previous
loop initialization. They will reclaim their AL_PAs during LIPA.
 Loop Initialization 78

LIPA Frame after passing around the Loop

H Word 0 22 000000
E Word 1 00 000000
A
Word 2 01 380000
D
Word 3 00 00 0000
E
R Word 4 FFFF FFFF
Word 5 00000000
P Word 6 11030000
A
Y Word 7 b’00110000000000000000000000000000’
L
Word 8 b’00000000000000000000000000000000’
O
A Word 9 b’00000000000000000000000000000000’
D
Word 10 b’00000000000000000111000000000000’

AL_PA ’D1’, ‘D2’ and ’D3’ reclaimed by Private storage

Additional Notes
 Loop Initialization 79

LIHA Frame as it enters the Loop

H Word 0 22 000000
E Word 1 00 000000
A
Word 2 01 380000
D
Word 3 00 00 0000
E
R Word 4 FFFF FFFF
Word 5 00000000
P Word 6 11040000
A
Y Word 7 b’00110000000000000000000000000000’
L
Word 8 b’00000000000000000000000000000000’
O
A Word 9 b’00000000000000000000000000000000’
D
Word 10 b’00000000000000000111000000000000’

Additional Notes
 Loop Initialization 80

LIHA Fame passed around the loop

Previous assign
‘D3’ LIHA FL LIHA
Fabric assign
NL ‘01’
Private NL
Previous assign Public
‘D2’ NL

FC-AL NL (new
Private device)

Previous assign
Fabric assign
‘02’ NL ‘D1’
NL

Private
Public

The new device does not have a hardware preference set.

 Loop Initialization 81

LIHA Frame after passing around the Loop

H Word 0 22 000000
E Word 1 00 000000
A
Word 2 01 380000
D
Word 3 00 00 0000
E
R Word 4 FFFF FFFF
Word 5 00000000
P Word 6 11040000
A
Y Word 7 b’00110000000000000000000000000000’
L
Word 8 b’00000000000000000000000000000000’
O
A Word 9 b’00000000000000000000000000000000’
D
Word 10 b’00000000000000000111000000000000’

No change since AL_PAs for ‘D1’, ‘D2’ and ‘D3’ were reclaimed
during LIPA

Additional Notes
 Loop Initialization 82

LISA Frame as it enters the Loop

H Word 0 22 000000
E Word 1 00 000000
A
Word 2 01 380000
D
Word 3 00 00 0000
E
R Word 4 FFFF FFFF
Word 5 00000000
P Word 6 11050100 or 11050000
A
Y Word 7 b’00110000000000000000000000000000’
L
Word 8 b’00000000000000000000000000000000’
O
A Word 9 b’00000000000000000000000000000000’
D
Word 10 b’00000000000000000111000000000000’

Additional Notes
 Loop Initialization 83

LISA Fame passed around the loop

Previous assign
‘D3’ LISA FL LISA
Fabric assign
NL ‘01’
Private NL
Previous assign Public
‘D2’ NL Soft assign
‘04’
FC-AL NL (new
Private device)

Previous assign
Fabric assign
‘02’ NL ‘D1’
NL

Private
Public

The new device will acquire the next available AL_PA, ’04’.
 Loop Initialization 84

LISA Frame after passing around the Loop

H Word 0 22 000000
E Word 1 00 000000
A
Word 2 01 380000
D
Word 3 00 00 0000
E
R Word 4 FFFF FFFF
Word 5 00000000
P Word 6 11050100 or 11050000
A
Y Word 7 b’00111000000000000000000000000000’
L
Word 8 b’00000000000000000000000000000000’
O
A Word 9 b’00000000000000000000000000000000’
D
Word 10 b’00000000000000000111000000000000’

AL_PA ‘04’ is set for new device

Additional Notes
Loop Initialization 85

LIRP Frame as it enters the Loop

H Word 0 22 000000
E Word 1 00 000000
A
Word 2 01 380000
D
Word 3 00 00 0000
E
R Word 4 FFFF FFFF
Word 5 00000000
P Word 6 11060000
A Word 7 01 00 FF FF (1st byte is offset,
Y
Word 8 FF FF FF FF followed by
L
Word 9 FF FF FF FF 127 AL_PA entries)
O
A Word 10 FF FF FF FF
D ... FF FF FF FF
Word 38 FF FF FF FF

FL_Port is always AL_PA ‘00’

 Loop Initialization 86

LIRP Fame passed around the loop

Previous assign
‘D3’ LIRP FL LIRP
Fabric assign
NL ‘01’
Private NL
Previous assign Public
‘D2’ NL Soft assign
‘04’
FC-AL NL (new
Private device)

Previous assign
Fabric assign
‘02’ NL ‘D1’
NL

Private
Public

Additional Notes
 Loop Initialization 87

LIRP Frame after passing around

H Word 0 22 000000
E Word 1 00 000000
A
Word 2 01 380000
D
Word 3 00 00 0000
E
R Word 4 FFFF FFFF
Word 5 00000000
P Word 6 11060000
A Word 7 07 00 01 04 (1st byte is offset,
Y
Word 8 D1 02 D2 D3 followed by
L
Word 9 FF FF FF FF 127 AL_PA entries)
O
A Word 10 FF FF FF FF
D ... FF FF FF FF
Word 38 FF FF FF FF

Additional Notes
 FC-AL Initialization 88

Review Questions

1. What is the maximum number of devices allowed in a loop?

2. What are the five Loop Initialization steps that occur when a
loop is powered on?

3. What are the difference between the private and public

Arbitrated Loop topology?

4. Which Link Protocol does Arbitrated Loop use?

Write your answers here:

1)

2)

3)

4)