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Oled Technology

The document describes the source code and test benches for three Verilog modules: 1) A 4-bit full adder circuit using smaller full adder modules. 2) A 16-input multiplexer circuit using smaller 2-input mux modules. 3) A module that swaps the values of two 8-bit inputs on alternating clock cycles. Constraint files are also provided to map the design inputs and outputs to FPGA pins.

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surendra parla
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75 views20 pages

Oled Technology

The document describes the source code and test benches for three Verilog modules: 1) A 4-bit full adder circuit using smaller full adder modules. 2) A 16-input multiplexer circuit using smaller 2-input mux modules. 3) A module that swaps the values of two 8-bit inputs on alternating clock cycles. Constraint files are also provided to map the design inputs and outputs to FPGA pins.

Uploaded by

surendra parla
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Set-1

1)sorce code:-

module fullbitadder(
input [3:0] A,
input [3:0] B,
input Cin,
output [3:0] Sum,
output Cout
);
wire c1,c2,c3;
full_adder f0(A[0] , B[0] , Cin , Sum[0] , c1);
full_adder f1(A[1] , B[1] , c1 , Sum[1] , c2);
full_adder f2(A[2] , B[2] , c2 , Sum[2] , c3);
full_adder f3(A[3] , B[3] , c3 , Sum[3] , Cout);
endmodule
//module halfadder
module adder(
input A,
input B,
output S,
output C
);
assign S = A ^ B;
assign C = A & B;

endmodule
TESTBENCH:-
module testbench();
wire [3:0]sum;
wire Cout;
reg [3:0]A;
reg [3:0]B;
reg Cin;
initial begin
A=4'b1000;
B=4'b1010;
Cin=1;
end
fullbitadder f(A,B,Cin,sum,Cout);
endmodule
RTL ANALYSIS:-

CONSTRAINT FILE:-
## Switches
set_property PACKAGE_PIN V17 [get_ports {A[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {A[0]}]
set_property PACKAGE_PIN V16 [get_ports {A[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {A[1]}]
set_property PACKAGE_PIN W16 [get_ports {A[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {A[2]}]
set_property PACKAGE_PIN W17 [get_ports {A[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {A[3]}]
set_property PACKAGE_PIN W15 [get_ports {B[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {B[0]}]
set_property PACKAGE_PIN V15 [get_ports {B[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {B[1]}]
set_property PACKAGE_PIN W14 [get_ports {B[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {B[2]}]
set_property PACKAGE_PIN W13 [get_ports {B[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {B[3]}]
set_property PACKAGE_PIN V2 [get_ports {Cin}]
set_property IOSTANDARD LVCMOS33 [get_ports {Cin}]
## LEDs
set_property PACKAGE_PIN U16 [get_ports {Sum[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Sum[0]}]
set_property PACKAGE_PIN E19 [get_ports {Sum[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Sum[1]}]
set_property PACKAGE_PIN U19 [get_ports {Sum[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Sum[2]}]
set_property PACKAGE_PIN V19 [get_ports {Sum[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Sum[3]}]
set_property PACKAGE_PIN W18 [get_ports {Cout}]
set_property IOSTANDARD LVCMOS33 [get_ports {Cout}]
2) SOURCE CODE:-
module mux(
input I0,
input I1,
input sel,
output reg Y
);
always @(sel,I0,I1)
begin
if(sel==0)
Y = I0;
else
Y = I1;
end
endmodule
module full_16_mux(
input d0,
input d1,
input d2,
input d3,
input d4,
input d5,
input d6,
input d7,
input d8,
input d9,
input d10,
input d11,
input d12,
input d13,
input d14,
input d15,
input [3:0] sel,
output Y
);
wire y1,y2,y3,y4,y5,y6,y7,y8;
wire x1,x2,x3,x4;
wire n1,n2;
mux m1(d0,d1,sel[0],y1);
mux m2(d2,d3,sel[0],y2);
mux m3(d4,d5,sel[0],y3);
mux m4(d6,d7,sel[0],y4);
mux m5(d8,d9,sel[0],y5);
mux m6(d10,d11,sel[0],y6);
mux m7(d12,d13,sel[0],y7);
mux m8(d14,d15,sel[0],y8);
mux m9(y1,y2,sel[1],x1);
mux m10(y3,y4,sel[1],x2);
mux m11(y5,y6,sel[1],x3);
mux m12(y7,y8,sel[1],x4);
mux m13(x1,x2,sel[2],n1);
mux m14(x3,x4,sel[2],n2);
mux m15(n1,n2,sel[3],Y);
endmodule
TESTBENCH:-
module testbench();
reg [3:0] sel;
wire Y;
reg [15:0] d;
initial begin
d = 16'b0101_1010_0101_0101;
sel=4'b0000;
#50 sel=4'b0001;
#50 sel = 4'b0010;
#50 sel = 4'b0011;
#50 sel = 4'b0100;
#50 sel = 4'b0101;
#50 sel = 4'b0110;
#50 sel = 4'b0111;
#50 sel = 4'b1000;
end
full_16_mux
M(d[0],d[1],d[2],d[3],d[4],d[5],d[6],d[7],d[8],d[9],d[10],d[11],d[12],d[13],d[14],d[15],sel,Y);
endmodule
RTL Analysis:-

CONSTRAINT FILE:-
set_property PACKAGE_PIN V17 [get_ports {d0}]
set_property IOSTANDARD LVCMOS33 [get_ports {d0}]
set_property PACKAGE_PIN V16 [get_ports {d1}]
set_property IOSTANDARD LVCMOS33 [get_ports {d1}]
set_property PACKAGE_PIN W16 [get_ports {d2}]
set_property IOSTANDARD LVCMOS33 [get_ports {d2}]
set_property PACKAGE_PIN W17 [get_ports {d3}]
set_property IOSTANDARD LVCMOS33 [get_ports {d3}]
set_property PACKAGE_PIN W15 [get_ports {d4}]
set_property IOSTANDARD LVCMOS33 [get_ports {d4}]
set_property PACKAGE_PIN V15 [get_ports {d5}]
set_property IOSTANDARD LVCMOS33 [get_ports {d5}]
set_property PACKAGE_PIN W14 [get_ports {d6}]
set_property IOSTANDARD LVCMOS33 [get_ports {d6}]
set_property PACKAGE_PIN W13 [get_ports {d7}]
set_property IOSTANDARD LVCMOS33 [get_ports {d7}]
set_property PACKAGE_PIN V2 [get_ports {d8}]
set_property IOSTANDARD LVCMOS33 [get_ports {d8}]
set_property PACKAGE_PIN T3 [get_ports {d9}]
set_property IOSTANDARD LVCMOS33 [get_ports {d9}]
set_property PACKAGE_PIN T2 [get_ports {d10}]
set_property IOSTANDARD LVCMOS33 [get_ports {d10}]
set_property PACKAGE_PIN R3 [get_ports {d11}]
set_property IOSTANDARD LVCMOS33 [get_ports {d11}]
set_property PACKAGE_PIN W2 [get_ports {d12}]
set_property IOSTANDARD LVCMOS33 [get_ports {d12}]
set_property PACKAGE_PIN U1 [get_ports {d13}]
set_property IOSTANDARD LVCMOS33 [get_ports {d13}]
set_property PACKAGE_PIN T1 [get_ports {d14}]
set_property IOSTANDARD LVCMOS33 [get_ports {d14}]
set_property PACKAGE_PIN R2 [get_ports {d15}]
set_property IOSTANDARD LVCMOS33 [get_ports {d15}]
##push buttons as selection pin for multiplexer
set_property PACKAGE_PIN U17 [get_ports {sel[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sel[0]}]
set_property PACKAGE_PIN T17 [get_ports {sel[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sel[1]}]
set_property PACKAGE_PIN T18 [get_ports {sel[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sel[2]}]
set_property PACKAGE_PIN W19 [get_ports {sel[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sel[3]}]
set_property PACKAGE_PIN U16 [get_ports {Y}]
set_property IOSTANDARD LVCMOS33 [get_ports {Y}]
3)
Source code:-
module swap(
input [7:0] A,
input [7:0] B,
input count,
output reg [7:0] C,
output reg [7:0] D
);
always @(count)
begin
if(count == 1)
begin
C <= B;
D <= A;
end
else
begin
C<=A;
D<=B;
end
end
endmodule
TESTBENCH:-
module testbench();
reg [7:0]A;
reg [7:0]B;
reg count;
wire [7:0]C;
wire [7:0]D;
initial begin
A = 25;
B = 30;
count = 0;
#50 count = 1;
#50 count = ~count;
#50 count = ~count;
end
swap swap(A,B,count,C,D);
endmodule
RTL Analysis:-
CONSTRAINT FILE:-
## Switches
set_property PACKAGE_PIN V17 [get_ports {A[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {A[0]}]
set_property PACKAGE_PIN V16 [get_ports {A[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {A[1]}]
set_property PACKAGE_PIN W16 [get_ports {A[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {A[2]}]
set_property PACKAGE_PIN W17 [get_ports {A[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {A[3]}]
set_property PACKAGE_PIN W15 [get_ports {A[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {A[4]}]
set_property PACKAGE_PIN V15 [get_ports {A[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {A[5]}]
set_property PACKAGE_PIN W14 [get_ports {A[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {A[6]}]
set_property PACKAGE_PIN W13 [get_ports {A[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {A[7]}]
set_property PACKAGE_PIN V2 [get_ports {B[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {B[8]}]
set_property PACKAGE_PIN T3 [get_ports {B[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {B[9]}]
set_property PACKAGE_PIN T2 [get_ports {B[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {B[10]}]
set_property PACKAGE_PIN R3 [get_ports {B[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {B[11]}]
set_property PACKAGE_PIN W2 [get_ports {B[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {B[12]}]
set_property PACKAGE_PIN U1 [get_ports {B[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {B[13]}]
set_property PACKAGE_PIN T1 [get_ports {B[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {B[14]}]
set_property PACKAGE_PIN R2 [get_ports {B[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {B[15]}]

## LEDs
set_property PACKAGE_PIN U16 [get_ports {C[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {C[0]}]
set_property PACKAGE_PIN E19 [get_ports {C[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {C[1]}]
set_property PACKAGE_PIN U19 [get_ports {C[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {C[2]}]
set_property PACKAGE_PIN V19 [get_ports {C[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {C[3]}]
set_property PACKAGE_PIN W18 [get_ports {C[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {C[4]}]
set_property PACKAGE_PIN U15 [get_ports {C[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {C[5]}]
set_property PACKAGE_PIN U14 [get_ports {C[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {C[6]}]
set_property PACKAGE_PIN V14 [get_ports {C[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {C[7]}]
set_property PACKAGE_PIN V13 [get_ports {D[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {D[8]}]
set_property PACKAGE_PIN V3 [get_ports {D[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {D[9]}]
set_property PACKAGE_PIN W3 [get_ports {D[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {D[10]}]
set_property PACKAGE_PIN U3 [get_ports {D[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {D[11]}]
set_property PACKAGE_PIN P3 [get_ports {D[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {D[12]}]
set_property PACKAGE_PIN N3 [get_ports {D[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {D[13]}]
set_property PACKAGE_PIN P1 [get_ports {D[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {D[14]}]
set_property PACKAGE_PIN L1 [get_ports {D[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {D[15]}]
##Buttons
set_property PACKAGE_PIN U18 [get_ports count]
set_property IOSTANDARD LVCMOS33 [get_ports count]
4)
Source code:-
module sw_fsm(
input clk,
input rst,
input stp,
input srt,
output reg [3:0] msec,
output reg [3:0] sec0,
output reg [3:0] sec1,
output reg [3:0] min
);
reg [31:0]count = 0;
reg [1:0]state = S0;
reg en = 0;
integer timer = 49;
localparam
S0 = 2'b00,
S1 = 2'b01,
S2 = 2'b10,
S3 = 2'b11;
always@(posedge clk,posedge rst,posedge stp,posedge srt)
begin
case(state)
S0: begin
count = 0;
en = 0;
msec = 0;
sec0 = 0;
sec1 = 0;
min = 0;
if(srt==1)begin
state = S1;
en = 1;
end
end
S1: begin
en = 1;
if(stp==1) begin
en =0;
state = S2;
end

end
S2: begin
en = 0;
if(srt == 1)begin
en = 1;
state = S1;
end
if(rst == 1)begin
en = 0;
state = S0;
count = 0;
end
end
endcase
end
always @ (posedge clk or posedge rst)
begin
if(rst)
count <= 0;
else if(count == timer)
count <= 0;
else if(en)
count <= count + 1;
end

assign click = ((count == timer)?1'b1:1'b0);


always@(posedge clk)
begin
if(rst)
begin
msec <= 0;
sec0 <= 0;
sec1 <= 0;
min <= 0;
end
if (click)
begin
if(msec == 9)
begin //if_1
msec <= 0;
if (sec0== 9) //xx99
begin // if_2
sec0<= 0;
if (sec1 == 5) //x599 - the two digit seconds digits
begin //if_3
sec1 <= 0;
if(min == 9) //9599 - The minute digit
min <= 0;
else
min <= min + 1;
end
else //else_3
sec1 <= sec1 + 1;
end
else //else_2
sec0<= sec0+ 1;
end
else //else_1
msec <= msec + 1;
end
end
endmodule
TESTBENCH:-
module testbench( );
reg clk;
reg stp,rst,srt;
wire [3:0] msec;
wire [3:0] sec0;
wire [3:0] sec1;
wire [3:0] min;
sw_fsm stopwatch(clk,rst,stp,srt,msec,sec0,sec1,min);
initial begin
clk = 0;
stp =0;
rst =0;
srt = 1;
#10
srt = 0;
#400
stp = 1;
#10
stp = 0;
#200
srt = 1;
#10
srt = 0;
#50
rst = 1;
#5
rst = 0;
end
reg [31:0]counter = 0;
always@(*)
begin
while(counter < 100000)begin
#0.2
clk = ~clk;
counter = counter + 1;
end
end
endmodule
RTL Analysis:-

CONSTRAINT FILE:-
## Clock signal
set_property PACKAGE_PIN W5 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
## LEDs
set_property PACKAGE_PIN U16 [get_ports {msec[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {msec[0]}]
set_property PACKAGE_PIN E19 [get_ports {msec[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {msec[1]}]
set_property PACKAGE_PIN U19 [get_ports {msec[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {msec[2]}]
set_property PACKAGE_PIN V19 [get_ports {msec[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {msec[3]}]
set_property PACKAGE_PIN W18 [get_ports {sec0[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sec0[0]}]
set_property PACKAGE_PIN U15 [get_ports {sec0[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sec0[1]}]
set_property PACKAGE_PIN U14 [get_ports {sec0[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sec0[2]}]
set_property PACKAGE_PIN V14 [get_ports {sec0[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sec0[3]}]
set_property PACKAGE_PIN V13 [get_ports {sec1[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sec1[0]}]
set_property PACKAGE_PIN V3 [get_ports {sec1[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sec1[1]}]
set_property PACKAGE_PIN W3 [get_ports {se1[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sec1[2]}]
set_property PACKAGE_PIN U3 [get_ports {sec1[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sec1[3]}]
set_property PACKAGE_PIN P3 [get_ports {min[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {min[0]}]
set_property PACKAGE_PIN N3 [get_ports {min[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {min[1]}]
set_property PACKAGE_PIN P1 [get_ports {min[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {min[2]}]
set_property PACKAGE_PIN L1 [get_ports {min[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {min[3]}]
##Buttons
set_property PACKAGE_PIN U18 [get_ports rst]
set_property IOSTANDARD LVCMOS33 [get_ports rst]
set_property PACKAGE_PIN T18 [get_ports stp]
set_property IOSTANDARD LVCMOS33 [get_ports stp]
set_property PACKAGE_PIN W19 [get_ports srt]
set_property IOSTANDARD LVCMOS33 [get_ports srt]

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