Saving time & money with JTAG

AltiumLive 2017:
ANNUAL PCB
DESIGN SUMMIT
Simon Payne
CEO, XJTAG Ltd.
 JTAG / IEEE 1149.X

Saving time and money with JTAG

 Take-away points

Get JTAG right Use JTAG more Free Stuff!

from the start

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 1 Why JTAG?

I Testability

II Testability and JTAG

2 Use JTAG more – JTAG Programming

3 Getting JTAG right from the start – Free Stuff

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 JTAG – a familiar name

Testing

is not new
JTAG CPU Debug

but it’s still under-

In-Circuit
used Programmin
g

• It can be found in most PCB designs

• JTAG is probably built into the silicon you already use – so if you have it, use
it!
• Make the most of it – if you have it for one purpose, why not use it for all
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 JTAG / Boundary Scan / 1149.x

Designed to minimise access difficulties

• Test Access Port interface is 4/5 signals

• Gives access to the whole device
• JTAG devices connect to form a chain

Abstracted from device and board complexity

• No need to know what type of CPU core, or even

whether the device is a CPU, FPGA, CPLD, RAM, PHY, etc.

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 1 Why JTAG?

I Testability

II Testability and JTAG

2 Use JTAG more – JTAG Programming

3 Getting JTAG right from the start – Free Stuff

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 What is testability?

Measuring testability is complex

• Prepare early
• Test as much as you can
• Test as quickly as you can

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 What is testability?

Testability sounds sensible

• But when you think about it, what does it mean?
• Tested for what?

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 What affects testability?

Testability is about ACCESS

Multiple test methodologies give more complete coverage

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 Test methodologies

Different methodologies have different strengths / weaknesses

Examples:

JTAG

Automated Optical Inspection (AOI)

X-ray

In-Circuit Test (ICT)

Correctness

Shorts

Opens
Alignment

Quality
Orientation
Presence

Live
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 Aside: using different test methodologies

Different methodologies are available at different times

• ICT generally not available in the lab

• X-ray might even involve sending out to a 3rd party
• Benchtop use of JTAG

DESIGN & DEVELOPMENT PRODUCTION & SERVICE

Desig Prototype Hardware Software System Manufacturin Field

n Manufacturing Debug Debug Integration g Updates

3rd Party Test 3rd Party Test

JTAG

AOI FPT X-ray AOI ICT X-ray

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 What affects testability?

JTAG controller
Testability is about ACCESS

• A point of access on a net gives you (some) fault detection

• Multiple points of access give you better detection
and fault diagnosis

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 Better access improves testability

Open-circuit fault diagnosis:

No open detected

Open detected   Open located 

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 Making sure of testability

So – the more access I have, the better?

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 Making sure of testability

Typical design process – where does testability come in?

• If your design will use JTAG for bring-up, testability just got a big boost anyway
– but make sure you don’t throw away the opportunities!

Electronics New Collect Client

NPI Reviews Product
Introduction (NPI)
Requirements

Time-to-Market Schematic
High Volume

• Is testability (and trade-off against speed) Challenges Design

Document
Control

reviewed early enough in your NPI process?

NPI FEEDBACK LOOP

Generate Adjust BOM
PCB Layout
BOM & Netlist for Volume

Netlist Footprint NPI Document Basic DfM & DfA

Associations Control Analysis

Design rules
DfM Analysis Prepare BOM

• Sometimes you simply have to have rules. NPI Document

High Volume
Document
Control
Control

High Volume
PCB Fabrication Prototype Build
Manufacturing

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 Making sure of testability

Design validation
• How?
• What are the most important things to get right?

If only there were some kind of

extension that could help… !

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 1 Why JTAG?

I Testability

II Testability and JTAG

2 Use JTAG more – JTAG Programming

3 Getting JTAG right from the start – Free Stuff

XJTAG.com © Copyright 2017 18

 Testing with JTAG 1149.x

JTAG is unaffected by component density

• The pins of JTAG devices become test points in your circuit

JTAG tests non-JTAG devices

• The JTAG devices provide access to test the PCB

• Particularly useful when the PCB has BGA devices
• Cheaper/quicker/better diagnostics than functional test

JTAG lowers costs

• Simpler fixtures and test setup
• This means it’s available at a lab bench as well as in the factory

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 For those who last saw JTAG 10 years ago…

Ways in which things have moved on…

• JTAG tools aimed at board designers not just production test engineers

• Costs have fallen

• Support for non-JTAG devices has become much easier

• Test scripts rather than test vectors (vectors are auto-generated)
• Code re-use – both within boards and across designs
• Model libraries

• Accelerated in-circuit programming limited only by flash write speed

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 Testing with JTAG 1149.x

The circuit is powered during tests

• Unlike most flying probe / bed-of-nails testers

No firmware is used

• Unlike functional testing

• JTAG device pins are controlled directly

The JTAG signals run at high speed

• Typically around 10 - 30 MHz,
sometimes faster

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 Test fixture cabling

We repeatedly see in test fixtures on JTAG TAP signals:

• Spaghetti wiring
• Poor ground connections

Try:

• Twisted pairs (Ground + signal)

• Or ribbon cables with ground between signals
• Shielded cables

Further reading:
www.xjtag.com/signal-integrity-in-test-fixtures/

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 Testing goes beyond direct access

There are many more non-JTAG devices than JTAG devices on a PCB

• Testing non-JTAG devices is achieved using the JTAG device pins

• Because JTAG devices tend to be major ones (CPU, FPGA, CPLD)
they have access to many peripherals

Access means testability

• This means that from JTAG you can perform tests based on device functionality

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 Testing goes beyond direct access

Examples of functionality-based testing

• Use pins on the JTAG devices to write data to the non-JTAG devices on their nets,
and read return data

• I2C devices
• DDR memory
• Flash
• Many others…

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 What faults can JTAG testing find?

• Shorts between nets with JTAG access

• Shorts to power or ground

• Open-circuit between JTAG devices

• Open-circuit between a pin on a JTAG device

and a testable non-JTAG device

• Missing or non-powered testable devices

• Missing pull resistors

• Faults in logic between JTAG devices or JTAG

and testable non-JTAG devices

• Faults around coupling capacitors (using

1149.6)

• Via functionality-based testing:

huge number of additional faults
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 1 Why JTAG?

I Testability

II Testability and JTAG

2 Use JTAG more – JTAG Programming

3 Getting JTAG right from the start – Free Stuff

XJTAG.com © Copyright 2017 26

 Accelerated Programming

Programming is a pain – it takes time

• It’s a pain in debug

• Uploading new firmware each time you fix a bug

• It’s a pain in the factory

• Throughput matters
• Time on the production line costs money

Plain ‘vanilla’ JTAG is not known for its programming speed, BUT:

Accelerated programming using JTAG is as fast as it gets!

How does this work?

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 Accelerated Programming

Accelerated programming can mean different things

• The PC may download some code to the JTAG controller

to reduce latency/communication between them

• Better solution is to program a device on the board and use that to program the flash
• Embedded s/w program on CPU
• Image for FPGA to configure it as programmer
• Flash image can be loaded via USB/ethernet,
or for an FPGA streamed over the JTAG signals

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 Accelerated Programming

Again – some thought at design stage brings huge benefits later:

• Re-flashing during development becomes quick & easy

• Reduces production line bottlenecks caused by in-system programming

Maybe you have access to flash from an FPGA?

• If not, design in better access to the flash!

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 Accelerated Programming

Acceleration scenarios
Using Microprocessor or FPGA

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 1 Why JTAG?

I Testability

II Testability and JTAG

2 Use JTAG more – JTAG Programming

3 Getting JTAG right from the start – Free Stuff

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 JTAG – getting it right

JTAG comes with some conditions

• You have to connect it
• Laws of physics still apply

• Signal integrity is important

• For test time
• For reliability
• For programming speed

• There may be pins which need to be accessible

• May need access to set the device into JTAG mode

Design and layout of the JTAG signals makes a difference

• Getting it wrong can double (or worse) the time taken to test each PCB

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 Checking connections

Multiple devices connected to form a JTAG Chain

Multiple devices connected to form a JTAG Chain

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 Checking termination

Multiple devices connected to form a JTAG Chain

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 Connector and cable design

• Again, layout makes a huge difference

• Avoid routing TDO next to TCK

• Both on the PCB and in cabling

• Use multiple Ground connections in the cable

• Interleave them if you can

• Don’t forget JTAG mode pins

• Route to header or have some way to set them

• Keep track lengths/buffer delays as similar as possible

• Particularly for TMS and TCK

www.xjtag.com/about-jtag/design-for-test-guidelines

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 Reporting in XJTAG DFT Assistant

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 XJTAG Access Viewer

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Saving time and money
 Saving time and money

Thinking about JTAG at the design stage…

• Get the JTAG chain(s) right – use an extension to verify your board design

• Consider signal integrity for JTAG traces

• Consider improving access to flash devices

• Use DFT analysis from your JTAG software to improve testability

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 Saving time and money

Thinking about JTAG at the design stage…

…brings benefits sooner than you would think:

• Use JTAG to test your prototypes

• Re-use those tests on the production line
• Benefit from the test coverage that JTAG gives you
• Use accelerated JTAG solutions for in-system programming – both for debug and for
production

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 Saving you time and money

Get JTAG right Use JTAG more Make use of the

from the start FREE STUFF!

• Altium Extension
• DFT Guidelines
• Signal Integrity article

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 We’re happy to talk more
Come and visit our table-top stand!