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ATPG LAB3d

The document contains Tcl scripts for generating a scan testbench for a digital design. The scripts set up scan chain insertion, generate test patterns using ATPG, convert the patterns to a stimulus file, compile the design and testbench for simulation, and run the simulation.

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Mani Kandan
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342 views2 pages

ATPG LAB3d

The document contains Tcl scripts for generating a scan testbench for a digital design. The scripts set up scan chain insertion, generate test patterns using ATPG, convert the patterns to a stimulus file, compile the design and testbench for simulation, and run the simulation.

Uploaded by

Mani Kandan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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scan_insert.

tcl

read_file inputs/dig_top_scan_mapped.v -format verilog

set current_design dig_top


link

#compile -scan
#write_file -format verilog -output outputs/dig_top_scan_mapped.v -hierarchy

#set current_design dig_top


#link

set_scan_configuration -style multiplexed_flip_flop


set_dft_signal -view existing_dft -type ScanClock -port clkin -timing [list 40 60]
set_dft_signal -view existing_dft -type ScanClock -port clk_500khz -timing [list 40 60]
set_dft_signal -view existing_dft -type Reset -port reset_n -active_state 0
set_dft_signal -view existing_dft -type TestMode -port test_override -active_state 1
set_dft_signal -view existing_dft -type Constant -port test_override -active_state 1

create_port SCAN_EN -dir IN


set_dft_signal -view spec -type ScanEnable -port SCAN_EN

set_scan_configuration -max_length 50
create_test_protocol

dft_drc -verbose

set_dft_signal -view spec -type TestMode -port test_override -active_state 1


set_dft_configuration -fix_clock enable
set_dft_signal -view spec -type TestData -port clkin
set_autofix_configuration -type clock -control test_override -test_data clkin
preview_dft -test_points all
insert_dft

write_file -format verilog -hierarchy -output outputs/dig_top_scan.v


write_test_protocol -output outputs/dig_top_scan.spf
report_scan_path -chain all > reports/Scan_chains.rpt
report_scan_path -cell all > reports/Scan_cells.rpt

run_tmax.tcl

set_messages -log logs/run_atpg.log -replace


set_build -black_box adc0808
read_netlist /tools/libraries/28nm/SAED32_EDK/lib/pll/verilog/PLL.v -library
read_netlist /tools/libraries/28nm/SAED32_EDK/lib/stdcell_hvt/verilog/saed32nm_hvt.v -library
read_netlist /tools/libraries/28nm/SAED32_EDK/lib/stdcell_lvt/verilog/saed32nm_lvt.v -library
read_netlist /tools/libraries/28nm/SAED32_EDK/lib/stdcell_rvt/verilog/saed32nm.v
read_netlist outputs/dig_top_scan.v
run_build_model dig_top
run_drc outputs/dig_top_scan.spf
set_faults -model Stuck
add_faults -all
report_faults -summary
set_atpg -patterns 100
run_atpg -auto
write_patterns outputs/dig_top_atpg_serial.stil -serial -format stil -replace
write_patterns outputs/dig_top_atpg_parallel.stil -parallel -format stil -replace
report_scan_chains > reports/scan_chains.rpt
report_scan_cells -all > reports/scan_cells.rpt

stil2verilog.tcl

/tools/synopsys/installers/tetramax/bin/stil2verilog outputs/dig_top_atpg_serial.stil
outputs/dig_top_serial_tb -replace

file.f

outputs/dig_top_serial_tb.v
outputs/dig_top_scan_hack.v
/tools/libraries/28nm/SAED32_EDK/lib/pll/verilog/PLL.v
/tools/libraries/28nm/SAED32_EDK/lib/stdcell_hvt/verilog/saed32nm_hvt.v
/tools/libraries/28nm/SAED32_EDK/lib/stdcell_rvt/verilog/saed32nm.v
/tools/libraries/28nm/SAED32_EDK/lib/stdcell_lvt/verilog/saed32nm_lvt.v

gen_simv.tcl

vcs -f scripts/file.f -debug_pp -debug_access+r -full64 -picarchive +v2k +notimingchecks -l


logs/gen_simv.log

run_sim.tcl
./simv +notimingchecks +v2k -gui -i -l logs/sim_lab3d.log

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