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Msem 2011

This document outlines a mid-autumn semester exam for a course on Testing and Verification from IIT Kharagpur. The exam is worth 60 marks and consists of two questions. Question 1 is worth 25 marks and involves proving properties of stuck-at fault testing, showing minimal test sets, and writing Verilog code. Question 2 is worth 35 marks and involves performing Boolean difference analysis, decision tree analysis, controllability/observability analysis, deductive and parallel fault simulation on the circuits shown in Figures 1 and 2.

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Mani Kandan
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27 views

Msem 2011

This document outlines a mid-autumn semester exam for a course on Testing and Verification from IIT Kharagpur. The exam is worth 60 marks and consists of two questions. Question 1 is worth 25 marks and involves proving properties of stuck-at fault testing, showing minimal test sets, and writing Verilog code. Question 2 is worth 35 marks and involves performing Boolean difference analysis, decision tree analysis, controllability/observability analysis, deductive and parallel fault simulation on the circuits shown in Figures 1 and 2.

Uploaded by

Mani Kandan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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Department of Computer Science and Engineering

Indian Institute of Technology, Kharagpur

Course: Testing and Verification (CS60089) Mid-Autumn Semester 2011-12


Time: 2 hours Marks: 60

Answer all the questions

1. Answer the following questions. [5+3+(5+4)+8=25]


(a) Prove that in a tree like circuit consisting of only AND, OR, NAND, NOR and NOT
gates, any test set that detects all stuck-at faults on the primary input lines will detect all
stuck-at faults in the circuit.
(b) Show the minimal test sets for detecting all single stuck-at faults in:
i) A 256-input exclusive-OR gate
ii) An 8-input NAND gate
iii) A 2-to-1 multiplexer (using functional testing approach)
(c) Express the circuit shown in Figure 1 in structural Verilog, and also write a test bench
corresponding to the three input vectors: {00100, 01100, 11100}.
(d) Consider the circuit shown in Figure 2. Show that a test for the fault A/0 in the circuit
cannot be obtained using the five-valued logic of D-calculus. Obtain a test for this fault
using nine-valued logic. (Hint: use two time frames in the expansion)

2. For the circuit shown in Figure 1, perform the following. [5+7+7+8+8=35]


(a) Use the method of Boolean differences to determine all test vectors that detect the faults
h/0 and h/1.
(b) Use the decision tree based approach using the JUSTIFY() and PROPAGATE() functions
to determine the test vector(s) that detect the faults h/0 and h/1.
(c) Using the SCOAP controllability and observability measures, calculate the CC0, CC1 and
CO values of all lines in the circuit.
(d) With the uncollapsed fault list, use deductive fault simulation to determine the faults
detected when the following test vectors are applied in sequence:
T1: 0 0 1 0 0, T2: 0 1 1 0 0 T3: 1 1 1 0 0
(e) Consider the fault list {a/0,m/1,h/1,h1/0,h2/1,n/0,n/1}. Assuming a 8-bit
word size, show the steps of parallel fault simulation using the test vectors:
T1: 0 0 1 0 0, T2: 0 1 1 0 0 T3: 1 1 1 0 0
a m
h1
b h f
c
h2
d g
e n

D Q

B
A

FIGURE 2

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