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Ramdas Mozhikunnath, Experienced Engineer, Co-Author of Cracking Digital What is frontend and backend in VLSI?
VLSI Verification Interviews
Answered Feb 24, 2016 What is the difference between a frontend
developer and a frontend Engineer?
This classification is based on the different steps involved in a typical VLSI
What is the difference between front end and
design flow. Following diagram shows a typical design flow for an ASIC or SOC
back end development?
or any VLSI chip design...
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engineers?
Does frontend engineer offer more opportunities
than backend engineering in the Bay Area?
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As the flow shows, any design starts with specification followed by translating Last Asked 12h ago
the specification to a high level design and then into a low level design. The Edits
high level design involves designing the functional blocks and the
communication protocol between them. The low level design involves
translating into actual modules that contain FSMs, combinational and
sequential circuits etc.
Following by this, the design is modelled using a HDL (Hardware description
language like Verilog/VHDL) which is the RTL coding stage.
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In Functional Verification stage, this HDL model is then verified for
Functional correctness using different Verification methodologies and refined
until the HDL model is proved to be meeting the specifications
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All tasks till this stage is normally called as the Front end of VLSI design
and are executed by Front end Engineers
The next step is to synthesize the HDL model to a target technology to obtain a
gate level design. This step is done normally in collaboration by a front end
design engineer and a back end design engineer who takes this gate level
netlist for further steps till fabrication
All steps after logic synthesis are performed by back end engineers and forms
the back end steps to take this netlist to fabrication of the chip.
This involves Placement and Routing where all the gates and flip-flops are
placed, Clock tree synthesis and reset routing etc. After this each block is
routed, output of the P&R tool is a GDS file, which is used by a foundry for
fabricating the ASIC. Gate level simulations and Static Timing Analysis are also
done to make sure that the gate level design meets the timing requirements for
correct design operations. Further this GDS file is sent to the foundry for
manufacturing.
In terms of future, both front end and back end design steps are equally
important and involves equal but different kinds of challenges for successful
chip designs.
So I cant really distinguish between both and have seen equal opportunities for
both in most of my experience in this industry.
Hope this helps and feel free to let me know any comments/questions.
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Darshan Salgar, B.E from Pune Institute of Computer Technology (2017)
Answered May 6, 2017
The process of modern Integrated circuit design consist of two parts front end
design and back end design
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WORK OF FRONTEND ENGINEER:
1. RTL coding: with help of high level HDL coding (VHDL or verilog ) he designs
the architecture of the chip, a basic skeleton of circuit. It is similar to design a
pipeline to circulate the flow of water.
2.synthesis: synthesis transforms high level verilog/vhdl constructs, which
don't have real physical hardware that can be wired up to do your logic, into low
level logical constructs which can be literally modeled in the form of transistor
logic or look-up tables or other FPGA or ASIC hardware components.
3. verification: HDL model is then verified for Functional correctness using
different Verification methodologies and refined until the HDL model is proved
to be meeting the specifications.
WORK OF BACK END ENGINEER: he deals with further manufacturing and
fabrication process. There he fabricates designs onto silicon dies which are then
packaged into ICs.
1. floorplanning and power planing: the physical design process starts
with floor planning. Where engineer actually works with the core level
circuit. He decides where to place basic blocks and how to route
them,what is power requirements of the circuit and how to utilities it
efficiently.
2. placement: To locate the basic components and efficiently eliminating
any timing constraints.
3. clock tree synthesis: As the circuit may use multiple clock sources such
as PLLs, oscillators etc. so a proper synchronization must be provided.
4. physical verification: After completing the routing process. It is needed
to inspect the process output, physical verification tools are needed to
look for signoff LVS and DRC checks.
Which one has future:
Well it totally depends on what are you good at,because there are many fields in
vlsi chip design in which core knowledge is required.Still for a long run, to work
in back end will give a more challenging and exciting opportunity to know what
is actually going on in the chip inside. Talented back end engineers are in very
good demand ,For coming decade it will generate an exciting opportunity to
build a good career.
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Harshul Mahendroo, studied at Modern Vidya Niketan Aravali Hills (2012)
Answered Oct 30, 2017
VLSI is broadly classified into two parts:- Front end VLSI and Back end VLSI.
Front end mainly deals with the designing and testing part of a digital system or
unit. It uses VHDL, Verilog or other hardware descriptive languages for the
purpose. This includes logical designing and verification, in other words, gate
level work or say RTL level designing and verification is considered.
While Backend VLSI holds mainly the fabrication and development part. This
includes floor planning, place & route, and all the foundry work like fabrication,
packaging etc.
In terms of future, I believe that you will get plenty of career options in both the
sectors. What matters the most, is your area of interest.
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Rakesh Patel, VLSI Engineer at Confidentiality (2016-present)
Answered Sep 15, 2017
VLSI consists of two domain BackEnd and FrontEnd
FrontEnd Engineer is responsible for the creating the RTL which follows the
Behavioural and Functional requirement of the requested design . Frontend
engineers are asked to write a code for the design . verify thhe code and also they
are needed to check the timing in the ideal clock.
Where as A backend Engineer is responsible for implementing the RTL Into the
silicon. they are needed to do the synthesis of the RTL , do the placement of
netlist verify the timing (STA), and make sure that the design will work fine by
after its been manufactured by doing ECO checks .
NOTE:- Correct me if i ma wrong or missing something
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Sougata Bhattacharjee, VLSI Engineer | Experienced with
VHDL/Verilog/C/SV/UVM/TCL |
Answered Apr 3
VLSI frontend and backend are nothing but two different domains in the field of
VLSI.
Frontend mostly deals with Design and Verification of a chip which mostly
includes RTL(Register Transfer Level) coding using either
VHDL/Verilog/SystemVerilog and the verification of the DUT(can be a IP or
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SOC) by building verification Environment or Testbench using
SystemVerilog/UVM/OVM.
The Frontend part also deals with meeting the Please
timing refresh this pageof
constraints tothe
receive
chipnew updates.
using STA(Static Timing Analysis),Synthesizing the design using synthesizable
constructs,Lint run to check for any unwanted or hanging wires and
signals,CDC(Clock Domain Cross) checks to check for any asynchronous path
and Metastability issues.Specific tool knowledge also required.
As you can see from any flow chart of ASIC,starting from Design Specification
Understanding,Functional simulation after writing RTL codes,Logic Synthesis(3
step process as unoptimized description is converted to optimised Boolean
description and then with help of technology library converted to gate level
netlist),Functional/Logic Verification using Testbench language to check
whether the intended input meeting the actual output and STA analysis falls
under Frontend.
Backend mostly deals with physical design part of the chip which includes
Floorplan,Map,Place and route and DFT and ATPG scan insertion and checks for
the flip flops.Also includes physical verification part of the chip,memory
characterization,analog layout and design.Then comes circuit extraction using
SPEF format.
So if you observe the ASIC flow,similar to frontend after STA analysis the
backend flow starts starting from ATPG scan
insertion,DFT,floorplan,backanotation and finally the GDS2 format is released.
Physical design mostly requires the knowledge for CMOS
circuits,Finfet,BJT,RAM and specific tools used for the purpose.
So accordingly you can decide on the basis of your interest as to which one to
choose as both will offer a great deal of learning and good growth.
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