E & C E 2 2 3

E&CE 223
Digital Circuits & Systems

Lecture Transparencies
(Asynchronous Sequential Circuits)

M. Sachdev

216 of 243
Department of Electrical & Computer Engineering, University of Waterloo

E & C E 2 2 3

Section 5

■ Major topics
❍ Secondary variables
❍ Excitation table
❍ Transition table
❍ Race hazard
❍ Cycle and stability
❍ Primitive flow table
❍ Merged flow table
❍ Hazards

217 of 243
Department of Electrical & Computer Engineering, University of Waterloo
 E & C E 2 2 3

Introduction

■ Synchronous, sequential circuit has a synchronizing signal

(clock)
❍ Asynchronous sequential logic has no clock signal
❍ Also known as fundamental mode sequential logic
n m
■ Memory is achieved by Inputs Outputs

❍ Unclocked latches, or Combinational Y1

circuit
❍ Delay elements, or
Y
2
❍ Inherent delay in circuits k
Y
secondary k
variables
(present state) k
yk excitation
Delay variables
(next state)
y
2 Delay
y
1 Delay

218 of 243
Department of Electrical & Computer Engineering, University of Waterloo

E & C E 2 2 3

Definitions

■ The asynchronous circuit is in

❍ Stable state if y i = Y i for all i
❍ Transition state if y i ≠ Y i for all i

■ In analysis and design one normally assumes that the combi-

national circuit is ideal (0 delay) and considers the delays as
lumped delay elements

■ Design restrictions
❍ Normally requires that inputs do not change simultaneously
(i.e., within the settling time of the circuit after an input change)
❍ Hence, input changes only in stable states

■ Excitation table
❍ K map of Yi and outputs in terms of yi and inputs

219 of 243
Department of Electrical & Computer Engineering, University of Waterloo
 E & C E 2 2 3

■ Transition table
❍ Excitation table for Yi with stable states marked
x’
2
■ Flow table x1

❍ Same table as transition table,

x2
but in symbolic form Y1
x1

■ Example: analyze the circuit

x
2
❍ Y2 = x’ 2x1y2 + x 2x1y1 + x 2x’1y’1 x’
1

❍ Y1 = x’ 2x1 +x2y1
❍ x’
2
x
1
Y
2
x2

y1
Delay1

y
2
Delay2

220 of 243
Department of Electrical & Computer Engineering, University of Waterloo

E & C E 2 2 3

Excitation and Transition Table

■ Circle indicates a stable state

❍ Every row has a stable state, x2x1
hence 4 stable states 00 01 11 10
y2y1

■ When y 2 y 1 ≠ Y 2 Y 1 (due to input 00 00 01 00 10

change) a transition to new row
will occur
01 00 01 11 01
■ Example
00 11 11 01
x2x1= Y2y1 = y2y1 = 00 (ini. cond.) 11

x2x1 =00 --> 01 --> 11 --> 10 -->

10 00 11 00 10
00

Y2Y1

221 of 243
Department of Electrical & Computer Engineering, University of Waterloo
 E & C E 2 2 3

y2y1 x2x1 Y2Y1

----------------------------------------
00 00 00 (initial condition)
01 01
---------------------------------------
01 01 01
11 11
---------------------------------------
11 11 11
10 01
---------------------------------------
01 10 01
00 00
---------------------------------------
00 00 00

222 of 243
Department of Electrical & Computer Engineering, University of Waterloo

E & C E 2 2 3

Flow Table

■ Let 00 = a; 01 = b; 11 = c; 01 = d
❍ 00 = a x2x1
❍ 01 = b 00 01 11 10
present
❍ 11 = c state
a a b a d
❍ 01 = d
The resulting flow table is
b a c
b b

a c c b
c

d a c a d

next state

223 of 243
Department of Electrical & Computer Engineering, University of Waterloo
 E & C E 2 2 3

Race Conditions

■ A race condition is caused when two or more binary state var-

iables change value due to change in an input variable
❍ Unequal delays may cause x x
state variables to change in 0 1 0 1
y1y2 y1y2
unpredictable manner
00 00 11 00 00 11
❍ Race condition may be
(i) non- critical, or
01 11 01 01
(ii) critical
11 11 11 11

10 11 10 10

Possible transistions Possible transistions

00 -> 11 00 -> 11
00 -> 01 -> 11 00 -> 01
00 -> 10 -> 11 00 -> 10

non-critical race critical race

224 of 243
Department of Electrical & Computer Engineering, University of Waterloo

E & C E 2 2 3

Stability Consideration

■ Circuit is unstable if it oscillates between two unstable states

❍ Y = (x1y)’x 2 = x’ 1x2 + x 2y’
❍

x x
1 2
00 01 11 10
y
y 0 1 1 0
0
x1 Y
1 0 1 0 0
x
2

225 of 243
Department of Electrical & Computer Engineering, University of Waterloo
 E & C E 2 2 3

Circuits with Latches

Q S R Q Q’
R
1 0 1 0

0 0 1 0

0 1 0 1
Q’
0 0 0 1

S 1 1 0 0

SR
Y 00 01 11 10
R y
0 0 0 0 1

1 1 0 0 1
S
y Delay Y = S + R’y

226 of 243
Department of Electrical & Computer Engineering, University of Waterloo

E & C E 2 2 3

Circuits with Latches

S
S R Q Q’

1 0 0 1
1 1 0 1 (after SR = 10)

0 1 1 0
R 1 1 1 0 (after SR = 01)

0 0 1 1

Delay
SR
00 01 11 10
y
y 1 1 0 0
0
Y
R
1 1 1 1 0
S

Y= S’ + Ry

227 of 243
Department of Electrical & Computer Engineering, University of Waterloo
 E & C E 2 2 3

Analysis Example
x1
R1
Y1

S1
y
2

y Y
1 2
R2

S2
x2

228 of 243
Department of Electrical & Computer Engineering, University of Waterloo

E & C E 2 2 3

Analysis: Transition Table

■ Analysis Procedure for NOR latch based asynchronous circuit

(i) Label each latch o/p with Yi and feed back path with yi
(ii) Derive Boolean functions for Si and Ri
(iii) Check SR = 0 for each NOR latch
(iv) Evaluate Y = S + R’y for each latch
x1x2
(v) Construct the transition 00 01 11 10
table y1y2

(vi) Circle all stable states 00 00 00 01 00

01 01 01 11 11

00 11 11 10
11

10 00 10 11 10

Y1 = S1 + R’1y1 = x1y2 + (x1 + x2)y1 = x1y2 + x1y1 + x2y1

Y2 = S2 + R’2y2 = x1x2 + (x2 +y’1)y2 = x1x2 + x2y2 + y’1y2

229 of 243
Department of Electrical & Computer Engineering, University of Waterloo
 E & C E 2 2 3

Implementation: Example

■ Given the transition table, obtain the sequential circuit with

SR latches
x1x2
00 01 11 10 y Y S R
y
0 0 0 1 0 0 0 X
0
0 1 1 0
1 0 0 1 1 1 0 0 1
1 1 X 0
Y= x1x’2 + x1y

x1x2 x1x2
y 00 01 11 10 y 00 01 11 10

0 0 0 0 1 0 X X X 0

1 0 0 X X 1 1 1 0 0

S = x1x’2 R = x’1

230 of 243
Department of Electrical & Computer Engineering, University of Waterloo

E & C E 2 2 3

Implementation: Procedure

■ Given the transition table, the general procedure for imple-

menting a circuit with SR latches is
(i) Derive a pair of maps for each Si and Ri (i = 1,2, ....k)
(ii) Derive the simplified Boolean function for each Si and Ri
(remember S iRi = 0)
(iii) Draw the logic diagram using k latches

231 of 243
Department of Electrical & Computer Engineering, University of Waterloo
 E & C E 2 2 3

Design Example

■ To design a gated latch

❍ D, data input; G, gating input; Q, the output
❍ Q <-- D if G = 1 and Q retains its previous value if G = 0

■ Gated latch state table

state Inputs Output Comments
D G Q
a 0 1 0 G=1
b 1 1 1 G=1
c 0 0 0 after state a or d
d 1 0 0 after state c
e 1 0 1 after state b or f
f 0 0 1 after state e

232 of 243
Department of Electrical & Computer Engineering, University of Waterloo

E & C E 2 2 3

Gated Latch: Flow Table

DG
00 01 11 10
present
state
a c, - a, 0 b, - -, -

b -, - a, - b, 1 e, -

c c, 0 a, - -, - d, -

d c, - -, - b, - d, 0

e f, - -, - b, - e, 1

f f, 1 a, - -, - e, -

❍ The primitive flow table has only one stable state in each row

233 of 243
Department of Electrical & Computer Engineering, University of Waterloo
 E & C E 2 2 3

Primitive Flow Table Reduction

DG DG
00 01 11 10 00 01 11 10

a c, - a, 0 b, - -, - b -, - a, - b, 1 e, -

c c, 0 a, - -, - d, - e f, - -, - b, - e, 1

d c, - -, - b, - d, 0
f f, 1 a, - -, - e, -

DG
00 01 11 10

a, c, d c, 0 a, 0 b, - d, 0

b, e, f f, 1 a, - b, 1 e, 1

234 of 243
Department of Electrical & Computer Engineering, University of Waterloo

E & C E 2 2 3

Transition Table and Logic Diagram

DG G
00 01 11 10 Q
y Y

0 0 0 1 0 D

1 1 0 1 1

y
Y = DG +G’y

235 of 243
Department of Electrical & Computer Engineering, University of Waterloo
 E & C E 2 2 3

Unstable States

■ Unlike stable states, the unstable states have unspecified out-

puts
❍ Can cause momentary undesirable output

a a, 0 b, - 0 0

b c, - b, 0 X 0

c c, 1 d, - 1 1

d a, - d, 1 X 1

Flow table (given) Output assignment

236 of 243
Department of Electrical & Computer Engineering, University of Waterloo

E & C E 2 2 3

Design procedure for asynchronous

circuits

(i) Obtain a primitive table from specifications

(ii) Reduce flow table by merging rows in the primitive flow table
(iii) Assign binary state variables to each row of reduced table
(iv) Assign output values to dashes associated with unstable states
to obtain the output map
(v) Simplify Boolean functions for excitation and output variables;
(vi) Draw the logic diagram

237 of 243
Department of Electrical & Computer Engineering, University of Waterloo
 E & C E 2 2 3

Systematic reduction of Flow and

State Tables

■ Two techniques:
❍ (i) Implications table, and
❍ (ii) Merger diagram

■ Implication table
❍ Tabulation of possible equivalent states (rows)
❍ Tick for equivalent, and X for not equivalent
❍ Two states, a, b are equivalent iff
(i) outputs are equivalent
(ii) transfers to the same (or equivalent state(s) for given input
sequence

238 of 243
Department of Electrical & Computer Engineering, University of Waterloo

E & C E 2 2 3

Example: Implication Table

■ State table to be reduced

Present Next Output
state state
X=0 X=1 X=0 X=1
a d b 0 0
b e a 0 0
c g f 0 1
d a d 1 0
e a d 1 0
f c b 0 0
g a e 1 0

239 of 243
Department of Electrical & Computer Engineering, University of Waterloo
 E & C E 2 2 3

Example: Implication Table

b d,e

c X X

d X X X

e X X X

c,e X
f c,d X X X X
a,b

g X X X d,e d,e X

a b c d e f

240 of 243
Department of Electrical & Computer Engineering, University of Waterloo

E & C E 2 2 3

Example: Reduced State Table

■ Reduced table
Present Next Output
state state
X=0 X=1 X=0 X=1
a d a 0 0
c d f 0 1
d a d 1 0
f c a 0 0

■ The equivalent states are

❍ (a,b), (d,e), (d,g), (e,g)

■ Hence the reduced states are

❍ (a,b), c, (d,e,g), f

241 of 243
Department of Electrical & Computer Engineering, University of Waterloo
 E & C E 2 2 3

Hazards

■ Unwanted switching transients, “glitches”, that may cause cir-

cuit to malfunction

G
a Y
Q

X G

b b

Y G’

❍ Static 1 hazard

242 of 243
Department of Electrical & Computer Engineering, University of Waterloo

E & C E 2 2 3

■ Glitches are inherent in a digital circuit and can not be elimi-

nated totally
❍ Similarly static 0 hazard can be explained

■ Dynamic hazards
❍ the output changes multiple times instead of 0 -->1 or 1 --> 0
transition

■ Example of a dynamic hazard

243 of 243
Department of Electrical & Computer Engineering, University of Waterloo