EMT 353/3 DIGITAL IC DESIGN
VERILOG BEHAVIOURAL
MODELING
(Part 3)
| SCHOOL OF MICROELECTRONIC ENGINEERING | UniMAP
Contents
Combinational vs. Synchronous logic
Finite State Machine
Moore & Mealy Machine
State Encoding Techniques
Combinational vs. Synchronous
Combinational logic Synchronous Logic
Time independent Time dependent (clock)
Implemented by Boolean Flip-flop elements
circuits Output is the function of
Output is immediate present input and history
function of present input of the input
only Has memory element
No memory element
Finite State Machine (FSM)
Synchronous state machines are one of the
most common building blocks in modern digital
systems
State machines operate at hardware speeds
where software cannot compete
Often engineers take an ad-hoc approach to
design the state machine hence could arise
poorly architecture and also glitches may
appear in the outputs
FSM (Finite State Machine)
FSM could be divided into two types:
Moore Machine
• the outputs only depend on the PRESENT STATE
Mealy Machine
• the outputs depend on both the PRESENT STATE
AND the input variables
FSM: Moore vs Mealy
Moore State Machine
The easiest of the two state machine types
The outputs are combinatorial signals based solely
on the current (present) state
Unfortunately, this can lead to glitches on the
output signals which can cause erratic
(inconsistent) operation of circuitry driven by state
machine
Moore State Machine
zero 0 input
[0]
1
0
name of state
one1
[0]
0
output
1
two1s 1
[1] A Moore ‘’11’
sequence detector
State transition diagram (STD) of Moore machine
Mealy State Machine
The outputs are a function of not only the current
state, but also the inputs
This implementation can lead to timing
problems since the output timing is not simply a
function of the clock, but of the input timing as
well
For this reason, the Mealy architecture is generally
a poor choice for synchronous devices or
designs
Mealy State Machine
0/0 name of state
zero
input
0/0 1/0
output
one1
1/1
A Mealy ’11’
sequence detector
State transition diagram of Mealy machine
Moore vs. Mealy
Ease of design
Moore state machine is easier to design
than Mealy. First design the states depending
on the previous state and input. Then design
output only depending on state.
Whereas in Mealy, you have to consider both
state and input while designing the output
Moore vs. Mealy
Number of states
Mealy state machine uses less states than
the Moore. Since inputs influence the output
in the immediate clock, memory needed to
remember the input is less. So, it uses less
flip-flops and hence circuit is simpler
Mealy vs. Moore
Output / Response
In Mealy, output changes immediately when
the input changes. So, Mealy is faster than
Moore.
Mealy gives immediate response to input and
Moore gives response in the next clock
FSM Behavioural Model
The logic in a state machine described using
‘case’ statement or ‘if-else’ statement
All possible combinations of current state and
inputs are enumerated (listed), and the
appropriate values are specified for next state
and the outputs
FSM Behavioural Model
There are 2 fundamental descriptive style of FSM
Explicit (used often)
• Declares a state register to encode the machine’s
state
Implicit
• Uses multiple event controls (@) within a cyclic
behavior to implicitly describe an evolution of states
• Only good for machines in which a given state can
be reached from only one other state
Styles of FSM (1)
module FSM_style1 (...)
input ...;
output ...;
parameter size = ...;
reg [size-1 : 0] state, next_state;
assign the_outputs = ... // a function of state and
// inputs
assign next_state = ... // a function of state and inputs.
always @ (negedge reset or posedge clk)
if (reset == 1’b0) state <= start_state;
else state <= next_state; // non-blocking assignment
endmodule
Styles of FSM (2)
module FSM_style2 (...)
input ...;
output ...;
parameter size = ...;
reg [size-1 : 0] state, next_state;
assign the_outputs = ... // a function of state and inputs
Cyclic behaviour is used to declare
always @ ( state or the_inputs )
the next-state logic
begin
// decode next_state with ‘case’ or ‘if’ statement
end
always @ (negedge reset or posedge clk)
if (reset == 1’b0) state <= start_state;
else state <= next_state; // Non-blocking or procedural
// assignment
endmodule
Styles of FSM (3)
module FSM_style3 (...)
input ...;
output ...;
parameter size = ...;
reg [size-1 : 0] state, next_state;
always @ ( state or the_inputs )
begin
// decode next_state with case or if statement
end
always @ (negedge reset or posedge clk) Declares output inside the
cyclic block that updates
if (reset == 1’b0) state <= start_state;
the states
else begin
state <= next_state;
outputs <= some_value (inputs, next_state);
end
endmodule
