Microblaze ”soft” IP from Xilinx

Soft IP Core “MicroBlaze”

• Soft Processor Core

– 32-bit - Harvard Bus RISC Architecture
– Size: 1000 Logic Cells
– Speed: 150MHz, 125 MIPS in Virtex-II Pro
– 32 General Purpose Registers; 3 Operand
Instruction Format

• IBM CoreConnnect Bus • GNU Development tools

• Standard Peripheral
set
 Microblaze ”soft” IP from Xilinx

Microblaze 32 RISC softcore

• 32-bit instruction word with three operands and two addressing

modes

• Separate 32-bit instruction and data buses that conform to IBM’s

OPB (On-chip Peripheral Bus) specification

• Separate 32-bit instruction and data buses with direct connection to

on-chip block RAM through a LMB (Local Memory Bus)

• 32-bit address bus

 Microblaze ”soft” IP from Xilinx

Microblaze 32 RISC softcore

• Single issue pipeline

• Instruction and data cache

• FSL (Fast Simplex Link) support

• Hardware multiplier (in Virtex-II and subsequent devices)

 Microblaze ”soft” IP from Xilinx

The MicroBlaze Soft Processor

An Implementation Example

~ 6% of XC3S1000
 Microblaze ”soft” IP from Xilinx

Microblaze Core Blockdiagram

 Microblaze ”soft” IP from Xilinx

General Purpose Registers

Microblaze ”soft” IP from Xilinx
 Microblaze ”soft” IP from Xilinx

Machine Status Register (cont’d)

 Microblaze ”soft” IP from Xilinx

3-stage pipeline
 Microblaze ”soft” IP from Xilinx

Load/Store Architecture

• Microblaze use Big-endian addressing and can access

memory in three data sizes:

1. Byte (8 bits)
2. Halfword (16 bits)
3. Word (32 bits)
 Microblaze ”soft” IP from Xilinx

Big-Endian Data Type

 Microblaze ”soft” IP from Xilinx

Instruction word format

 Microblaze ”soft” IP from Xilinx

Instruction Cache overview

Optional I-cache can be used when executing code residing outside the
LMB address range.

• User selectable cacheable memory area

• Configurable cache size and tag size
• Individual cache line lock capability
• Cache on/off controlled by bit in the MSR register
• Instructions to write to the I-cache
• Doesn’t require any specific memory controller
• Little area (< 20 LUTs) and frequency impact
• Can be used in conjunction with Instruction side LMB
 Microblaze ”soft” IP from Xilinx

Data Cache overview

Optional D-cache can be used when accessing data residing outside the
LMB address range.

• Write through policy

• User selectable cacheable memory area
• Configurable cache size and tag size
• Individual cache line lock capability
• Cache on/off controlled by bit in the MSR register
• Instructions to write to the D-cache
• Doesn’t require any specific memory controller
• Little area (< 20 LUTs) and frequency impact
• Can be used in conjunction with Data side LMB
 Microblaze ”soft” IP from Xilinx

Microblaze 32 RISC softcore – Bus

interfaces
• OPB (On-chip Peripheral Bus) bus interface with byte-enable support

• LMB (Local Memory Bus) provides simple synchronous protocol for

efficient block RAM transfers.

• LMB provides guaranteed performance of 125 MHz for local memory

subsystem.

• FSL (Fast Simplex Links) provides a fast non-arbitrated streaming

communication mechanism.
 Microblaze ”soft” IP from Xilinx

Six different bus configurations

 Microblaze ”soft” IP from Xilinx

Use this configuration when the application

requires more instruction and data memory
than is available in the on-chip block RAM
(BRAM). Critical sections of instruction
memory can be allocated to the faster ILMB
BRAM to improve the application’s
performance.
 Microblaze ”soft” IP from Xilinx

In this configuration, all of the instruction

memory
is resident in off-chip memory
 Microblaze ”soft” IP from Xilinx

Use this configuration when your application

code fits into the on-chip BRAM, but more
memory may be required for data memory.
 Microblaze ”soft” IP from Xilinx

Use this configuration when the application

requires more instruction and data memory
than is available in the on-chip BRAM. Critical
sections of instruction memory can be
allocated to the faster ILMB BRAM to
improve the application’s performance.
 Microblaze ”soft” IP from Xilinx

Use this configuration when the application

requires external instruction and data
memory. In this configuration, all of the
instruction and data memory is resident in
off-chip
memory.
 Microblaze ”soft” IP from Xilinx

Use this configuration when your application

code fits into the on-chip ILMB BRAM, but
more memory may be required for data
memory.
 Microblaze ”soft” IP from Xilinx

Microblaze 32 RISC softcore- FSL :

Fast Simplex Links
 Microblaze ”soft” IP from Xilinx

The Designer’s Challenge

• How to partition between HW and SW to get the best cost and

performance ?

– Hardware is fast and cost grows with complexity

– Software is inexpensive and performance degrades with
complexity
– Some functions are naturally meant to be implemented in
processors
 Microblaze ”soft” IP from Xilinx

Accelerating Software Example:

Inverse Discrete Cosine Transform

• A typical software development starts as 100% “C”

• Performance profiling determines the critical paths

– IDCT function is in the critical path

– The system requirements are off by an order of magnitude

 Microblaze ”soft” IP from Xilinx

If All Code is Run in Software...

Main Software IDCT
Calling IDCT Function Software Library
#include "mb_interface.h"
xil_idct (int *indata, int *outdata) {
int main() { int i, j, k;
int indata[8], outdata[8]; int sum;
...
xil_idct (indata, outdata); for (j = 0; j < 8; j++) {
... sum = 0;
} for (i = 0; i < 8; i++)
sum += (indata[i] * idct_constants[j][i]);

outdata[j] = (sum >> 2);

outdata[j] = (int) DESCALE (outdata[j], 10);
}

• Entire IDCT function takes 1144 clock cycles to execute

• 896 clock cycles (14*64) reside in the inner loop

 Microblaze ”soft” IP from Xilinx
“Xtreme Processing Acceleration”
( Xilinx )
Main Software
OPB PCI
Calling IDCT Function FSL
Ports

#include "mb_interface.h"
FSL
Option 1:
Use small (200 LUTs)
int main() {
Ports
int indata[8], outdata[8];
…
IDCT Logic
implementation of IDCT in
xil_idct_hw(indata, outdata);
…

HW
}
IDCT Logic
void xil_idct_hw(int indata[8], int outdata[8] {

– only 107 clock cycles

microblaze_bwrite_datafsl (indata[0], 0);
microblaze_bwrite_datafsl (indata[1], 0);
microblaze_bwrite_datafsl (indata[2], 0);
microblaze_bwrite_datafsl (indata[3], 0);
microblaze_bwrite_datafsl (indata[4], 0); – 10x faster
microblaze_bread_datafsl (outdata[0], 0);
microblaze_bread_datafsl (outdata[1], 0); IDCT Function in HW Option 2:
Use fast (1,600 LUTs)
microblaze_bread_datafsl (outdata[2], 0);
microblaze_bread_datafsl (outdata[3], 0);
microblaze_bread_datafsl (outdata[4], 0); through FSL
}
implementation of IDCT in
HW
– only 52 clock cycles
– 22x faster
 Microblaze ”soft” IP from Xilinx
MicroBlaze FSL Accelerates System Performance

Processor(s) and HW on a single programmable platform

C++ Code Stack
Parallel HW Acceleration
Control Tasks 0 1 2 3 n

FSL
IDCT Function
+ + + +

Control Tasks

Xtreme
IDCT Function Processing
Control Tasks Traditional IDCT Function IDCT Function

Processing time
 Microblaze ”soft” IP from Xilinx

Microblaze 32 RISC softcore- FSL :

Fast Simplex Links
FSL Read Instructions

Blocking Data Get Instruction: Blocking Control Get Instruction:

get regM, fslN cget regM, fslN

Non-blocking Data Get Instruction: Non-blocking Control Get Instruction:

nget regM, fslN ncget regM, fslN
 Microblaze ”soft” IP from Xilinx

FSL Write Instructions

Blocking Data Put Instruction: Blocking Control Put Instruction

put regM, fslN cput regM, fslN

Non-blocking Data Put Instruction: Non-blocking Data Put Instruction:

nput regM, fslN ncput regM, fslN
 Microblaze ”soft” IP from Xilinx

Microblaze 32 RISC softcore - Full

documentation
Full Microblaze documentation can be found at :

www.xilinx.com/ise/embedded/mb_ref_guide.pdf

Also in the lab: Start -> Programs -> Embedded Development

Kit 8.2i -> Documentation

And: Use the ”Help” button in EDK !