Comm-04-Phase and Frequency Modulation
Comm-04-Phase and Frequency Modulation
2
Introduction
3
Cyclic Redundancy Code (CRC)
4
Cyclic Redundancy Code (CRC)
5
Cyclic Redundancy Code (CRC)
6
Linear Block Codes
7
Vector Spaces
◊ A subset S of Vn is a subspace if
◊ The all-zero vector is in S
◊ The sum of any two vectors in S is also in S.
S
◊ Example of S: V 0 = 0000
V 1 = 0101
V 2 = 1010
V 3 = 1111
9
Reducing Encoding Complexity
10
Reducing Encoding Complexity
11
Generator Matrix
14
Parity Check Matrix
⎢ ⎥ ⎢ ⎥
⎢ ⎥ ⎢ ⎥
⎣⎢ ( n − k ) ⎥⎦ ⎢⎣h( n − k )1
h h( n − k ) 2 h( n − k ) n ⎥⎦
u = u1 , u2 ,… , un
uH T = u1hi1 + u2 hi 2 + + un hin = 0
where i = 1,2, …, n − k
◊ U iss a code word
wo d ge
generated
e ed by matrix G if and y if uuHT=0
d oonly
15
Parity Check Matrix and Syndrome
⎧= 0 If r is a code vector
◊ Syndrome s ⎨
⎩≠ 0 Otherwise
16
Example of Syndrome Test
⎡ ⎤ H = [ I n−k PT ]
⎢1 1 0 1 0 0⎥
⎢ ⎥
◊ G = ⎢0 1 1 0 1 0 ⎥ ⎡1 0 0 1 0 1⎤
⎢1 0 1 0 0 1⎥ H = ⎢⎢0 1 0 1 1 0⎥⎥
⎢⎣ ⎥
P Ik ⎦ ⎢⎣0 0 1 0 1 1⎥⎦
◊ The 66-tuple
tuple 1 0 1 1 1 0 is the code vector corresponding to the
message 1 1 0. ⎡1 0 0⎤
⎢0 1 0⎥⎥
⎢
⎢0 0 1⎥
s = u ⋅ H = [1 0 1 1 1 0]• ⎢
T
⎥ = [0 0 0]
⎢1 1 0⎥
⎢0 1 1⎥
⎢ ⎥
⎣⎢1 0 1⎥⎦
◊ Compute
Co pu e thee syndrome
sy d o e for
o thee non-code-vector
o code vec o 0 0 1 1 1 0
s = [0 0 1 1 1 0]• H T = [1 0 0]
17
Weight and Distance of Binary Vectors
18
Minimum Distance of a Linear Code
dmin=3
20
Example of Error Correction and Detection Capability
u v
d min (u , v ) = 7
⎢ d min − 1⎥
t max =⎢ ⎥ : E
Error C
Correcting
i S
Strength
h
⎣ 2 ⎦
1 2 K
1 2 k 1 2 k 1 2 k
k bits
+ 1 + 2 + n-1 + n
Output
22
Convoltuional Code
◊ Convolutional codes
◊ k = number
b off bits
bit shifted
hift d into
i t the
th encoder
d att one time
ti
◊ k=1 is usually used!!
◊ n = number of encoder output bits corresponding to the k
information bits
◊ r = k/n = code rate
◊ K = constraint length, encoder memory
◊ Each encoded bit is a function of the present input bits and
their past ones.
23
Generator Sequence
◊ u
r0 r1 r2 v
g (1)
0 = 1, g(1)
1 = 0, g (1)
2 = 1, and
d g (1)
3 = 1.
Generator Sequence:
q g(1)=(1
( 0 1 1))
◊
u
r0 r1 r2 r3 v
g 0( 2 ) = 1, g1( 2 ) = 1, g 2( 2 ) = 1, g 3( 2 ) = 0, and g 4( 2 ) = 1.
G
Generator
t Sequence:
S g(2)=(1
(1 1 1 0 1)
24
Convolutional Codes
An Example – (rate=1/2 with K=2)
G1(x)=1+x2 0(00)
G2(x)=1+x1+x2
x1 x2
00
0(11) 1(11)
Present Next Output
0(01)
0 00 00 00 01 10
1(00)
1 00 10 11
0 01 00 11 0(10) 1(10)
1 01 10 00 11
0 10 01 01
1 10 11 10
1(01)
0 11 01 10
State Diagram
1 11 11 01
25
Trellis Diagram Representation
Trellis termination: K tail bits with value 0 are usually added to the end of the code.
26
Encoding Process
Input: 1 0 1 1 1 0 0
Output: 11 01 00 10 01 10 11
27
Viterbi Decoding Algorithm
ML
received sequence r detected sequence d
min(d,r) !!
28
Viterbi Decoding Algorithm
◊ Basic concept
◊ Generate
G t th
the code
d ttrellis
lli att the
th decoder
d d
◊ The decoder penetrates through the code trellis level by level in
search for the transmitted code sequence
◊ At each level of the trellis, the decoder computes and compares
the metrics of all the partial paths entering a node
◊ The decoder stores the partial path with the larger metric and
eliminates all the other partial paths. The stored partial path is
called the survivor.
29
Viterbi Decoding Algorithm
Output: 11 01 00 10 01 10 11
Receive: 11 11 00 10 01 11 11
0(00) 0(00) 0(00) 0(00) 0(00)
00 00 00 00 0(00) 00 0(00) 00 00 00
2
01 01 01 01 01
10 10 10 10 10
0
30
Viterbi Decoding Algorithm
Output: 11 01 00 10 01 10 11
Receive: 11 11 00 10 01 11 11
0(00) 0(00) 0(00) 0(00) 0(00)
00 00 00 00 0(00) 00 0(00) 00 00 00
2 4
01 01 01 01 01
1
10 10 10 10 10
0 2
Output: 11 01 00 10 01 10 11
Receive: 11 11 00 10 01 11 11
0(00) 0(00) 0(00) 0(00) 0(00)
00 00 00 00 0(00) 00 0(00) 00 00 00
2 4 3
01 01 01 01 01
1 2
10 10 10 10 10
0 2 1
Output: 11 01 00 10 01 10 11
Receive: 11 11 00 10 01 11 11
0(00) 0(00) 0(00) 0(00) 0(00)
00 00 00 00 0(00) 00 0(00) 00 00 00
2 4 3 3
01 01 01 01 01
1 2 2
10 10 10 10 10
0 2 1 3
Output: 11 01 00 10 01 10 11
Receive: 11 11 00 10 01 11 11
0(00) 0(00) 0(00) 0(00) 0(00)
00 00 00 00 0(00) 00 0(00) 00 00 00
2 4 3 3 3
01 01 01 01 01
1 2 2 3
10 10 10 10 10
0 2 1 3 3
Output: 11 01 00 10 01 10 11
Receive: 11 11 00 10 01 11 11
0(00) 0(00) 0(00) 0(00) 0(00)
00 00 00 00 0(00) 00 0(00) 00 00 00
2 4 3 3 3 3
01 01 01 01 01
1 2 2 3 2
10 10 10 10 10
0 2 1 3 3
Output: 11 01 00 10 01 10 11
Receive: 11 11 00 10 01 11 11
0(00) 0(00) 0(00) 0(00) 0(00)
00 00 00 00 0(00) 00 0(00) 00 00 00
2 4 3 3 3 3 2
01 01 01 01 01
1 2 2 3 2
10 10 10 10 10
0 2 1 3 3
Decision:11 01 00 10 01 10 11
Receive: 11 11 00 10 01 11 11
0(00) 0(00) 0(00) 0(00) 0(00)
00 00 00 00 0(00) 00 0(00) 00 00 00
2 4 3 3 3 3 2
01 01 01 01 01
1 2 2 3 2
10 10 10 10 10
0 2 1 3 3